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DE69332857D1 - Halbleitervorrichtung. - Google Patents

Halbleitervorrichtung.

Info

Publication number
DE69332857D1
DE69332857D1 DE69332857T DE69332857T DE69332857D1 DE 69332857 D1 DE69332857 D1 DE 69332857D1 DE 69332857 T DE69332857 T DE 69332857T DE 69332857 T DE69332857 T DE 69332857T DE 69332857 D1 DE69332857 D1 DE 69332857D1
Authority
DE
Germany
Prior art keywords
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69332857T
Other languages
English (en)
Other versions
DE69332857T2 (de
Inventor
Tadashi Shibata
Tadahiro Ohmi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Application granted granted Critical
Publication of DE69332857D1 publication Critical patent/DE69332857D1/de
Publication of DE69332857T2 publication Critical patent/DE69332857T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • Evolutionary Computation (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Computational Linguistics (AREA)
  • General Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Artificial Intelligence (AREA)
  • Neurology (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Measurement Of Current Or Voltage (AREA)
DE69332857T 1992-07-29 1993-07-29 Halbleitervorrichtung. Expired - Fee Related DE69332857T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP22216692A JP3421365B2 (ja) 1992-07-29 1992-07-29 半導体装置
JP22216692 1992-07-29
PCT/JP1993/001071 WO1994003929A1 (en) 1992-07-29 1993-07-29 Semiconductor device

Publications (2)

Publication Number Publication Date
DE69332857D1 true DE69332857D1 (de) 2003-05-15
DE69332857T2 DE69332857T2 (de) 2004-02-05

Family

ID=16778214

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69332857T Expired - Fee Related DE69332857T2 (de) 1992-07-29 1993-07-29 Halbleitervorrichtung.

Country Status (5)

Country Link
US (1) US5521858A (de)
EP (1) EP0653793B1 (de)
JP (1) JP3421365B2 (de)
DE (1) DE69332857T2 (de)
WO (1) WO1994003929A1 (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5764081A (en) * 1991-05-17 1998-06-09 Theseus Logic, Inc. Null convention interface circuits
US5664211A (en) * 1993-06-08 1997-09-02 Theseus Research, Inc. Null convention threshold gate
US5796962A (en) * 1991-05-17 1998-08-18 Theeus Logic Null convention bus
US5656948A (en) * 1991-05-17 1997-08-12 Theseus Research, Inc. Null convention threshold gate
US6020754A (en) * 1991-05-17 2000-02-01 Theseus Logic, Inc. Look up table threshold gates
AU670241B2 (en) * 1991-05-17 1996-07-11 Theseus Logic, Inc. Null convention speed independent logic
US5930522A (en) * 1992-02-14 1999-07-27 Theseus Research, Inc. Invocation architecture for generally concurrent process resolution
JP3278080B2 (ja) * 1993-02-22 2002-04-30 直 柴田 半導体集積回路
JP3459017B2 (ja) * 1993-02-22 2003-10-20 直 柴田 半導体装置
US5652902A (en) * 1993-06-08 1997-07-29 Theseus Research, Inc. Asynchronous register for null convention logic systems
US5793662A (en) * 1993-06-08 1998-08-11 Theseus Research, Inc. Null convention adder
JP3289749B2 (ja) * 1993-12-02 2002-06-10 直 柴田 半導体集積回路
US6327607B1 (en) 1994-08-26 2001-12-04 Theseus Research, Inc. Invocation architecture for generally concurrent process resolution
EP0774726A1 (de) * 1995-11-03 1997-05-21 STMicroelectronics S.r.l. Vorrichtung zum Selektieren von analogen Spannungssignalen
DE19548529C1 (de) * 1995-12-22 1997-04-03 Siemens Ag Verfahren zur Herstellung eines Neuron-MOS-Transistors auf der Basis eines CMOS-Prozesses
US5917960A (en) * 1996-01-31 1999-06-29 Canon Kabushiki Kaisha Image correlator, an image processing apparatus using the same, and a signal adder used in the image correlator
JPH09229970A (ja) * 1996-02-28 1997-09-05 Sharp Corp 入力検出回路
JPH09245110A (ja) * 1996-03-13 1997-09-19 Tadahiro Omi フィードバック回路
JPH10224224A (ja) * 1997-02-03 1998-08-21 Sunao Shibata 半導体演算装置
JPH10283793A (ja) * 1997-02-06 1998-10-23 Sunao Shibata 半導体回路
JPH10257352A (ja) 1997-03-15 1998-09-25 Sunao Shibata 半導体演算回路
JPH10260817A (ja) 1997-03-15 1998-09-29 Sunao Shibata 半導体演算回路及びデ−タ処理装置
US6150851A (en) * 1997-06-06 2000-11-21 Tadahiro Ohmi Charge transfer amplifier circuit, voltage comparator, and sense amplifier
US5847993A (en) * 1997-06-23 1998-12-08 Xilinx, Inc. Non-volatile programmable CMOS logic cell and method of operating same
JPH1196276A (ja) 1997-09-22 1999-04-09 Sunao Shibata 半導体演算回路
US5907693A (en) * 1997-09-24 1999-05-25 Theseus Logic, Inc. Autonomously cycling data processing architecture
US5986466A (en) * 1997-10-08 1999-11-16 Theseus Logic, Inc. Programmable gate array
US6031390A (en) * 1997-12-16 2000-02-29 Theseus Logic, Inc. Asynchronous registers with embedded acknowledge collection
US6262593B1 (en) 1998-01-08 2001-07-17 Theseus Logic, Inc. Semi-dynamic and dynamic threshold gates with modified pull-up structures
JP3933817B2 (ja) * 1999-06-24 2007-06-20 富士通株式会社 不揮発性メモリ回路
JP3199707B2 (ja) 1999-08-09 2001-08-20 株式会社半導体理工学研究センター 半導体演算回路及び演算装置
JP3226513B2 (ja) 1999-08-09 2001-11-05 株式会社半導体理工学研究センター 演算回路、演算装置、及び半導体演算回路
JP4270832B2 (ja) * 2002-09-26 2009-06-03 株式会社東芝 不揮発性半導体メモリ
KR100823450B1 (ko) * 2006-12-27 2008-04-17 동부일렉트로닉스 주식회사 반도체 소자와 이의 제조 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5055897A (en) * 1988-07-27 1991-10-08 Intel Corporation Semiconductor cell for neural network and the like
US5331215A (en) * 1988-12-09 1994-07-19 Synaptics, Incorporated Electrically adaptable neural network with post-processing circuitry
US5093803A (en) * 1988-12-22 1992-03-03 At&T Bell Laboratories Analog decision network
JPH02281759A (ja) * 1989-04-24 1990-11-19 Sony Corp 半導体装置
JP2662559B2 (ja) * 1989-06-02 1997-10-15 直 柴田 半導体装置
JPH0363996A (ja) * 1989-08-01 1991-03-19 Casio Comput Co Ltd 薄膜トランジスタによるプログラマブル連想メモリ
US5247206A (en) * 1992-03-12 1993-09-21 Intel Corporation Neural network accommodating parallel synaptic weight adjustments in a single cycle
US5336936A (en) * 1992-05-06 1994-08-09 Synaptics, Incorporated One-transistor adaptable analog storage element and array
US5336937A (en) * 1992-08-28 1994-08-09 State University Of New York Programmable analog synapse and neural networks incorporating same

Also Published As

Publication number Publication date
DE69332857T2 (de) 2004-02-05
JPH0653431A (ja) 1994-02-25
JP3421365B2 (ja) 2003-06-30
WO1994003929A1 (en) 1994-02-17
EP0653793B1 (de) 2003-04-09
EP0653793A4 (de) 1997-03-19
EP0653793A1 (de) 1995-05-17
US5521858A (en) 1996-05-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee