[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

DE69027832D1 - Feld-Effekt-Transistor mit Gate-Abstandsstück - Google Patents

Feld-Effekt-Transistor mit Gate-Abstandsstück

Info

Publication number
DE69027832D1
DE69027832D1 DE69027832T DE69027832T DE69027832D1 DE 69027832 D1 DE69027832 D1 DE 69027832D1 DE 69027832 T DE69027832 T DE 69027832T DE 69027832 T DE69027832 T DE 69027832T DE 69027832 D1 DE69027832 D1 DE 69027832D1
Authority
DE
Germany
Prior art keywords
field
effect transistor
gate spacer
spacer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69027832T
Other languages
English (en)
Other versions
DE69027832T2 (de
Inventor
Kuo-Hua Lee
Chih-Yuan Lu
Janmye Sung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of DE69027832D1 publication Critical patent/DE69027832D1/de
Application granted granted Critical
Publication of DE69027832T2 publication Critical patent/DE69027832T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69027832T 1989-10-17 1990-10-10 Feld-Effekt-Transistor mit Gate-Abstandsstück Expired - Fee Related DE69027832T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/422,834 US5153145A (en) 1989-10-17 1989-10-17 Fet with gate spacer

Publications (2)

Publication Number Publication Date
DE69027832D1 true DE69027832D1 (de) 1996-08-22
DE69027832T2 DE69027832T2 (de) 1996-11-28

Family

ID=23676607

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69027832T Expired - Fee Related DE69027832T2 (de) 1989-10-17 1990-10-10 Feld-Effekt-Transistor mit Gate-Abstandsstück

Country Status (6)

Country Link
US (2) US5153145A (de)
EP (1) EP0424019B1 (de)
JP (1) JPH03139847A (de)
DE (1) DE69027832T2 (de)
ES (1) ES2088985T3 (de)
HK (1) HK179796A (de)

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW203148B (de) * 1991-03-27 1993-04-01 American Telephone & Telegraph
US5424234A (en) * 1991-06-13 1995-06-13 Goldstar Electron Co., Ltd. Method of making oxide semiconductor field effect transistor
JP3144056B2 (ja) * 1992-05-08 2001-03-07 ヤマハ株式会社 薄膜トランジスタの製法
KR100260577B1 (ko) * 1992-09-09 2000-08-01 김영환 자기정렬형 콘택 형성방법
US5312768A (en) * 1993-03-09 1994-05-17 Micron Technology, Inc. Integrated process for fabricating raised, source/drain, short-channel transistors
KR0171732B1 (ko) * 1993-11-26 1999-03-30 김주용 모스 트랜지스터 및 그 제조방법
US5420057A (en) * 1994-06-30 1995-05-30 International Business Machines Corporation Simplified contact method for high density CMOS
KR0172273B1 (ko) * 1995-06-24 1999-02-01 김주용 플래쉬 메모리 셀의 제조방법
US5783475A (en) * 1995-11-13 1998-07-21 Motorola, Inc. Method of forming a spacer
US5714413A (en) 1995-12-11 1998-02-03 Intel Corporation Method of making a transistor having a deposited dual-layer spacer structure
JP2894283B2 (ja) * 1996-06-27 1999-05-24 日本電気株式会社 半導体装置の製造方法
US5739066A (en) * 1996-09-17 1998-04-14 Micron Technology, Inc. Semiconductor processing methods of forming a conductive gate and line
US5766969A (en) * 1996-12-06 1998-06-16 Advanced Micro Devices, Inc. Multiple spacer formation/removal technique for forming a graded junction
US5869879A (en) * 1996-12-06 1999-02-09 Advanced Micro Devices, Inc. CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions
JPH10173177A (ja) * 1996-12-10 1998-06-26 Mitsubishi Electric Corp Ｍｉｓトランジスタの製造方法
US5895955A (en) * 1997-01-10 1999-04-20 Advanced Micro Devices, Inc. MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch
US5793089A (en) * 1997-01-10 1998-08-11 Advanced Micro Devices, Inc. Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon
US5817562A (en) * 1997-01-24 1998-10-06 Taiwan Semiconductor Manufacturing Company, Ltd Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC)
FR2760130B1 (fr) * 1997-02-25 1999-07-02 Sgs Thomson Microelectronics Transistor mos a faible resistance de drain
TW312810B (en) * 1997-03-17 1997-08-11 United Microelectronics Corp The manufacturing method for LDD forming in MOS device
TW339470B (en) * 1997-09-01 1998-09-01 United Microelectronics Corp The manufacturing method for spacer
US5879993A (en) * 1997-09-29 1999-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride spacer technology for flash EPROM
US6087234A (en) * 1997-12-19 2000-07-11 Texas Instruments - Acer Incorporated Method of forming a self-aligned silicide MOSFET with an extended ultra-shallow S/D junction
US6001690A (en) * 1998-02-13 1999-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming flash EPROM by using iso+aniso silicon nitride spacer etching technology
EP0951061A3 (de) * 1998-03-31 2003-07-09 Interuniversitair Microelektronica Centrum Vzw Verfahren zur Herstellung von einem FET
US6124610A (en) * 1998-06-26 2000-09-26 Advanced Micro Devices, Inc. Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant
US5998248A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region
US6022771A (en) * 1999-01-25 2000-02-08 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions
US5998273A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions
US6025242A (en) * 1999-01-25 2000-02-15 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation
TW408354B (en) * 1999-03-02 2000-10-11 United Microelectronics Corp Structure of field effect transistor and its manufacture method
US6228730B1 (en) * 1999-04-28 2001-05-08 United Microelectronics Corp. Method of fabricating field effect transistor
US6355527B1 (en) * 1999-05-19 2002-03-12 Taiwan Semiconductor Manufacturing Company Method to increase coupling ratio of source to floating gate in split-gate flash
US6472283B1 (en) * 1999-09-24 2002-10-29 Advanced Micro Devices, Inc. MOS transistor processing utilizing UV-nitride removable spacer and HF etch
US6156598A (en) * 1999-12-13 2000-12-05 Chartered Semiconductor Manufacturing Ltd. Method for forming a lightly doped source and drain structure using an L-shaped spacer
US6864143B1 (en) * 2000-01-24 2005-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate bridging between gate and source/drain in cobalt salicidation
US6346468B1 (en) 2000-02-11 2002-02-12 Chartered Semiconductor Manufacturing Ltd. Method for forming an L-shaped spacer using a disposable polysilicon spacer
JP3501107B2 (ja) * 2000-06-19 2004-03-02 セイコーエプソン株式会社 半導体装置の製造方法
US6506650B1 (en) * 2001-04-27 2003-01-14 Advanced Micro Devices, Inc. Method of fabrication based on solid-phase epitaxy for a MOSFET transistor with a controlled dopant profile
DE10222867B4 (de) * 2001-05-23 2009-01-22 Promos Technologies, Inc. Verfahren der Verwendung von Opferabstandsstücken (Spacers) zur Verringerung des Kurzkanaleffekts
JP3418383B2 (ja) * 2001-05-31 2003-06-23 沖電気工業株式会社 半導体装置の製造方法
US6764912B1 (en) 2001-08-02 2004-07-20 Advanced Micro Devices, Inc. Passivation of nitride spacer
US6784506B2 (en) 2001-08-28 2004-08-31 Advanced Micro Devices, Inc. Silicide process using high K-dielectrics
KR100395878B1 (ko) * 2001-08-31 2003-08-25 삼성전자주식회사 스페이서 형성 방법
US7256113B1 (en) 2001-12-14 2007-08-14 Advanced Micro Devices, Inc. System for forming a semiconductor device and method thereof
US6881616B1 (en) * 2001-12-14 2005-04-19 Advanced Micro Devices, Inc. System for forming a semiconductor device and method thereof including implanting through a L shaped spacer to form source and drain regions
US6696345B2 (en) * 2002-01-07 2004-02-24 Intel Corporation Metal-gate electrode for CMOS transistor applications
US6723609B2 (en) * 2002-02-04 2004-04-20 United Microelectronics Corp. Method of preventing leakage current of a metal-oxide semiconductor transistor
US6664156B1 (en) * 2002-07-31 2003-12-16 Chartered Semiconductor Manufacturing, Ltd Method for forming L-shaped spacers with precise width control
US6911695B2 (en) * 2002-09-19 2005-06-28 Intel Corporation Transistor having insulating spacers on gate sidewalls to reduce overlap between the gate and doped extension regions of the source and drain
CN100383935C (zh) * 2002-11-22 2008-04-23 南亚科技股份有限公司 源极/漏极元件的制造方法
KR100517555B1 (ko) * 2003-01-02 2005-09-28 삼성전자주식회사 살리사이드층을 포함하는 반도체 소자 및 그 제조방법
JP2004281631A (ja) * 2003-03-14 2004-10-07 Renesas Technology Corp 半導体装置の設計方法
CN1591823A (zh) * 2003-08-27 2005-03-09 上海宏力半导体制造有限公司 增加集成电路构装密度的制造方法
US20050212015A1 (en) * 2004-03-25 2005-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Metal gate semiconductor device and manufacturing method
US7705385B2 (en) * 2005-09-12 2010-04-27 International Business Machines Corporation Selective deposition of germanium spacers on nitride
US7759206B2 (en) * 2005-11-29 2010-07-20 International Business Machines Corporation Methods of forming semiconductor devices using embedded L-shape spacers
KR100772833B1 (ko) * 2006-07-21 2007-11-01 동부일렉트로닉스 주식회사 반도체 소자 및 반도체 소자의 제조 방법
KR100809330B1 (ko) * 2006-09-04 2008-03-05 삼성전자주식회사 게이트 스페이서로 인한 응력이 배제된 반도체 소자 및 그제조 방법
KR100772901B1 (ko) * 2006-09-28 2007-11-05 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US20080230848A1 (en) * 2007-03-22 2008-09-25 Chih-Chao Yang Structure having dual silicide region and related method
US9153668B2 (en) * 2013-05-23 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Tuning tensile strain on FinFET
US10312348B1 (en) 2017-11-22 2019-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device gate spacer structures and methods thereof

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4445267A (en) * 1981-12-30 1984-05-01 International Business Machines Corporation MOSFET Structure and process to form micrometer long source/drain spacing
JPS58158970A (ja) * 1982-03-16 1983-09-21 Nec Corp 半導体装置の製造方法
US4503601A (en) * 1983-04-18 1985-03-12 Ncr Corporation Oxide trench structure for polysilicon gates and interconnects
JPS59220971A (ja) * 1983-05-31 1984-12-12 Toshiba Corp 半導体装置の製造方法
JPS60200572A (ja) * 1984-03-26 1985-10-11 Hitachi Ltd 半導体装置の製造方法
JPS60241267A (ja) * 1984-05-16 1985-11-30 Hitachi Ltd 半導体装置の製造方法
US4727038A (en) * 1984-08-22 1988-02-23 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor device
JPS61101077A (ja) * 1984-10-24 1986-05-19 Oki Electric Ind Co Ltd 半導体装置の製造方法
SE453547B (sv) * 1985-03-07 1988-02-08 Stiftelsen Inst Mikrovags Forfarande vid framstellning av integrerade kretsar der pa en substratplatta ledare och s k gate-strukturer uppbygges
JPS61224459A (ja) * 1985-03-29 1986-10-06 Toshiba Corp 半導体装置およびその製造方法
JPS6269560A (ja) * 1985-09-24 1987-03-30 Hitachi Ltd 半導体装置の製造方法
EP0218408A3 (de) * 1985-09-25 1988-05-25 Hewlett-Packard Company Verfahren zum Herstellen einer schwach dotierten Drainstruktur (LLD) in integrierten Schaltungen
US4843023A (en) * 1985-09-25 1989-06-27 Hewlett-Packard Company Process for forming lightly-doped-drain (LDD) without extra masking steps
US4701423A (en) * 1985-12-20 1987-10-20 Ncr Corporation Totally self-aligned CMOS process
US4703551A (en) * 1986-01-24 1987-11-03 Ncr Corporation Process for forming LDD MOS/CMOS structures
US4728617A (en) * 1986-11-04 1988-03-01 Intel Corporation Method of fabricating a MOSFET with graded source and drain regions
US4735680A (en) * 1986-11-17 1988-04-05 Yen Yung Chau Method for the self-aligned silicide formation in IC fabrication
JPS6437852A (en) * 1987-08-04 1989-02-08 Mitsubishi Electric Corp Manufacture of semiconductor device
US4755478A (en) * 1987-08-13 1988-07-05 International Business Machines Corporation Method of forming metal-strapped polysilicon gate electrode for FET device
US4818714A (en) * 1987-12-02 1989-04-04 Advanced Micro Devices, Inc. Method of making a high performance MOS device having LDD regions with graded junctions
NL8800222A (nl) * 1988-01-29 1989-08-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij op zelfregistrerende wijze metaalsilicide wordt aangebracht.
US4877755A (en) * 1988-05-31 1989-10-31 Texas Instruments Incorporated Method of forming silicides having different thicknesses
JPH023242A (ja) * 1988-06-17 1990-01-08 Sanyo Electric Co Ltd 半導体装置の製造方法
FR2654258A1 (fr) * 1989-11-03 1991-05-10 Philips Nv Procede pour fabriquer un dispositif a transistor mis ayant une electrode de grille en forme de "t" inverse.
US4981810A (en) * 1990-02-16 1991-01-01 Micron Technology, Inc. Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers

Also Published As

Publication number Publication date
HK179796A (en) 1996-10-04
JPH03139847A (ja) 1991-06-14
EP0424019A3 (en) 1991-12-04
ES2088985T3 (es) 1996-10-01
US5153145A (en) 1992-10-06
EP0424019B1 (de) 1996-07-17
US5679589A (en) 1997-10-21
DE69027832T2 (de) 1996-11-28
EP0424019A2 (de) 1991-04-24

Similar Documents

Publication Publication Date Title
DE69027832D1 (de) Feld-Effekt-Transistor mit Gate-Abstandsstück
DE68925873D1 (de) Transistor mit schwebendem Gate
DE69121535D1 (de) Feldeffekttransistor mit inverser T-förmiger Silizid-Torelektrode
DE69213539D1 (de) Halbleitervorrichtung mit verbessertem isoliertem Gate-Transistor
DE3650630D1 (de) Transistor mit Resonanztunneleffekt
DE3679971D1 (de) Modulationsdotierter feldeffekttransistor.
KR900011019A (ko) 전송게이트
DE3856545D1 (de) Halbleiterbauelement mit isoliertem Gatter
AT399910B (de) Hubgliedertor
DE69128206D1 (de) FET mit U-förmiger Gateelektrode
DE3689433D1 (de) Feldeffekttransistor.
KR860006138A (ko) 헤테로 접합 전계 효과 트랜지스터
DE3782748D1 (de) Feldeffekttransistor mit isoliertem gate.
DE69028161D1 (de) Halbleiteranordnung mit isoliertem Gate
KR900015357A (ko) 절연 게이트 트랜지스터용 mos 파일럿 구조체
KR890007435A (ko) 쇼트키이(Schottky)게이트 전계효과트랜지스터
DK623788D0 (da) Tofaset gate-motor
DE69233306D1 (de) Bipolartransistor mit isoliertem gate
ATA135088A (de) Sektionaltor
DE68925092D1 (de) MOS-Feldeffekttransistor
DE3780895D1 (de) Komplementaerer feldeffekt-transistor mit isoliertem gate.
DE68927192D1 (de) Halbleiteranordnung mit Gattermatrix
ATA14889A (de) Tor
ATA102291A (de) Schiebetor
ATA182189A (de) Sektionaltor

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee