DE69025886D1 - Verfahren zum teilweisen Anfüllen von Kontakten oder Durchführungen verschiedener Tiefe - Google Patents
Verfahren zum teilweisen Anfüllen von Kontakten oder Durchführungen verschiedener TiefeInfo
- Publication number
- DE69025886D1 DE69025886D1 DE69025886T DE69025886T DE69025886D1 DE 69025886 D1 DE69025886 D1 DE 69025886D1 DE 69025886 T DE69025886 T DE 69025886T DE 69025886 T DE69025886 T DE 69025886T DE 69025886 D1 DE69025886 D1 DE 69025886D1
- Authority
- DE
- Germany
- Prior art keywords
- bushings
- procedure
- different depths
- partially filling
- filling contacts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/459,047 US4987099A (en) | 1989-12-29 | 1989-12-29 | Method for selectively filling contacts or vias or various depths with CVD tungsten |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69025886D1 true DE69025886D1 (de) | 1996-04-18 |
| DE69025886T2 DE69025886T2 (de) | 1996-10-02 |
Family
ID=23823191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69025886T Expired - Fee Related DE69025886T2 (de) | 1989-12-29 | 1990-12-18 | Verfahren zum teilweisen Anfüllen von Kontakten oder Durchführungen verschiedener Tiefe |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4987099A (de) |
| EP (1) | EP0435388B1 (de) |
| JP (1) | JPH0430426A (de) |
| DE (1) | DE69025886T2 (de) |
Families Citing this family (64)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0831606B2 (ja) * | 1989-11-17 | 1996-03-27 | 株式会社東芝 | 大電力用半導体装置 |
| US5066612A (en) * | 1990-01-05 | 1991-11-19 | Fujitsu Limited | Method of forming wiring of a semiconductor device |
| JP2892421B2 (ja) * | 1990-02-27 | 1999-05-17 | 沖電気工業株式会社 | 半導体素子の製造方法 |
| DE69026503T2 (de) * | 1990-07-31 | 1996-11-14 | Ibm | Verfahren zur Herstellung von Bauelementen mit übereinander angeordneten selbstjustierten Feldeffekttransistoren aus Polisilizium und sich daraus ergebende Struktur |
| KR930005238B1 (ko) * | 1990-10-25 | 1993-06-16 | 현대전자산업 주식회사 | 금속박막의 평탄화 형성방법 |
| JPH04298030A (ja) * | 1991-03-27 | 1992-10-21 | Sony Corp | メタルプラグの形成方法 |
| JP2811131B2 (ja) * | 1991-04-26 | 1998-10-15 | 三菱電機株式会社 | 半導体装置の配線接続構造およびその製造方法 |
| US5298463A (en) * | 1991-08-30 | 1994-03-29 | Micron Technology, Inc. | Method of processing a semiconductor wafer using a contact etch stop |
| JPH0574955A (ja) * | 1991-09-11 | 1993-03-26 | Nec Corp | 半導体装置の製造方法 |
| KR950012918B1 (ko) * | 1991-10-21 | 1995-10-23 | 현대전자산업주식회사 | 선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택 매립방법 |
| JP2890380B2 (ja) * | 1991-11-27 | 1999-05-10 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| US5250457A (en) * | 1992-02-19 | 1993-10-05 | Micron Technology, Inc. | Method of forming a buried bit line array of memory cells |
| EP0558304B1 (de) * | 1992-02-28 | 2000-01-19 | STMicroelectronics, Inc. | Herstellungsverfahren von Submikronkontakten |
| EP0566253A1 (de) * | 1992-03-31 | 1993-10-20 | STMicroelectronics, Inc. | Herstellungsverfahren für Kontaktstrukturen in integrierten Schaltungen |
| US5466636A (en) * | 1992-09-17 | 1995-11-14 | International Business Machines Corporation | Method of forming borderless contacts using a removable mandrel |
| KR950010858B1 (ko) * | 1992-10-20 | 1995-09-25 | 현대전자산업주식회사 | 반도체 소자의 금속콘택 형성방법 |
| DE59308407D1 (de) * | 1993-01-19 | 1998-05-20 | Siemens Ag | Verfahren zur Herstellung einer Kontakte und diese verbindende Leiterbahnen umfassenden Metallisierungsebene |
| JP2727909B2 (ja) * | 1993-03-26 | 1998-03-18 | 松下電器産業株式会社 | 金属配線の形成方法 |
| JPH07122644A (ja) * | 1993-10-26 | 1995-05-12 | Nec Corp | 半導体装置及びその製造方法 |
| JP3014019B2 (ja) * | 1993-11-26 | 2000-02-28 | 日本電気株式会社 | 半導体装置の製造方法 |
| US5756397A (en) * | 1993-12-28 | 1998-05-26 | Lg Semicon Co., Ltd. | Method of fabricating a wiring in a semiconductor device |
| US5571751A (en) * | 1994-05-09 | 1996-11-05 | National Semiconductor Corporation | Interconnect structures for integrated circuits |
| US5529953A (en) * | 1994-10-14 | 1996-06-25 | Toshiba America Electronic Components, Inc. | Method of forming studs and interconnects in a multi-layered semiconductor device |
| KR0137579B1 (ko) * | 1994-11-30 | 1998-06-01 | 김주용 | 반도체 소자의 플러그 형성방법 |
| JP3274324B2 (ja) * | 1995-09-01 | 2002-04-15 | 株式会社東芝 | 半導体装置の製造方法 |
| JPH09139429A (ja) | 1995-11-10 | 1997-05-27 | Nippon Steel Corp | 半導体装置の製造方法 |
| US5783496A (en) * | 1996-03-29 | 1998-07-21 | Lam Research Corporation | Methods and apparatus for etching self-aligned contacts |
| US5950099A (en) * | 1996-04-09 | 1999-09-07 | Kabushiki Kaisha Toshiba | Method of forming an interconnect |
| JP3607424B2 (ja) * | 1996-07-12 | 2005-01-05 | 株式会社東芝 | 半導体装置及びその製造方法 |
| KR100442407B1 (ko) * | 1996-07-18 | 2004-07-30 | 어드밴스드 마이크로 디바이시즈,인코포레이티드 | 에칭 스톱을 이용하여 스태거된 상호 접속 라인을 생성하는 집적회로 |
| US5854515A (en) * | 1996-07-23 | 1998-12-29 | Advanced Micro Devices, Inc. | Integrated circuit having conductors of enhanced cross-sectional area |
| JPH1070252A (ja) * | 1996-08-27 | 1998-03-10 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| US6001420A (en) | 1996-09-23 | 1999-12-14 | Applied Materials, Inc. | Semi-selective chemical vapor deposition |
| US6391754B1 (en) * | 1996-09-27 | 2002-05-21 | Texas Instruments Incorporated | Method of making an integrated circuit interconnect |
| KR100214852B1 (ko) * | 1996-11-02 | 1999-08-02 | 김영환 | 반도체 디바이스의 금속 배선 형성 방법 |
| US5847462A (en) * | 1996-11-14 | 1998-12-08 | Advanced Micro Devices, Inc. | Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer |
| US6537905B1 (en) | 1996-12-30 | 2003-03-25 | Applied Materials, Inc. | Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug |
| US6342681B1 (en) * | 1997-10-15 | 2002-01-29 | Avx Corporation | Surface mount coupler device |
| US6165910A (en) * | 1997-12-29 | 2000-12-26 | Lam Research Corporation | Self-aligned contacts for semiconductor device |
| US6133153A (en) * | 1998-03-30 | 2000-10-17 | Lam Research Corporation | Self-aligned contacts for semiconductor device |
| JP3631380B2 (ja) * | 1998-08-28 | 2005-03-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US6223432B1 (en) * | 1999-03-17 | 2001-05-01 | Micron Technology, Inc. | Method of forming dual conductive plugs |
| US6232168B1 (en) | 2000-08-25 | 2001-05-15 | Micron Technology, Inc. | Memory circuitry and method of forming memory circuitry |
| US6376380B1 (en) | 2000-08-30 | 2002-04-23 | Micron Technology, Inc. | Method of forming memory circuitry and method of forming memory circuitry comprising a buried bit line array of memory cells |
| US6423609B1 (en) | 2001-05-18 | 2002-07-23 | Micron Technology, Inc. | Methods of forming capacitors on a wafer, photolithographic methods of forming capacitors on a wafer, and semiconductor wafer |
| TW517339B (en) * | 2001-07-25 | 2003-01-11 | Promos Technologies Inc | Method of preventing short circuit between contact window and metal line |
| US6797620B2 (en) * | 2002-04-16 | 2004-09-28 | Applied Materials, Inc. | Method and apparatus for improved electroplating fill of an aperture |
| US20060124026A1 (en) * | 2004-12-10 | 2006-06-15 | 3M Innovative Properties Company | Polishing solutions |
| US7435162B2 (en) * | 2005-10-24 | 2008-10-14 | 3M Innovative Properties Company | Polishing fluids and methods for CMP |
| DE102007004884A1 (de) * | 2007-01-31 | 2008-08-14 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Metallschicht über einem strukturierten Dielektrikum durch stromlose Abscheidung unter Anwendung einer selektiv vorgesehenen Aktivierungsschicht |
| US8952553B2 (en) * | 2009-02-16 | 2015-02-10 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device with stress relaxation during wire-bonding |
| US8486743B2 (en) | 2011-03-23 | 2013-07-16 | Micron Technology, Inc. | Methods of forming memory cells |
| US8994489B2 (en) | 2011-10-19 | 2015-03-31 | Micron Technology, Inc. | Fuses, and methods of forming and using fuses |
| US9252188B2 (en) | 2011-11-17 | 2016-02-02 | Micron Technology, Inc. | Methods of forming memory cells |
| US8723155B2 (en) | 2011-11-17 | 2014-05-13 | Micron Technology, Inc. | Memory cells and integrated devices |
| US8546231B2 (en) | 2011-11-17 | 2013-10-01 | Micron Technology, Inc. | Memory arrays and methods of forming memory cells |
| US8765555B2 (en) | 2012-04-30 | 2014-07-01 | Micron Technology, Inc. | Phase change memory cells and methods of forming phase change memory cells |
| US9136467B2 (en) | 2012-04-30 | 2015-09-15 | Micron Technology, Inc. | Phase change memory cells and methods of forming phase change memory cells |
| US8859417B2 (en) | 2013-01-03 | 2014-10-14 | Globalfoundries Inc. | Gate electrode(s) and contact structure(s), and methods of fabrication thereof |
| US9553262B2 (en) | 2013-02-07 | 2017-01-24 | Micron Technology, Inc. | Arrays of memory cells and methods of forming an array of memory cells |
| US9881971B2 (en) | 2014-04-01 | 2018-01-30 | Micron Technology, Inc. | Memory arrays |
| US9362494B2 (en) | 2014-06-02 | 2016-06-07 | Micron Technology, Inc. | Array of cross point memory cells and methods of forming an array of cross point memory cells |
| US9343506B2 (en) | 2014-06-04 | 2016-05-17 | Micron Technology, Inc. | Memory arrays with polygonal memory cells having specific sidewall orientations |
| US9793216B2 (en) | 2016-01-26 | 2017-10-17 | Globalfoundries Inc. | Fabrication of IC structure with metal plug |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL153374B (nl) * | 1966-10-05 | 1977-05-16 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze. |
| US4005470A (en) * | 1974-07-15 | 1977-01-25 | Signetics Corporation | Triple diffused logic elements |
| US4018627A (en) * | 1975-09-22 | 1977-04-19 | Signetics Corporation | Method for fabricating semiconductor devices utilizing oxide protective layer |
| JPS5275989A (en) * | 1975-12-22 | 1977-06-25 | Hitachi Ltd | Production of semiconductor device |
| JPS53124084A (en) * | 1977-04-06 | 1978-10-30 | Hitachi Ltd | Semiconductor memory device containing floating type poly silicon layer and its manufacture |
| US4141022A (en) * | 1977-09-12 | 1979-02-20 | Signetics Corporation | Refractory metal contacts for IGFETS |
| US4213818A (en) * | 1979-01-04 | 1980-07-22 | Signetics Corporation | Selective plasma vapor etching process |
| US4317690A (en) * | 1980-06-18 | 1982-03-02 | Signetics Corporation | Self-aligned double polysilicon MOS fabrication |
| JPS59195823A (ja) * | 1983-04-20 | 1984-11-07 | Sanyo Electric Co Ltd | 電極形成方法 |
| US4612257A (en) * | 1983-05-02 | 1986-09-16 | Signetics Corporation | Electrical interconnection for semiconductor integrated circuits |
| US4517225A (en) * | 1983-05-02 | 1985-05-14 | Signetics Corporation | Method for manufacturing an electrical interconnection by selective tungsten deposition |
| JPS6081842A (ja) * | 1983-10-12 | 1985-05-09 | Mitsubishi Electric Corp | 配線の形成方法 |
| US4641420A (en) * | 1984-08-30 | 1987-02-10 | At&T Bell Laboratories | Metalization process for headless contact using deposited smoothing material |
| JPS61136274A (ja) * | 1984-12-07 | 1986-06-24 | Toshiba Corp | 半導体装置 |
| JPS6376453A (ja) * | 1986-09-19 | 1988-04-06 | Oki Electric Ind Co Ltd | 多層配線の製造方法 |
| JPS63133551A (ja) * | 1986-11-26 | 1988-06-06 | Agency Of Ind Science & Technol | 半導体装置の製造方法 |
| US4837051A (en) * | 1986-12-19 | 1989-06-06 | Hughes Aircraft Company | Conductive plug for contacts and vias on integrated circuits |
| EP0298110A1 (de) * | 1986-12-19 | 1989-01-11 | Hughes Aircraft Company | Leitfähige füllung von kontakten und kontaktlöchern von integrierten halbleiterschaltungen |
| JPS63190357A (ja) * | 1987-02-02 | 1988-08-05 | Matsushita Electronics Corp | 半導体装置の製造方法 |
| JPS63190358A (ja) * | 1987-02-03 | 1988-08-05 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
| JPS6411346A (en) * | 1987-07-03 | 1989-01-13 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| US4822749A (en) * | 1987-08-27 | 1989-04-18 | North American Philips Corporation, Signetics Division | Self-aligned metallization for semiconductor device and process using selectively deposited tungsten |
| JPS6475260A (en) * | 1987-09-18 | 1989-03-20 | Seiko Epson Corp | Character generation system |
| US4879257A (en) * | 1987-11-18 | 1989-11-07 | Lsi Logic Corporation | Planarization process |
| JPH01175260A (ja) * | 1987-12-29 | 1989-07-11 | Nec Corp | 絶縁ゲート電界効果トランジスタの製造方法 |
-
1989
- 1989-12-29 US US07/459,047 patent/US4987099A/en not_active Expired - Fee Related
-
1990
- 1990-12-18 DE DE69025886T patent/DE69025886T2/de not_active Expired - Fee Related
- 1990-12-18 EP EP90203377A patent/EP0435388B1/de not_active Expired - Lifetime
- 1990-12-26 JP JP2406701A patent/JPH0430426A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0430426A (ja) | 1992-02-03 |
| EP0435388A3 (en) | 1993-03-17 |
| US4987099A (en) | 1991-01-22 |
| EP0435388B1 (de) | 1996-03-13 |
| EP0435388A2 (de) | 1991-07-03 |
| DE69025886T2 (de) | 1996-10-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |