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DE69629068D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69629068D1
DE69629068D1 DE69629068T DE69629068T DE69629068D1 DE 69629068 D1 DE69629068 D1 DE 69629068D1 DE 69629068 T DE69629068 T DE 69629068T DE 69629068 T DE69629068 T DE 69629068T DE 69629068 D1 DE69629068 D1 DE 69629068D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69629068T
Other languages
English (en)
Other versions
DE69629068T2 (de
Inventor
Daisaburo Takashima
Tsuneo Inaba
Yukihito Oowaki
Takashi Ohsawa
Shinichiro Shiratake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69629068D1 publication Critical patent/DE69629068D1/de
Application granted granted Critical
Publication of DE69629068T2 publication Critical patent/DE69629068T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
DE69629068T 1995-03-16 1996-03-14 Halbleiterspeicheranordnung Expired - Fee Related DE69629068T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP8345495 1995-03-16
JP8345495 1995-03-16
JP8717095 1995-04-12
JP08717095A JP3281215B2 (ja) 1995-03-16 1995-04-12 ダイナミック型半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69629068D1 true DE69629068D1 (de) 2003-08-21
DE69629068T2 DE69629068T2 (de) 2004-04-22

Family

ID=26424470

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69629068T Expired - Fee Related DE69629068T2 (de) 1995-03-16 1996-03-14 Halbleiterspeicheranordnung

Country Status (5)

Country Link
US (1) US5761109A (de)
EP (1) EP0732700B1 (de)
JP (1) JP3281215B2 (de)
KR (1) KR100236215B1 (de)
DE (1) DE69629068T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5687114A (en) 1995-10-06 1997-11-11 Agate Semiconductor, Inc. Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
US5870335A (en) 1997-03-06 1999-02-09 Agate Semiconductor, Inc. Precision programming of nonvolatile memory cells
US6487116B2 (en) 1997-03-06 2002-11-26 Silicon Storage Technology, Inc. Precision programming of nonvolatile memory cells
JPH11110967A (ja) * 1997-10-01 1999-04-23 Nec Corp 半導体メモリ装置
US5917744A (en) * 1997-12-18 1999-06-29 Siemens Aktiengesellschaft Semiconductor memory having hierarchical bit line architecture with interleaved master bitlines
US6282145B1 (en) * 1999-01-14 2001-08-28 Silicon Storage Technology, Inc. Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
JP2001084785A (ja) * 1999-09-17 2001-03-30 Nec Corp センスアンプ回路及び半導体記憶装置
US6396742B1 (en) 2000-07-28 2002-05-28 Silicon Storage Technology, Inc. Testing of multilevel semiconductor memory
US6327169B1 (en) * 2000-10-31 2001-12-04 Lsi Logic Corporation Multiple bit line memory architecture
JP2002216471A (ja) 2001-01-17 2002-08-02 Mitsubishi Electric Corp 半導体記憶装置
US6456521B1 (en) * 2001-03-21 2002-09-24 International Business Machines Corporation Hierarchical bitline DRAM architecture system
FR2830365B1 (fr) * 2001-09-28 2004-12-24 St Microelectronics Sa Memoire vive dynamique
JP3696144B2 (ja) 2001-10-17 2005-09-14 株式会社東芝 半導体記憶装置
US6836427B2 (en) * 2002-06-05 2004-12-28 Micron Technology, Inc. System and method to counteract voltage disturbances in open digitline array dynamic random access memory systems
JP3806084B2 (ja) 2002-12-25 2006-08-09 株式会社東芝 強誘電体メモリ及びそのデータ読み出し方法
TWI281159B (en) * 2003-03-21 2007-05-11 Mediatek Inc Sense out circuit for single-bitline semiconductor memory device
US7254074B2 (en) * 2005-03-07 2007-08-07 Micron Technology, Inc. Open digit line array architecture for a memory array
KR100780954B1 (ko) * 2006-08-04 2007-12-03 삼성전자주식회사 감지증폭기 및 이를 구비하는 반도체 메모리 장치, 그리고데이터 센싱 방법
US20080056041A1 (en) * 2006-09-01 2008-03-06 Corvin Liaw Memory circuit
DE102007012902B3 (de) * 2007-03-19 2008-07-10 Qimonda Ag Kopplungsoptimierte Anschlusskonfiguration von Signalleitungen und Verstärkern
US8085611B2 (en) * 2009-01-22 2011-12-27 Macronix International Co., Ltd. Twisted data lines to avoid over-erase cell result coupling to normal cell result
JP2011048885A (ja) * 2009-08-28 2011-03-10 Renesas Electronics Corp 半導体記憶装置
TW201337925A (zh) 2011-10-04 2013-09-16 Mosaid Technologies Inc 減低雜訊動態隨機存取記憶體（ｄｒａｍ）感測
CN116206648B (zh) * 2022-01-27 2024-02-20 北京超弦存储器研究院 动态存储器及其读写方法、存储装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656613A (en) * 1984-08-29 1987-04-07 Texas Instruments Incorporated Semiconductor dynamic memory device with decoded active loads
JPS62202397A (ja) * 1986-02-28 1987-09-07 Fujitsu Ltd 半導体記憶装置
US5214601A (en) * 1986-12-11 1993-05-25 Mitsubishi Denki Kabushiki Kaisha Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers
JP3076606B2 (ja) * 1990-12-14 2000-08-14 富士通株式会社 半導体記憶装置およびその検査方法
JP3302796B2 (ja) * 1992-09-22 2002-07-15 株式会社東芝 半導体記憶装置
JP3440335B2 (ja) * 1993-08-18 2003-08-25 日本テキサス・インスツルメンツ株式会社 半導体メモリ装置
KR100215595B1 (ko) * 1993-09-21 1999-08-16 니시무로 타이죠 다이나믹형 반도체 기억장치

Also Published As

Publication number Publication date
EP0732700B1 (de) 2003-07-16
EP0732700A2 (de) 1996-09-18
KR100236215B1 (ko) 1999-12-15
EP0732700A3 (de) 1996-10-30
KR960035632A (ko) 1996-10-24
DE69629068T2 (de) 2004-04-22
JPH08315577A (ja) 1996-11-29
US5761109A (en) 1998-06-02
JP3281215B2 (ja) 2002-05-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee