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DE69623688D1 - Logiksyntheseverfahren zum Entwurf integrierter Halbleiterschaltungen - Google Patents

Logiksyntheseverfahren zum Entwurf integrierter Halbleiterschaltungen

Info

Publication number
DE69623688D1
DE69623688D1 DE69623688T DE69623688T DE69623688D1 DE 69623688 D1 DE69623688 D1 DE 69623688D1 DE 69623688 T DE69623688 T DE 69623688T DE 69623688 T DE69623688 T DE 69623688T DE 69623688 D1 DE69623688 D1 DE 69623688D1
Authority
DE
Germany
Prior art keywords
design
integrated circuits
semiconductor integrated
synthesis method
logic synthesis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69623688T
Other languages
English (en)
Other versions
DE69623688T2 (de
Inventor
Kazutake Ohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69623688D1 publication Critical patent/DE69623688D1/de
Publication of DE69623688T2 publication Critical patent/DE69623688T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
    • G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Logic Circuits (AREA)
DE69623688T 1995-05-26 1996-05-24 Logiksyntheseverfahren zum Entwurf integrierter Halbleiterschaltungen Expired - Fee Related DE69623688T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12781995 1995-05-26

Publications (2)

Publication Number Publication Date
DE69623688D1 true DE69623688D1 (de) 2002-10-24
DE69623688T2 DE69623688T2 (de) 2003-06-05

Family

ID=14969453

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69623688T Expired - Fee Related DE69623688T2 (de) 1995-05-26 1996-05-24 Logiksyntheseverfahren zum Entwurf integrierter Halbleiterschaltungen

Country Status (6)

Country Link
US (2) US5926396A (de)
EP (3) EP0955594A3 (de)
KR (1) KR100296183B1 (de)
CN (2) CN1130829C (de)
DE (1) DE69623688T2 (de)
TW (1) TW305958B (de)

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JP4428489B2 (ja) * 1999-08-23 2010-03-10 パナソニック株式会社 集積回路装置及びそのテスト方法
JP2001142921A (ja) * 1999-11-12 2001-05-25 Nec Ic Microcomput Syst Ltd 機能ブロック間制約高速抽出方法、及び、機能ブロック間制約高速抽出プログラムを記録した記録媒体
US6327552B2 (en) * 1999-12-28 2001-12-04 Intel Corporation Method and system for determining optimal delay allocation to datapath blocks based on area-delay and power-delay curves
JP4313488B2 (ja) * 2000-01-19 2009-08-12 パナソニック株式会社 半導体装置
JP4295894B2 (ja) * 2000-04-14 2009-07-15 株式会社アドバンテスト 半導体デバイスの試験装置および試験方法
US6792582B1 (en) 2000-11-15 2004-09-14 International Business Machines Corporation Concurrent logical and physical construction of voltage islands for mixed supply voltage designs
DE10100168A1 (de) * 2001-01-04 2002-07-18 Infineon Technologies Ag Entwurf von Schaltungen mit Abschnitten unterschiedlicher Versorgungsspannung
US6470476B2 (en) 2001-03-16 2002-10-22 International Business Machines Corporation Substitution of non-minimum groundrule cells for non-critical minimum groundrule cells to increase yield
US7149992B2 (en) 2002-10-23 2006-12-12 Via Technologies, Inc. Method for faster timing closure and better quality of results in IC physical design
US7805697B2 (en) 2002-12-06 2010-09-28 Multigig Inc. Rotary clock synchronous fabric
US20040169544A1 (en) * 2003-02-28 2004-09-02 Roy Aninda K. Flip-flop design with built-in voltage translation
WO2004081761A2 (en) * 2003-03-12 2004-09-23 Sensory Networks Inc. Apparatus and method for memory efficient, programmable, pattern matching finite state machine hardware
US7111266B2 (en) * 2003-11-24 2006-09-19 International Business Machines Corp. Multiple voltage integrated circuit and design method therefor
US7146471B2 (en) * 2003-12-31 2006-12-05 International Business Machines Corp. System and method for variable array architecture for memories
US7219319B2 (en) * 2004-03-12 2007-05-15 Sensory Networks, Inc. Apparatus and method for generating state transition rules for memory efficient programmable pattern matching finite state machine hardware
JP4562456B2 (ja) * 2004-08-20 2010-10-13 パナソニック株式会社 半導体集積回路
JP2007109983A (ja) * 2005-10-14 2007-04-26 Matsushita Electric Ind Co Ltd 半導体集積回路装置、電子機器及び半導体集積回路装置の製造方法
US7958476B1 (en) * 2007-07-10 2011-06-07 Magma Design Automation, Inc. Method for multi-cycle path and false path clock gating
US8843862B2 (en) * 2008-12-16 2014-09-23 Synopsys, Inc. Method and apparatus for creating and changing logic representations in a logic design using arithmetic flexibility of numeric formats for data
US8539388B2 (en) * 2010-07-14 2013-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for low power semiconductor chip layout and low power semiconductor chip
US9171117B2 (en) 2011-03-28 2015-10-27 Freescale Semiconductor, Inc. Method for ranking paths for power optimization of an integrated circuit design and corresponding computer program product
CN102710248A (zh) * 2012-05-21 2012-10-03 奇瑞汽车股份有限公司 一种电压隔离采集电路
US8791743B1 (en) 2013-02-18 2014-07-29 Apple Inc. Balanced level shifter with wide operation range
US8839171B1 (en) 2013-03-31 2014-09-16 Atrenta, Inc. Method of global design closure at top level and driving of downstream implementation flow
KR102268591B1 (ko) * 2014-08-18 2021-06-25 삼성전자주식회사 회로의 자가 발열 특성을 예측하는 시뮬레이션 시스템 및 그것의 회로 설계 방법
US20200106424A1 (en) 2018-09-27 2020-04-02 Apple Inc. Semi dynamic flop and single stage pulse flop with shadow latch and transparency on both input data edges
KR102474856B1 (ko) 2021-11-18 2022-12-06 주식회사 마키나락스 인공지능 기반의 반도체 설계 자동화 방법
KR20230073074A (ko) 2021-11-18 2023-05-25 주식회사 마키나락스 인공지능 기반의 반도체 설계 자동화 방법
KR20230118486A (ko) 2022-02-04 2023-08-11 주식회사 마키나락스 반도체 소자의 배치를 평가하는 방법
KR20230122516A (ko) 2022-02-14 2023-08-22 주식회사 마키나락스 금지 영역 정보를 기반으로 반도체 소자를 배치하는 방법
KR20230123864A (ko) 2022-02-17 2023-08-24 주식회사 마키나락스 인공지능 기반의 반도체 설계 방법
KR102597328B1 (ko) 2023-01-25 2023-11-02 주식회사 마키나락스 반도체 소자의 배치를 평가하기 위해 2중 클러스터링을 수행하는 방법

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US3950636A (en) * 1974-01-16 1976-04-13 Signetics Corporation High speed multiplier logic circuit
US5245224A (en) * 1983-01-31 1993-09-14 Hitachi, Ltd. Level conversion circuitry for a semiconductor integrated circuit
JPH0795395B2 (ja) * 1984-02-13 1995-10-11 株式会社日立製作所 半導体集積回路
WO1986002792A1 (en) * 1984-11-02 1986-05-09 Advanced Micro Devices, Inc. Integrated circuit device accepting inputs and providing outputs at the levels of different logic families
JPS62189739A (ja) * 1986-02-17 1987-08-19 Hitachi Ltd 半導体集積回路装置
US5115408A (en) * 1988-01-29 1992-05-19 Texas Instruments Incorporated High speed multiplier
JPH02187063A (ja) * 1989-01-13 1990-07-23 Fuji Electric Co Ltd Ｍｏｓ集積回路装置
US5541849A (en) * 1990-04-06 1996-07-30 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of timing parameters
JPH0496369A (ja) * 1990-08-13 1992-03-27 Kawasaki Steel Corp ゲートアレー型ｌｓｉ
JPH04223616A (ja) * 1990-12-25 1992-08-13 Toshiba Corp 半導体論理回路
JP3079515B2 (ja) * 1991-01-29 2000-08-21 株式会社東芝 ゲ−トアレイ装置及び入力回路及び出力回路及び降圧回路
JPH0567963A (ja) * 1991-09-06 1993-03-19 Hitachi Ltd 論理集積回路
JPH05289851A (ja) * 1992-04-15 1993-11-05 Fujitsu Ltd 乗算装置
JPH05299624A (ja) * 1992-04-23 1993-11-12 Mitsubishi Electric Corp 半導体集積回路装置
US5311083A (en) * 1993-01-25 1994-05-10 Standard Microsystems Corporation Very low voltage inter-chip CMOS logic signaling for large numbers of high-speed output lines each associated with large capacitive loads
US5300835A (en) * 1993-02-10 1994-04-05 Cirrus Logic, Inc. CMOS low power mixed voltage bidirectional I/O buffer
JPH06348459A (ja) * 1993-06-04 1994-12-22 Hitachi Ltd 論理演算回路
JPH0774616A (ja) * 1993-07-06 1995-03-17 Seiko Epson Corp 信号電圧レベル変換回路及び出力バッファ回路
US5612892A (en) * 1993-12-16 1997-03-18 Intel Corporation Method and structure for improving power consumption on a component while maintaining high operating frequency
EP0862127B1 (de) * 1994-01-19 2002-09-04 Matsushita Electric Industrial Co., Ltd. Verfahren zum Entwurf einer integrierten Halbleiter-Schaltung
US5557533A (en) * 1994-04-19 1996-09-17 Lsi Logic Corporation Cell placement alteration apparatus for integrated circuit chip physical design automation system
JP3117603B2 (ja) * 1994-06-06 2000-12-18 松下電器産業株式会社 半導体集積回路
US5594368A (en) * 1995-04-19 1997-01-14 Kabushiki Kaisha Toshiba Low power combinational logic circuit
JPH08330939A (ja) * 1995-06-05 1996-12-13 Toshiba Microelectron Corp レベルシフタ回路

Also Published As

Publication number Publication date
EP0744704B1 (de) 2002-09-18
EP0744704A2 (de) 1996-11-27
TW305958B (de) 1997-05-21
DE69623688T2 (de) 2003-06-05
US5926396A (en) 1999-07-20
EP0955594A3 (de) 2002-04-10
KR100296183B1 (ko) 2001-10-22
EP1335309A1 (de) 2003-08-13
CN1430331A (zh) 2003-07-16
KR960043163A (ko) 1996-12-23
EP0955594A2 (de) 1999-11-10
CN1143860A (zh) 1997-02-26
US5978573A (en) 1999-11-02
CN1208900C (zh) 2005-06-29
EP0744704A3 (de) 1998-04-08
CN1130829C (zh) 2003-12-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP

8339 Ceased/non-payment of the annual fee