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DE60040593D1 - Doppeleingangspuffer fur einen abtast- und halteverstarker - Google Patents

Doppeleingangspuffer fur einen abtast- und halteverstarker

Info

Publication number
DE60040593D1
DE60040593D1 DE60040593T DE60040593T DE60040593D1 DE 60040593 D1 DE60040593 D1 DE 60040593D1 DE 60040593 T DE60040593 T DE 60040593T DE 60040593 T DE60040593 T DE 60040593T DE 60040593 D1 DE60040593 D1 DE 60040593D1
Authority
DE
Germany
Prior art keywords
screw
input buffer
double input
amplifier
holder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60040593T
Other languages
English (en)
Inventor
Gian Hoogzaad
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Application granted granted Critical
Publication of DE60040593D1 publication Critical patent/DE60040593D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)
DE60040593T 1999-12-24 2000-12-13 Doppeleingangspuffer fur einen abtast- und halteverstarker Expired - Lifetime DE60040593D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP99204526 1999-12-24
PCT/EP2000/012620 WO2001048759A1 (en) 1999-12-24 2000-12-13 Double input buffer for track-and-hold amplifier

Publications (1)

Publication Number Publication Date
DE60040593D1 true DE60040593D1 (de) 2008-12-04

Family

ID=8241083

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60040593T Expired - Lifetime DE60040593D1 (de) 1999-12-24 2000-12-13 Doppeleingangspuffer fur einen abtast- und halteverstarker

Country Status (6)

Country Link
US (1) US6323700B2 (de)
EP (1) EP1157389B1 (de)
JP (1) JP2003518858A (de)
KR (1) KR100741183B1 (de)
DE (1) DE60040593D1 (de)
WO (1) WO2001048759A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100747808B1 (ko) * 2000-03-28 2007-08-08 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 트랙 및 홀드 증폭기
KR100477564B1 (ko) * 2002-08-19 2005-03-18 이디텍 주식회사 영상출력시스템에 내장되는 에이디변환기의 트랙앤홀드회로장치
US7782096B2 (en) * 2007-08-08 2010-08-24 Texas Instruments Incorporated Track-and-hold circuit with low distortion
US7804337B2 (en) * 2007-10-23 2010-09-28 Texas Instruments Incorporated Method and apparatus of SFDR enhancement
JP5122526B2 (ja) * 2009-01-15 2013-01-16 日本電信電話株式会社 トラック・ホールド回路
JP6830079B2 (ja) * 2018-03-30 2021-02-17 日本電信電話株式会社 トラック・アンド・ホールド回路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1213307B (it) * 1986-07-29 1989-12-20 Sgs Microelettronica Spa Circuito ripetitore di tensione per carichi con componente resistiva con compensazione della distorsione armonica.
US4806790A (en) * 1987-02-16 1989-02-21 Nec Corporation Sample-and-hold circuit
JPS63200397A (ja) * 1987-02-16 1988-08-18 Nec Corp サンプルホ−ルド回路
US5198782A (en) * 1991-01-15 1993-03-30 Crystal Semiconductor Low distortion amplifier output stage for dac
JP2680753B2 (ja) * 1991-07-31 1997-11-19 三洋電機株式会社 バッファアンプ
JP3332991B2 (ja) * 1993-05-12 2002-10-07 日本テキサス・インスツルメンツ株式会社 駆動回路
US5442309A (en) * 1993-12-14 1995-08-15 Advanced Micro Devices, Inc. Low distortion output stage
JP2570185B2 (ja) 1994-07-08 1997-01-08 日本電気株式会社 サンプルホールド回路
US5457418A (en) * 1994-12-05 1995-10-10 National Semiconductor Corporation Track and hold circuit with an input transistor held on during hold mode
US5654665A (en) * 1995-05-18 1997-08-05 Dynachip Corporation Programmable logic bias driver
JPH0964665A (ja) * 1995-08-28 1997-03-07 Nec Eng Ltd 半導体集積回路
EP0819339A1 (de) * 1996-02-01 1998-01-21 Koninklijke Philips Electronics N.V. Verzerrungskompensation für eine kapazitiv belastete folgerschaltung

Also Published As

Publication number Publication date
EP1157389A1 (de) 2001-11-28
US20010007434A1 (en) 2001-07-12
US6323700B2 (en) 2001-11-27
WO2001048759A1 (en) 2001-07-05
JP2003518858A (ja) 2003-06-10
EP1157389B1 (de) 2008-10-22
KR20010102362A (ko) 2001-11-15
KR100741183B1 (ko) 2007-07-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition