DE3277758D1 - Semiconductor chip mounting module - Google Patents
Semiconductor chip mounting moduleInfo
- Publication number
- DE3277758D1 DE3277758D1 DE8282304406T DE3277758T DE3277758D1 DE 3277758 D1 DE3277758 D1 DE 3277758D1 DE 8282304406 T DE8282304406 T DE 8282304406T DE 3277758 T DE3277758 T DE 3277758T DE 3277758 D1 DE3277758 D1 DE 3277758D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor chip
- chip mounting
- mounting module
- module
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
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- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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- H01L2924/161—Cap
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- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Lead Frames For Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/294,100 US4446477A (en) | 1981-08-21 | 1981-08-21 | Multichip thin film module |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3277758D1 true DE3277758D1 (en) | 1988-01-07 |
Family
ID=23131876
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8282304406T Expired DE3277758D1 (en) | 1981-08-21 | 1982-08-20 | Semiconductor chip mounting module |
Country Status (4)
Country | Link |
---|---|
US (1) | US4446477A (de) |
EP (1) | EP0073149B1 (de) |
JP (1) | JPS5853161U (de) |
DE (1) | DE3277758D1 (de) |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2137807B (en) * | 1983-04-05 | 1987-08-12 | Plessey Co Plc | A semiconductor component and method of manufacture |
JPS60108460U (ja) * | 1983-12-27 | 1985-07-23 | 本田技研工業株式会社 | 加圧鋳造機における注湯部構造 |
EP0162521A3 (de) * | 1984-05-23 | 1986-10-08 | American Microsystems, Incorporated | Packung für Halbleiteranordnungen |
FR2575331B1 (fr) * | 1984-12-21 | 1987-06-05 | Labo Electronique Physique | Boitier pour composant electronique |
US4783697A (en) * | 1985-01-07 | 1988-11-08 | Motorola, Inc. | Leadless chip carrier for RF power transistors or the like |
US4647959A (en) * | 1985-05-20 | 1987-03-03 | Tektronix, Inc. | Integrated circuit package, and method of forming an integrated circuit package |
US4874721A (en) * | 1985-11-11 | 1989-10-17 | Nec Corporation | Method of manufacturing a multichip package with increased adhesive strength |
US4700473A (en) * | 1986-01-03 | 1987-10-20 | Motorola Inc. | Method of making an ultra high density pad array chip carrier |
US4700276A (en) * | 1986-01-03 | 1987-10-13 | Motorola Inc. | Ultra high density pad array chip carrier |
JPS62216259A (ja) * | 1986-03-17 | 1987-09-22 | Fujitsu Ltd | 混成集積回路の製造方法および構造 |
AU1346088A (en) * | 1987-02-04 | 1988-08-24 | Coors Porcelain Company | Ceramic substrate with conductively-filled vias and method for producing |
US4743568A (en) * | 1987-07-24 | 1988-05-10 | Motorola Inc. | Multilevel interconnect transfer process |
GB2209867B (en) * | 1987-09-16 | 1990-12-19 | Advanced Semiconductor Package | Method of forming an integrated circuit chip carrier |
JPH0751270B2 (ja) * | 1988-07-06 | 1995-06-05 | 田辺工業株式会社 | 溶融金属の給湯方法と給湯装置 |
US4916259A (en) * | 1988-08-01 | 1990-04-10 | International Business Machines Corporation | Composite dielectric structure for optimizing electrical performance in high performance chip support packages |
US5005070A (en) * | 1988-12-19 | 1991-04-02 | Hewlett-Packard Company | Soldering interconnect method and apparatus for semiconductor packages |
US5237205A (en) * | 1989-10-02 | 1993-08-17 | Advanced Micro Devices, Inc. | Ground plane for plastic encapsulated integrated circuit die packages |
US5208188A (en) * | 1989-10-02 | 1993-05-04 | Advanced Micro Devices, Inc. | Process for making a multilayer lead frame assembly for an integrated circuit structure and multilayer integrated circuit die package formed by such process |
US5559369A (en) * | 1989-10-02 | 1996-09-24 | Advanced Micro Devices, Inc. | Ground plane for plastic encapsulated integrated circuit die packages |
US5068708A (en) * | 1989-10-02 | 1991-11-26 | Advanced Micro Devices, Inc. | Ground plane for plastic encapsulated integrated circuit die packages |
JP2633366B2 (ja) * | 1989-11-24 | 1997-07-23 | 株式会社日立製作所 | 計算機モジュール用リードレスチップキャリア |
US5061987A (en) * | 1990-01-09 | 1991-10-29 | Northrop Corporation | Silicon substrate multichip assembly |
US5157477A (en) * | 1990-01-10 | 1992-10-20 | International Business Machines Corporation | Matched impedance vertical conductors in multilevel dielectric laminated wiring |
US5948533A (en) * | 1990-02-09 | 1999-09-07 | Ormet Corporation | Vertically interconnected electronic assemblies and compositions useful therefor |
WO1992008606A1 (en) * | 1990-11-19 | 1992-05-29 | The Carborundum Company | Microelectronics package |
US6111308A (en) * | 1991-06-05 | 2000-08-29 | Advanced Micro Devices, Inc. | Ground plane for plastic encapsulated integrated circuit die packages |
US5262719A (en) * | 1991-09-19 | 1993-11-16 | International Business Machines Corporation | Test structure for multi-layer, thin-film modules |
US5625307A (en) * | 1992-03-03 | 1997-04-29 | Anadigics, Inc. | Low cost monolithic gallium arsenide upconverter chip |
US5287619A (en) * | 1992-03-09 | 1994-02-22 | Rogers Corporation | Method of manufacture multichip module substrate |
US5440805A (en) * | 1992-03-09 | 1995-08-15 | Rogers Corporation | Method of manufacturing a multilayer circuit |
JP2721093B2 (ja) * | 1992-07-21 | 1998-03-04 | 三菱電機株式会社 | 半導体装置 |
JPH08250827A (ja) * | 1995-03-08 | 1996-09-27 | Shinko Electric Ind Co Ltd | 半導体装置用パッケージ及びその製造方法並びに半導体装置 |
US6861290B1 (en) * | 1995-12-19 | 2005-03-01 | Micron Technology, Inc. | Flip-chip adaptor package for bare die |
US5719440A (en) | 1995-12-19 | 1998-02-17 | Micron Technology, Inc. | Flip chip adaptor package for bare die |
US5952716A (en) | 1997-04-16 | 1999-09-14 | International Business Machines Corporation | Pin attach structure for an electronic package |
USRE43112E1 (en) | 1998-05-04 | 2012-01-17 | Round Rock Research, Llc | Stackable ball grid array package |
US6377464B1 (en) * | 1999-01-29 | 2002-04-23 | Conexant Systems, Inc. | Multiple chip module with integrated RF capabilities |
FR2793990B1 (fr) | 1999-05-19 | 2001-07-27 | Sagem | Boitier electronique sur plaque et procede de fabrication d'un tel boitier |
JP4780844B2 (ja) * | 2001-03-05 | 2011-09-28 | Okiセミコンダクタ株式会社 | 半導体装置 |
CN103534802A (zh) * | 2011-06-01 | 2014-01-22 | E.I.内穆尔杜邦公司 | 用于高频应用的低温共烧陶瓷结构及其制造方法 |
US20130015504A1 (en) * | 2011-07-11 | 2013-01-17 | Chien-Li Kuo | Tsv structure and method for forming the same |
US10643936B2 (en) * | 2017-05-31 | 2020-05-05 | Dyi-chung Hu | Package substrate and package structure |
KR102613513B1 (ko) | 2019-05-17 | 2023-12-13 | 삼성전자주식회사 | 반도체 모듈 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5233787B2 (de) * | 1972-05-10 | 1977-08-30 | ||
US4074342A (en) * | 1974-12-20 | 1978-02-14 | International Business Machines Corporation | Electrical package for lsi devices and assembly process therefor |
JPS5242371A (en) * | 1975-10-01 | 1977-04-01 | Hitachi Ltd | Multi-chip packaged semiconductor device |
US4210885A (en) * | 1978-06-30 | 1980-07-01 | International Business Machines Corporation | Thin film lossy line for preventing reflections in microcircuit chip package interconnections |
US4221047A (en) * | 1979-03-23 | 1980-09-09 | International Business Machines Corporation | Multilayered glass-ceramic substrate for mounting of semiconductor device |
US4245273A (en) * | 1979-06-29 | 1981-01-13 | International Business Machines Corporation | Package for mounting and interconnecting a plurality of large scale integrated semiconductor devices |
US4322778A (en) * | 1980-01-25 | 1982-03-30 | International Business Machines Corp. | High performance semiconductor package assembly |
-
1981
- 1981-08-21 US US06/294,100 patent/US4446477A/en not_active Expired - Fee Related
-
1982
- 1982-08-20 JP JP1982125066U patent/JPS5853161U/ja active Granted
- 1982-08-20 DE DE8282304406T patent/DE3277758D1/de not_active Expired
- 1982-08-20 EP EP82304406A patent/EP0073149B1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0073149A2 (de) | 1983-03-02 |
US4446477A (en) | 1984-05-01 |
EP0073149B1 (de) | 1987-11-25 |
JPS5853161U (ja) | 1983-04-11 |
EP0073149A3 (en) | 1984-12-19 |
JPH0220848Y2 (de) | 1990-06-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |