CN218385229U - IGBT device and chip - Google Patents
IGBT device and chip Download PDFInfo
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- CN218385229U CN218385229U CN202221006202.3U CN202221006202U CN218385229U CN 218385229 U CN218385229 U CN 218385229U CN 202221006202 U CN202221006202 U CN 202221006202U CN 218385229 U CN218385229 U CN 218385229U
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Abstract
The utility model provides a IGBT device and chip. The IGBT device comprises a plurality of field limiting rings arranged on a semiconductor substrate at intervals, and a junction terminal extension structure surrounding the outer sides of the field limiting rings, wherein the innermost field limiting ring defines an active region, and a plurality of etched regions are arranged in the active region; the first doped regions of adjacent field limiting rings are contacted or overlapped; the second doping region of the junction terminal extension structure is in contact with or overlapped with the first doping region in the outermost field limiting ring; the depth of the second doping region is less than or equal to the depth of the first doping region in the outermost field limiting ring; the depth of the third doping area of the outermost side etching area is less than or equal to the depth of the first doping area of the innermost side field limiting ring; the third doped region of the outermost etched region contacts or overlaps the first doped region of the innermost field limiting ring. The utility model provides a IGBT device has stronger resistance to pressure.
Description
Technical Field
The utility model relates to the field of semiconductor technology, concretely relates to IGBT device and chip.
Background
An IGBT (Insulated Gate Bipolar Transistor) has both the advantages of high input impedance of an MOSFET (metal-oxide-semiconductor-field effect Transistor) and low on-state voltage drop of a GTR (power Bipolar Transistor), and is very suitable for application to a converter system having a dc voltage of 600V or more. As a core device for energy conversion and transmission, the IGBT has been widely used in products such as rail transit, smart grid, and white appliances.
In the IGBT, an FLR (Field Limiting Ring) is usually disposed in a termination region thereof to improve a withstand voltage of the device and meet a low power loss requirement. Taking an epitaxial wafer as an example, an oxide layer with a certain thickness can be grown on the surface of the epitaxial layer, patterning is performed on the oxide layer to form a plurality of injection windows, ion injection is performed on the epitaxial layer through the injection windows, and then high-temperature oxidation junction pushing is performed to form a plurality of doped regions with the same diffusion depth. Because the terminal region is slowly pulled open in a gradient manner in the transverse direction and the longitudinal direction, the electric field concentration is effectively slowed down, and the withstand voltage of the device can be improved by the field limiting ring.
However, with the increasing performance requirements of the market on products such as rail transit, smart grid and white home appliances, higher requirements are also put forward on the performance of the IGBT, especially the voltage withstanding performance, and therefore how to further improve the voltage withstanding of the IGBT is a problem to be solved at present.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides a IGBT device to improve the voltage resistance of IGBT device. The utility model also provides a chip, including above-mentioned IGBT device.
In order to achieve the above object, the present invention provides an IGBT device including a semiconductor substrate; the semiconductor substrate is provided with a plurality of field limiting rings at intervals, wherein the innermost field limiting ring defines an active region and a junction terminal extension structure surrounding the outer sides of the field limiting rings, and a plurality of etched regions are arranged in the active region; each field limiting ring comprises a first groove formed on the upper surface of the semiconductor substrate and first doping regions extending from the side parts and the bottom parts of the first grooves into the semiconductor substrate, and the first doping regions of adjacent field limiting rings are contacted or overlapped; the junction terminal extension structure comprises a second doped region, the second doped region extends from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate, and the second doped region is in contact with or overlapped with the first doped region in the outermost field limiting ring; the depth of the second doping region is less than or equal to the depth of the first doping region in the outermost field limiting ring; each etched region comprises a second groove formed on the upper surface of the semiconductor substrate and a third doped region extending from the side part and the bottom part of the second groove into the semiconductor substrate; the depth of a third doped region of the outermost etched region adjacent to the innermost field limiting ring is less than or equal to the depth of the first doped region of the innermost field limiting ring; the third doped region of the outermost etched region is in contact with or overlapped with the first doped region of the innermost field limiting ring; the depth of the second doped region, the depth of the first doped region in the outermost field limiting ring, and the depth of the third doped region of the outermost etched region are not all the same.
Further, the depth of the second doped region is smaller than that of the first doped region; the depth of the first doped region closest to the active region is greater than the depth of the third doped region.
Furthermore, in two adjacent field limiting rings, the depth of the first doped region of the inner field limiting ring is greater than or equal to the depth of the first doped region of the outer field limiting ring; the depths of the first doping regions of at least two field limiting rings in the plurality of field limiting rings are different;
the second doping region comprises an ion implantation region and an ion diffusion region, wherein the ion diffusion region surrounds the ion implantation region; the width of the ion implantation area is larger than that of the groove in the field limiting ring at the outermost side.
Further, in a plurality of the field limiting rings, the depth of the first doped region is distributed in a progressive manner.
Further, the etching region further includes a fourth doped region and a fifth doped region located in the third doped region, wherein the fourth doped region extends from the side of the second trench to the inside of the third doped region, and the fifth doped region extends from the side and the bottom of the second trench to the inside of the third doped region.
Further, the fourth doped region extends from the second trench side into the third doped region to a greater extent than the fifth doped region extends from the second trench side into the third doped region.
Further, the fourth doped region of the outermost etched region extends from the side portion, far away from the field limiting ring, of the second trench of the outermost etched region to the inside of the third doped region.
Further, the upper surface of the fifth doped region is lower than the upper surface of the semiconductor substrate or the upper surface of the fifth doped region is flush with the upper surface of the semiconductor substrate.
Further, the distance from the bottom of the fourth doped region to the lower surface of the semiconductor substrate is greater than the distance from the bottom of the fifth doped region to the lower surface of the semiconductor substrate.
The utility model discloses the second aspect provides a chip, including the first aspect the IGBT device.
The utility model provides a IGBT device has following technological effect:
the depth of the second doped region of the junction terminal extension structure is less than or equal to the depth of the first doped region in the outermost field limiting ring, and the depth of the third doped region of the outermost etched region is less than or equal to the depth of the first doped region of the innermost field limiting ring; and the depth of the second doped region, the depth of the first doped region in the outermost field limiting ring and the depth of the third doped region in the outermost etched region are not completely the same, so that in the direction from the junction terminal extension structure to the etched region, the depth of the second doped region of the junction terminal extension structure, the depth of the first doped region of the field limiting ring and the depth of the third doped region of the etched region show a trend of increasing and then decreasing on the whole.
The utility model provides a chip owing to include above IGBT device, consequently also has good voltage resistance.
Drawings
Fig. 1 is a schematic structural diagram of an IGBT according to an embodiment of the present invention;
fig. 2 and 3 are schematic diagrams of a plurality of trenches in an IGBT device according to an embodiment of the present invention;
fig. 4 to fig. 19 are schematic structural diagrams of partial steps in a manufacturing process of an IGBT device according to an embodiment of the present invention.
Detailed Description
In order to understand the features and technical contents of the embodiments of the present invention in more detail, the following description is given in conjunction with the accompanying drawings for describing the embodiments of the present invention in detail, and the accompanying drawings are only used for the purpose of reference and are not used to limit the embodiments of the present invention. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures may be shown to simplify the drawing.
The terms "first," "second," and the like in the description and in the claims, and in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
In the prior art, a process for forming a field limiting ring includes forming an oxide layer mask on a surface of a semiconductor substrate, and then performing ion implantation and high-temperature junction pushing, thereby forming a plurality of doping regions arranged in a concentric ring in the semiconductor substrate. The oxide layer mask is also used for protecting the semiconductor substrate from being damaged in the ion implantation process. The radius of curvature of a terminal junction formed after the junction is pushed by the process is smaller, so that the voltage resistance of the IGBT device is lower.
Based on this, the utility model provides a solution to improve the withstand voltage of IGBT device.
Fig. 1 is a schematic structural diagram of an IGBT device provided by an embodiment of the present invention, and fig. 1 is a partial cross-sectional view, which only shows a terminal region and a portion of an active region close to the terminal region. As shown in fig. 1, the IGBT device provided in this embodiment includes a semiconductor substrate; a plurality of field limiting rings are arranged on the semiconductor substrate at intervals, wherein the innermost field limiting ring defines an active region, and a plurality of etched regions are formed in the active region.
Each field limiting ring comprises a first trench 30 formed on the upper surface of the semiconductor substrate, and a first doped region 40 extending from the side and bottom of the first trench 30 into the semiconductor substrate, and the first doped regions 40 of adjacent field limiting rings contact or overlap.
A junction terminal extension structure is arranged around the outer sides of the field limiting rings and comprises a second doping region 50, the second doping region 50 extends inwards from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate, and the second doping region 50 is in contact with or overlapped with the first doping region 40 in the field limiting ring at the outermost side; the depth of the second doped region 50 is less than or equal to the depth of the first doped region 40 in the outermost field limiting ring.
Each of the etched-out regions includes a second trench 64 formed in the upper surface of the semiconductor substrate, and a third doped region 61 extending from the side and bottom of the second trench 64 into the semiconductor substrate; the depth of the third doped region 61 of the outermost etched region adjacent to the innermost field limiting ring is less than or equal to the depth of the first doped region 40 of the innermost field limiting ring; the third doped region 61 of the outermost etched-out region contacts or overlaps the first doped region 40 of the innermost field limiting ring.
The depth of the second doped region 50 of the junction termination extension structure is less than or equal to the depth of the first doped region 40 in the outermost field limiting ring, and the depth of the third doped region 61 of the outermost etched region is less than or equal to the depth of the first doped region 40 of the innermost field limiting ring; moreover, the depth of the second doped region 50, the depth of the first doped region 40 in the outermost field limiting ring, and the depth of the third doped region 61 in the outermost etched region are not completely the same, so that in the direction from the junction terminal extension structure to the etched region, i.e., the direction from the terminal region to the active region, the depth of the second doped region 50 of the junction terminal extension structure, the depth of the first doped region 40 of the field limiting ring, and the depth of the third doped region 61 of the etched region, generally exhibit a tendency of increasing and then decreasing, and the junction terminal extension structure, the field limiting ring, and the etched region arranged in this way can increase the radius of curvature of the junction terminal extension structure, the field limiting ring, and the etched region, reduce the electric field density, thereby improving the breakdown voltage resistance of the semiconductor device, increasing the breakdown voltage value, and improving the leakage problem of the IGBT device.
In the embodiment, the first doped region 40 is obtained by implanting ions into the semiconductor substrate through the first trench 30 and diffusing the ions, so that in a specific implementation process, in addition to controlling the implantation energy in the ion implantation process, the temperature and time in the junction pushing process and other process conditions, the depth and width of the first trench 30 can be controlled to control the depth and width of the first doped region 40, so that the curvature radius of the termination junction can be controlled, and the voltage resistance and the leakage problem of the IGBT device can be controlled.
And, compare in the doping area of prior art field limiting ring and carry out ion implantation and diffusion formation to semiconductor substrate, the utility model discloses the first doping area 40 of well field limiting ring carries out ion implantation and diffusion formation through first slot 30, need not to grow the oxide layer on semiconductor substrate surface promptly at preparation field limiting ring in-process, can directly pour into ion and high temperature into to the slot and push away the knot and form the doping area, has reduced the thermal budget, has reduced transition district diffusion then, has further improved the voltage endurance of IGBT device. Referring to fig. 4, in a general IGBT device, the doping concentration of the substrate 10 is higher than that of the epitaxial layer 20, so that under the influence of high temperature, ions in the substrate 10 diffuse into the epitaxial layer 20, i.e. a transition region diffuses.
The etched region in the active region is first described in detail, and then the field limiting ring and the junction termination extension structure are described in detail.
And a polysilicon gate is arranged between every two etched regions, the projection of the etched regions on the upper surface of the semiconductor substrate can be rectangular, and the whole polysilicon gates are connected in parallel. A gate dielectric layer, such as a silicon dioxide layer, is also disposed between the polysilicon gate and the upper surface of the semiconductor substrate.
In terms of the specific structure of the single scribe region, as shown in fig. 1, the scribe region further includes a fourth doping region 62 and a fifth doping region 63 in the third doping region 61.
Further, the fourth doped region 62 extends from the side of the second trench 64 to the inside of the third doped region 61, and the fifth doped region 63 extends from the side and the bottom of the second trench 64 to the inside of the third doped region 61. The doping types of the third doping region 61 and the fourth doping region 62 are opposite, and the doping types of the third doping region 61 and the fifth doping region 63 are the same.
Further, the fourth doping region 62 extends into the third doping region 61 from the side of the second trench 64 to a greater extent than the fifth doping region 63 extends into the third doping region 61 from the side of the second trench 64; the fourth doped region 62 extends below the gate dielectric layer.
Further, the upper surface of the fourth doped region 62 is flush with the upper surface of the semiconductor substrate.
The notch region includes a notch region adjacent to the field limiting ring (outermost notch region) and a notch region not adjacent to the field limiting ring (non-outermost notch region). The fourth doped region 62 of the non-outermost scribe region may be partially different from the fourth doped region 62 of the outermost scribe region.
The fourth doping region 62 of the non-outermost etched region may extend from both side portions of the second trench 64 toward the third doping region 61, respectively.
The fourth doping region 62 of the outermost etched region extends from the side of the second trench 64 of the outermost etched region far away from the field limiting ring to the third doping region 61; the second trench 64 of the outermost etched region may be provided with the fourth doped region 62 at a side portion close to the field limiting ring, or may not be provided with the fourth doped region 62.
The dielectric layers may be two layers, such as a first dielectric layer 91 and a second dielectric layer 92 shown in fig. 1, projections of the two dielectric layers on the upper surface of the semiconductor substrate are completely overlapped, and the two dielectric layers completely cover the polysilicon gate between the two etched regions and partially cover the semiconductor substrate near the polysilicon gate.
In practical application, the breakdown voltage of a conventional IGBT device can generally reach 1200V, while the breakdown voltage of the IGBT device provided by the embodiment can reach several kilovolts, so that the IGBT device is particularly suitable for application fields with very high requirements on the breakdown voltage, such as rail transit, smart grid, and the like.
The field limiting rings and junction termination extension structures are described in detail below:
in two adjacent field limiting rings, the depth of the first doped region 40 of the inner field limiting ring is greater than or equal to the depth of the first doped region 40 of the outer field limiting ring; the first doped regions 40 of at least two of the plurality of field limiting rings have different depths.
Specifically, the semiconductor substrate includes an active region, which refers to a region forming a function of an IGBT device, and a termination region surrounding the active region. A plurality of first grooves 30 are formed on the upper surface of the terminal region, and the bottoms of the first grooves 30 are positioned in the semiconductor substrate; the first doped regions 40 extend from the bottom and the side of the first trench 30 to the periphery, that is, the first doped regions 40 extend longitudinally from the bottom of the first trench 30 to the lower surface of the termination region and laterally from the side of the first trench 30 to the surrounding region thereof, and finally, the adjacent first doped regions 40 are contacted and even overlapped, so that the first doped regions 40 of all the field limiting rings form the whole ion doped region in the semiconductor substrate. In other words, the orthographic projection of the first doped region 40 on the upper surface of the termination region completely covers the orthographic projection of the first trench 30 on the upper surface of the termination region, and the orthographic projections of adjacent first doped regions 40 on the upper surface of the termination region contact or overlap.
The junction termination extension structure is located in the termination region and further away from the active region relative to the plurality of field limiting rings. The junction termination extension structure includes a second doped region 50 having an orthographic projection of the second doped region 50 at the upper surface of the termination region contacting or overlapping an orthographic projection of the adjacent first doped region 40 at the upper surface of the termination region. In this way, the second doped region 50 and all of the first doped regions 40 collectively form an entire doped region within the semiconductor substrate.
Fig. 2 is a schematic diagram of a plurality of first trenches in an IGBT device according to an embodiment of the present invention, in which a shaded portion is an un-etched portion on a semiconductor substrate, and a blank between two shaded portions is the first trench. The illustration is made with the active region (not shown) on the right side of fig. 2.
Referring to fig. 1 in combination with fig. 2, the first trenches 30 are respectively marked as a 1 st first trench, a 2 nd first trench, \ 8230, an i-1 st first trench, and an i-th first trench according to a sequence from a near distance to a far distance between the first trenches 30 and the active region. The depth of the 1 st first trench is recorded as D 1 The depth of the 2 nd first trench is denoted as D 2 823060, 82301 th first groove with depth D i-1 The depth of the ith first trench is recorded as D i . Wherein D is i ≤D i-1 And D is i ＜D 1 ，i≥2。
In the IGBT device provided in this embodiment, as the distance between the first trenches 30 and the active region is from close to far, the depths of the plurality of first trenches 30 as a whole tend to decrease, and correspondingly, the depths of the first doped regions 40 in the semiconductor substrate as a whole also tend to decrease; on this basis, because the degree of depth in second doping region 50 is no longer than the degree of depth in adjacent first doping region 40, consequently, compare with current field limiting ring, the utility model provides a terminal junction radius of curvature that junction terminal extension-field limiting ring composite construction formed is bigger to the voltage resistance of IGBT device has been improved. And because the radius of curvature of the terminal junction is larger, the electric field density is smaller, and the electric leakage problem of the IGBT device is also improved.
The following describes each structure of the IGBT device in detail:
in this embodiment, an epitaxial wafer or a single wafer can be used as the semiconductor substrate. The single crystal wafer can be a silicon single crystal wafer, a silicon carbide single crystal wafer and the like which are commonly used for preparing IGBT devices. The epitaxial wafer may be obtained commercially, or may be obtained by depositing an epitaxial layer on the surface of a single wafer by an epitaxial process such as CVD (Chemical Vapor Deposition) or PVD (Physical Vapor Deposition).
For the case of an epitaxial wafer as a semiconductor substrate, referring to fig. 4, the semiconductor substrate includes a substrate 10 and an epitaxial layer 20 located on an upper surface of the substrate 10, where the upper surface of the semiconductor substrate refers to a surface of the epitaxial layer 20 on a side far from the substrate 10, that is, an upper surface of the epitaxial layer 20; the bottom of the semiconductor base refers to the position where the substrate 10 is located; the lower surface of the semiconductor substrate refers to the lower surface of the substrate 10.
It should be understood that, for a semiconductor substrate obtained by depositing the epitaxial layer 20 on the surface of the substrate 10, the depth of the first trench 30 is smaller than the thickness of the epitaxial layer 20, and the bottom of the first trench 30 is located within the epitaxial layer 20. The depth of the first doped region 40 does not exceed the thickness of the epitaxial layer 20, i.e., the bottom of the first doped region 40 is at a distance from the upper surface of the substrate 10.
Optionally, each field limiting ring includes a first trench 30 formed in the upper surface of the termination region of the semiconductor substrate, and a first doped region 40 extending from the bottom of the first trench 30 to the lower surface of the semiconductor substrate, the first doped region 40 extending from the side of the first trench 30 to the periphery.
Before ions are injected into the first trench 30 to form the first doped region 40, an oxide layer does not need to be grown on the upper surface of the semiconductor substrate, so that the thermal budget of the IGBT device in the preparation process is reduced, the diffusion of the transition region is reduced, and the voltage resistance of the IGBT device is further improved.
In an IGBT device, the field limiting rings define an active region. In the present embodiment, a plurality of first trenches 30 are disposed around the active region, and more specifically, the innermost first trench 30 defines the active region. In some embodiments, the projected shape of the plurality of first trenches 30 on the upper surface of the semiconductor substrate matches the projected shape of the active region on the upper surface of the semiconductor substrate. For example, the projection of the active region on the upper surface of the semiconductor substrate is circular, and the projection of the first trench 30 on the upper surface of the semiconductor substrate is circular; the projection of the active region on the upper surface of the semiconductor substrate is polygonal (such as square), the projection of the first trench 30 on the upper surface of the semiconductor substrate is polygonal ring (such as square ring), and the corners of the polygon are chamfers. Of course, the first trench 30 may also have other shapes, and accordingly, the active region may also have other adaptive shapes, which is not limited in this embodiment. In other embodiments, the projection shape of the plurality of first trenches 30 on the upper surface of the semiconductor substrate does not absolutely match the shape of the active region, for example, the projection of the first trenches 30 on the upper surface of the semiconductor substrate is a circle, and the projection of the active region on the upper surface of the semiconductor substrate is a square ring.
Optionally, the plurality of first trenches 30 are concentric first trenches, which surround the active region; in other words, the projections of the plurality of first trenches 30 on the upper surface of the semiconductor substrate are concentrically arranged.
Referring to fig. 2 and 3, in order from the near to the far of the first trench 30 from the active region, the first trenches include a 1 st first trench 31, a 2 nd first trench 32, a 3 rd first trench 33, and a 4 th first trench 34, the 1 st first trench 31 defines the active region, the 2 nd first trench 32 surrounds the outside of the 1 st first trench 31, the 3 rd first trench 33 surrounds the outside of the 2 nd first trench 32, the 4 th first trench 34 surrounds the outside of the 3 rd first trench 33, and the 1 st first trench 31, the 2 nd first trench 32, the 3 rd first trench 33, and the 4 th first trench 34 overlap with each other in a projection center of the upper surface of the semiconductor substrate.
Correspondingly, according to the sequence from the near to the far of the first doping region 40 from the active region, the plurality of first doping regions 40 are the 1 st first doping region 41, the 2 nd first doping region 42, the 3 rd first doping region 43 and the 4 th first doping region 44 in sequence; the 1 st first doping region 41, the 2 nd first doping region 42, the 3 rd first doping region 43 and the 4 th first doping region 44 overlap in the center of the projection of the upper surface of the semiconductor substrate.
Optionally, as the distance between the plurality of first trenches 30 and the active region is increased from near to far, the depth of the plurality of first trenches 30 decreases, i.e. D 1 ＞D 2 ……＞D i-1 ＞D i . Such as depth D of the 1 st first trench 31 1 Greater than the depth D of the 2 nd first trench 32 2 Depth D of the 2 nd first groove 32 2 Greater than the depth D of the 3 rd first trench 33 3 Depth D of the 3 rd first groove 33 3 Greater than the depth D of the 4 th first trench 34 4 . Further, as the distance between the first trenches 30 and the active region is from near to far, the depths of the first trenches 30 are arranged in an arithmetic series, for example, the depth D of the 1 st first trench 31 1 Is 4 μm, and the depth D of the 2 nd first trench 32 2 3 μm, depth D of the 3 rd first trench 33 3 2 μm, depth D of the 4 th first trench 34 4 Is 1 micron.
Accordingly, as the distance between the first trenches 30 and the active region decreases, the depth of the doped regions 40 in the semiconductor substrate decreases, and the doped regions are further arranged in an arithmetic progression. For example, the depth of the 1 st first doping region 41 in the semiconductor substrate is 5 micrometers, the depth of the 2 nd first doping region 42 in the semiconductor substrate is 4 micrometers, the depth of the 3 rd first doping region 43 in the semiconductor substrate is 3 micrometers, and the depth of the 4 th first doping region 44 in the semiconductor substrate is 2 micrometers. Therefore, the field limiting rings form approximate parallel plane junctions, so that the density of electric field lines is reduced, the voltage resistance of the IGBT device is further improved, and electric leakage is reduced to a certain extent.
Optionally, with moreThe distance between the first trenches 30 and the active region is from near to far, and the width of the first trenches 30 is from wide to narrow. Specifically, the width of the 1 st first trench 30 is denoted as W 1 The width of the 2 nd first trench 30 is denoted as W 2 8230the width of the i-1 th first trench 30 is denoted as W i-1 The width of the ith first trench 30 is denoted as W i Wherein W is 1 ＞W 2 ……＞W i-1 ＞W i . Therefore, the curvature radius of a terminal junction formed by the field limiting rings can be further increased, the withstand voltage of the IGBT device is improved on one hand, and the electric leakage can be reduced on the other hand.
Optionally, as the distance between the plurality of first trenches 30 and the active region is from near to far, the widths of the plurality of first trenches 30 are arranged in an arithmetic progression; for example, the width W of the 1 st first trench 31 1 5.5 μm, width W of the 2 nd first trench 32 2 5 μm, the width W of the 3 rd first trench 33 3 Is 4.5 μm, and the width W of the 4 th first trench 34 4 And was 4 μm. Therefore, the field limiting rings form an approximately parallel plane junction, the curvature radius is further increased, the electric field line density is further reduced, the withstand voltage is further improved, and the electric leakage is reduced.
Alternatively, the distance between the center positions of every two adjacent first grooves 30 is a fixed preset value.
Referring to fig. 2, according to the sequence of the distances between the first trenches and the active region from near to far, the plurality of first trenches are respectively the 1 st first trench, the 2 nd first trench, \ 8230, the i-1 st first trench and the i-th first trench. In this case, the 1 st first groove has a center position x 1 The reserved width of the 1 st first trench (the width between the 1 st first trench and the 2 nd first trench) is w 1 (ii) a The 2 nd first groove has a center position x 2 The reserved width of the 2 nd first trench is w 2 (ii) a 8230; the central position of the (i-1) th first groove is x i-1 The remaining width of the i-1 st first trench is w i-1 (ii) a The central position of the ith first groove is x i The reserved width of the ith first trench is w i 。
In case of applying a Lateral Variation of Doping (VLD), the above fixed preset values satisfy:
wherein a is the distance between the center positions of every two adjacent first grooves, and x 1 Is the central position of the 1 st first trench, x n Is the central position of the nth first groove, and n is less than or equal to i; χ is the characteristic diffusion length; d is the diffusion coefficient of the impurities, and t is the high-temperature junction pushing time.
Optionally, the fixed preset value further satisfies:
wherein a is the distance between the center positions of every two adjacent first trenches, W i Is the width of the ith first trench, C 0 Maximum impurity concentration, x, of VLD i Is the central position of the ith first trench, C (x) i ) As a function of the impurity concentration profile of VLD.
By adopting the technical scheme, any doping concentration distribution of VLD can be realized.
The second doped region 50 of the junction termination extension structure extends from the upper surface of the semiconductor substrate into the semiconductor substrate and contacts or overlaps with the adjacent first doped region 40, so that the electric field of the junction termination extension structure and the electric field of the field limiting ring form a continuous electric field; the depth of the second doping region 50 is less than or equal to the depth of the first doping region 40 of the adjacent field limiting ring, so that the curvature radius of the terminal junction is increased, and the withstand voltage of the IGBT device is improved.
In this embodiment, the second doped region 50 of the junction termination extension structure can be obtained by implanting ions and annealing. The second doped region 50 forming the junction termination extension structure is implanted with the same type of ions as the first doped region 40 forming the field limiting ring.
The relationship between the ion implantation dose concentration of the second doping region 50 of the junction termination extension structure and the withstand voltage curve of the IGBT device is: with the increase of the implantation dose concentration, the withstand voltage rises first and then falls. Generally, the higher the withstand voltage of the IGBT device, the higher the required implantation dose; in the specific implementation process, the injection dosage can be reasonably determined according to the voltage withstanding requirement of the IGBT device.
With further reference to fig. 1, the second doped region 50 includes an ion implanted region and an ion diffusion region, wherein the ion implanted region refers to a doped region formed during an ion implantation process; the ion diffusion region refers to a doped region formed by further diffusion of ions into the semiconductor substrate during annealing. It will be appreciated that the ion diffusion region surrounds the ion implantation region. In this embodiment, the width of the ion implantation region is greater than the width of the first trench 30 in the outermost field limiting ring. In a specific implementation, the above structure may be achieved by controlling the ion implantation window during the process of forming the second doping region 50, for example, the ion implantation window width is greater than the width of the adjacent first trench 30. Through the structure, the electric field lines of the junction terminal extension-field limiting ring composite structure far away from the end part of the active area are more gentle, so that the voltage resistance of the IGBT is favorably improved, the electric field line density of the junction of the second doping area 50 of the junction terminal extension structure and the adjacent first doping area 40 is reduced, and the electric leakage problem of the IGBT device is improved.
The following is an exemplary description of the manufacturing process of the IGBT device, and first, the manufacturing process of the field limiting ring and the junction termination extension structure of the IGBT device is described.
As shown in fig. 4, the semiconductor substrate includes a substrate 10 and an epitaxial layer 20 on a surface of the substrate 10.
As shown in fig. 5, a mask 100 is formed on the upper surface of the epitaxial layer 20, and specifically, a photoresist may be first coated on the upper surface of the semiconductor substrate, and then the photoresist may be subjected to a patterning process to obtain the mask 100. Wherein fig. 5 is a longitudinal sectional view of this step and fig. 6 is a top view of this step. The areas of the top surface of epitaxial layer 20 not covered by mask 100 are shown as areas where first trenches 30 are subsequently formed.
As shown in fig. 7, the epitaxial layer 20 not covered by the mask 100 is etched to form a plurality of first trenches 30. Further, the deeper the depth of the first trench 30, the wider the width of the first trench 30, the closer to the active region (taking the active region on the right side in fig. 5 and 7 as an example). The wider the first trench 30, the faster the etching rate due to the loading effect, so the above-described profile can be obtained by one-step etching by controlling the etching process or the like. Of course, it is also possible to etch several times according to actual requirements to obtain the desired distribution of the first trenches 30.
Under the protection of the mask 100, the epitaxial layer 20 is ion implanted through the first trench 30, then the mask 100 is removed, and then a high temperature oxidation push junction is performed, thereby forming a doped region 40, as shown in fig. 8. Of course, the volume of the doped region may be further enlarged during subsequent processing due to the inevitable thermal processes involved.
Referring further to fig. 8, the first trench 30 is further filled with an insulating layer 70, which may be an oxide layer formed during the high temperature oxidation push junction process, the oxide layer being formed on the surface of the epitaxial layer 20 and in the first trench 30. Since the oxidation rate in the first trench 30 is greater than that of the surface of the epitaxial layer 20, an oxide layer having a substantially flat surface can be finally formed. Of course, the insulating layer 70 may be formed by other deposition processes, and is not particularly limited.
In the above steps, before ion implantation, an oxide layer does not need to be deposited on the epitaxial layer 20 for protection, but ions are directly implanted into the first trench 30, which reduces the thermal budget and shortens the process cycle. And because the thermal budget is reduced, the diffusion of the transition region is reduced, and the withstand voltage of the IGBT device is further improved.
From another perspective, to obtain the same withstand voltage, the present invention can suitably reduce the thickness of the semiconductor substrate, and particularly, the thickness of the epitaxial layer 20, so that Rdson (resistance) is reduced. In addition, the reduction in thickness of the epitaxial layer 20 and the semiconductor substrate is also advantageous for the miniaturization of the IGBT device.
As shown in fig. 9, a mask 100 is formed on the insulating layer 70, and specifically, a photoresist may be first coated on the upper surface of the insulating layer 70, and then the photoresist may be subjected to a patterning process, resulting in the mask 100. Fig. 9 is a longitudinal sectional view of this step, and fig. 10 is a top view of this step. The area of the top surface of the insulating layer 70 not covered by the mask 100 in fig. 9 is an implantation window for the subsequent formation of a junction termination extension structure. During the process of etching the insulating layer 70 to form the implantation window, a certain thickness of the insulating layer 70 may be remained, for example, a thinner insulating layer 70 is remained on the surface of the epitaxial layer 20 in a region corresponding to the implantation window to protect the epitaxial layer 20 during the subsequent ion implantation process. It is of course also possible to etch the insulating layer 70 corresponding to the implantation window completely, resulting in the structure shown in fig. 11. Fig. 12 is a view for showing a relative position relationship of an implantation window of a junction termination extension structure and a first trench 30 of a field limiting ring, and as shown in fig. 12, the width of the implantation window is larger than that of an adjacent first trench 30.
And performing ion implantation through the ion implantation window and annealing to form a second doped region 50 of the junction terminal extension structure shown in fig. 13, wherein the doping type of the second doped region 50 is the same as that of the first doped region 40, and an orthographic projection of the second doped region 50 on the upper surface of the terminal region is in contact with or overlaps with an orthographic projection of the adjacent first doped region 40 on the upper surface of the terminal region. In this way, the second doped region 50 and all of the first doped regions 40 together form the entire doped region within the semiconductor substrate. The depth of the second doping region 50 is less than or equal to the depth of the first doping region 40 of the outermost field limiting ring; preferably, the depth of the second doping region 50 is less than the depth of the first doping region 40 of the outermost field limiting ring.
The following is a description of the process of forming the etching region of the IGBT device.
As shown in fig. 14, an insulating layer 70 is first deposited on the upper surface of the epitaxial layer, a polysilicon layer 80 is then deposited on the upper surface of the insulating layer, and then the polysilicon layer 80 and the insulating layer 70 are etched to form a first implantation window, and ion implantation and junction pushing are performed on the first implantation window to form a third doping region 61, it is understood that the width of the third doping region 61 is greater than the width of the first implantation window, and the third doping region 61 extends to the lower portion of the polysilicon layer 80 on both sides of the first implantation window. For the N (Negative) type epitaxial layer, P-type ions can be implanted into the first implantation window and junction pushing can be performed through a thermal process to form a P-well region (third doped region 61); for P (Positive) type epitaxial layer, N type ions can be implanted into the first window and the junction can be pushed by thermal process to form an N well region (third doped region 61).
Referring to fig. 15, ion implantation is continued to be performed in the first implantation window, and then high temperature annealing is performed to form a fourth doping region 62, wherein the depth of the fourth doping region 62 is smaller than the depth of the third doping region 61, and the width of the fourth doping region 62 is smaller than the width of the third doping region 61. For example, in the case that the third doped region 61 is a P-well region, N-type ions may be continuously implanted into the first implantation window and then annealed at a high temperature to form an N-well region (the fourth doped region 62); in the case where the third doped region 61 is an N-well region, P-type ions may be continuously implanted into the first implantation window and high-temperature annealing is performed to form a P-well region (the fourth doped region 62).
Then, a mask 100 is formed on the surface of the epitaxial layer 20 and the surface of the polysilicon layer 80 to form a second implantation window as shown in fig. 16, wherein the width of the second implantation window is smaller than the width of the fourth doping region 62.
Performing ion implantation and junction pushing in the second implantation window to form a fifth doping region 63 shown in fig. 17, wherein the depth of the fifth doping region 63 is greater than the depth of the fourth doping region 62 and less than the depth of the third doping region 61; the width of the fifth doping region 63 is smaller than the width of the fourth doping region 62. For the N-type epitaxial layer, P-type ions can be implanted into the second implantation window and junction pushing is performed to form a fifth doped region 63; for the P-type epitaxial layer, N-type ions may be implanted into the second implantation window and junction pushed to form the fifth doped region 63.
Then depositing a dielectric layer on the upper surface of the structure, for example, sequentially depositing a first dielectric layer 91 and a second dielectric layer 92, and then patterning the dielectric layers to form an etching window, wherein the width of the etching window is smaller than that of the fifth doped region 63; after the dielectric layer is etched, the epitaxial layer 20 with the set depth is continuously etched to obtain a second trench 64, and the structure shown in fig. 18 is formed; the set depth here is larger than the depth of forming the fourth doping region 62 and smaller than the ion implantation depth of forming the fifth doping region 63.
In other embodiments, after the third doped region 61 and the fourth doped region 62 are formed, the deposition of the dielectric layer, the etching of the dielectric layer and the epitaxial layer may be performed to obtain the second trench 64, and then the ion implantation and the junction push may be performed based on the second trench 64 to form the fifth doped region 63. Compared to the manufacturing method in the foregoing embodiment, the method of this embodiment can make the doping ions in the fifth doping region 63 as less as possible "neutralized" by other doping ions in the epitaxial layer 20, thereby reducing the consumption of the doping ions.
According to the two embodiments, the second trench 64 and the fifth doped region 63 are formed in different orders, and the morphology of the fifth doped region 63 is different. For the way of forming the fifth doped region 63 first and then forming the second trench 64, the surface of the fifth doped region 63 is flush with the upper surface of the epitaxial layer 20; conversely, the surface of the fifth doped region 63 is lower than the upper surface of the epitaxial layer 20.
Finally, with reference to fig. 19, metal deposition is performed on the upper surface of the above structure to form the emitter 110. Of course, after the emitter 110 is formed, conventional process steps in the IGBT manufacturing process, such as wafer thinning, are also included, and are not described herein again.
A second aspect of the present invention provides a chip including the IGBT device in the foregoing embodiment. Specifically, the chip may be a product obtained by packaging the IGBT.
In the description of the present invention, the terms "upper", "lower", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience of description of the present invention, but do not require the present invention to be constructed and operated in a specific orientation, and thus, cannot be construed as limiting the present invention.
The particular features, structures, materials, or characteristics described in this disclosure may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations of the above embodiments may be made by those of ordinary skill in the art without departing from the scope of the present invention.
Claims (10)
1. An IGBT device, characterized by comprising:
a semiconductor substrate;
the field limiting rings are arranged at intervals, wherein the innermost field limiting ring defines an active region; each field limiting ring comprises a first groove formed on the upper surface of the semiconductor substrate and first doping regions extending from the side parts and the bottom parts of the first grooves into the semiconductor substrate, and the first doping regions of adjacent field limiting rings are contacted or overlapped;
the junction terminal extension structure surrounds the outer sides of the field limiting rings and comprises a second doping area, the second doping area extends inwards from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate, and the second doping area is in contact with or overlapped with the first doping area in the field limiting ring at the outermost side; the depth of the second doping region is less than or equal to the depth of the first doping region in the outermost field limiting ring;
a plurality of etched regions in the active region, each of the etched regions including a second trench formed in the upper surface of the semiconductor substrate and a third doped region extending from the side and bottom of the second trench into the semiconductor substrate; the depth of the third doped region of the outermost etched region adjacent to the innermost field limiting ring is less than or equal to the depth of the first doped region of the innermost field limiting ring; the third doped region of the outermost etched region is in contact with or overlapped with the first doped region of the innermost field limiting ring;
wherein the depth of the second doped region, the depth of the first doped region in the outermost field limiting ring, and the depth of the third doped region of the outermost etched region are not all the same.
2. The IGBT device of claim 1, wherein the depth of the second doped region is less than the depth of the first doped region; the depth of the first doped region closest to the active region is greater than the depth of the third doped region.
3. The IGBT device according to claim 1 or 2, characterized in that, in two adjacent field limiting rings, the depth of the first doped region of the inner field limiting ring is greater than or equal to the depth of the first doped region of the outer field limiting ring; the depths of the first doped regions of at least two field limiting rings in the field limiting rings are different;
the second doping region comprises an ion implantation region and an ion diffusion region, wherein the ion diffusion region surrounds the ion implantation region; the width of the ion implantation area is larger than that of the groove in the field limiting ring at the outermost side.
4. The IGBT device of claim 3, wherein the depth of the first doped region in a plurality of the field limiting rings is progressively distributed.
5. The IGBT device of claim 1 or 2, wherein the etched region further comprises a fourth doped region and a fifth doped region located in the third doped region, wherein the fourth doped region extends from the second trench side into the third doped region, and the fifth doped region extends from the second trench side and the bottom into the third doped region.
6. The IGBT device of claim 5, wherein the fourth doped region extends from the second trench side into the third doped region to a greater extent than the fifth doped region extends from the second trench side into the third doped region.
7. The IGBT device of claim 5, wherein the fourth doped region of the outermost etched region extends into the third doped region from a side of the second trench of the outermost etched region distal from the field limiting ring.
8. The IGBT device according to claim 6 or 7, wherein the upper surface of the fifth doped region is lower than the upper surface of the semiconductor substrate or the upper surface of the fifth doped region is flush with the upper surface of the semiconductor substrate.
9. The IGBT device of claim 5, wherein the bottom of the fourth doped region is a greater distance from the lower surface of the semiconductor substrate than the bottom of the fifth doped region.
10. A chip comprising the IGBT device according to any one of claims 1 to 9.
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| CN117711938A (en) * | 2024-02-05 | 2024-03-15 | 深圳腾睿微电子科技有限公司 | Isolation groove type terminal IGBT device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117711938A (en) * | 2024-02-05 | 2024-03-15 | 深圳腾睿微电子科技有限公司 | Isolation groove type terminal IGBT device and manufacturing method thereof |
| CN117711938B (en) * | 2024-02-05 | 2024-06-14 | 深圳腾睿微电子科技有限公司 | Isolation groove type terminal IGBT device and manufacturing method thereof |
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