CN216250738U - Power semiconductor device and chip - Google Patents
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- CN216250738U CN216250738U CN202123026017.9U CN202123026017U CN216250738U CN 216250738 U CN216250738 U CN 216250738U CN 202123026017 U CN202123026017 U CN 202123026017U CN 216250738 U CN216250738 U CN 216250738U
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Abstract
The embodiment of the utility model provides a power semiconductor device and a chip. The power semiconductor device includes: a semiconductor substrate; a plurality of field limiting rings arranged at intervals, wherein the innermost field limiting ring defines an element region; each field limiting ring comprises a groove formed on the upper surface of the semiconductor substrate and doped regions extending from the side parts and the bottom parts of the groove into the semiconductor substrate, and the doped regions of the adjacent field limiting rings are contacted or overlapped; the distance from the bottom of the doped region of the inner side field limiting ring to the lower surface of the semiconductor substrate is not more than the distance from the bottom of the doped region of the outer side field limiting ring to the lower surface of the semiconductor substrate; in the field limiting rings, the distances from the bottoms of the doped regions of at least two field limiting rings to the lower surface of the semiconductor substrate are different. The power semiconductor device provided by the embodiment of the utility model can improve the withstand voltage of the device and reduce the electric leakage of the device.
Description
Technical Field
The utility model relates to the technical field of semiconductors, in particular to a power semiconductor device and a chip.
Background
The Power semiconductor Device is also called a Power Electronic Device (Power Electronic Device). Typical power Semiconductor devices mainly include power diodes, thyristors, Metal-Oxide-Semiconductor Field Effect transistors (MOSFETs). Early power semiconductor devices were used primarily in industry and power systems. With the rapid development of new power semiconductor devices represented by power MOSFET devices, power semiconductor devices have been widely used in 4C industries represented by computers, traffic, consumer electronics, and automotive electronics.
In most cases, the power semiconductor device is used as a switch, and therefore, it is required to have a better withstand voltage to meet the requirement of low power loss. The Field Limiting Ring (FLR) is an effective means for increasing the withstand voltage of the power semiconductor device. Taking an epitaxial wafer as an example, in the conventional technology, an oxide layer with a certain thickness is grown on the surface of an epitaxial layer, and then patterning is performed on the oxide layer, so that a plurality of injection windows are formed in the oxide layer corresponding to a terminal region; and then, carrying out ion implantation on the epitaxial layer through the implantation window, and then oxidizing and pushing the junction at high temperature to finally form a plurality of field limiting rings with the same implantation depth. Because the terminal region is slowly pulled open in a gradient manner in the transverse direction and the longitudinal direction, the electric field concentration is effectively slowed down, and the withstand voltage of the device can be improved by the field limiting ring.
However, although the field limiting ring can satisfy the voltage withstanding performance of the power semiconductor device, the leakage current of the device is large, and the application of the power semiconductor device is limited.
SUMMERY OF THE UTILITY MODEL
In order to solve the above technical problems, embodiments of the present invention provide a power semiconductor device and a chip to reduce leakage while ensuring a withstand voltage.
A first aspect of the present invention provides a power semiconductor device, including:
a semiconductor substrate;
a plurality of field limiting rings arranged at intervals, wherein the innermost field limiting ring defines an element region;
each field limiting ring comprises a groove formed on the upper surface of the semiconductor substrate and doped regions extending from the side parts and the bottom parts of the groove into the semiconductor substrate, and the doped regions of the adjacent field limiting rings are contacted or overlapped;
in two adjacent field limiting rings, the distance from the bottom of the doped region of the inner field limiting ring to the lower surface of the semiconductor substrate is not greater than the distance from the bottom of the doped region of the outer field limiting ring to the lower surface of the semiconductor substrate; in the field limiting rings, the distances from the bottoms of the doped regions of at least two field limiting rings to the lower surface of the semiconductor substrate are different.
Further, as the distance between the plurality of grooves and the element region is from near to far, the depth of the groove close to the element region is larger than or equal to the depth of the groove far from the element region; at least two of the plurality of grooves have different depths.
Further, the depth of the plurality of grooves is arranged in an arithmetic progression with the distance from the plurality of grooves to the element region from near to far.
Further, the plurality of trenches have a width from wide to narrow as the plurality of trenches are located closer to the device region.
Further, the widths of the plurality of grooves are arranged in an arithmetic progression with the distance from the plurality of grooves to the element region from near to far.
Further, the distance between the center positions of every two adjacent grooves is a fixed preset value.
Further, the projection of the groove on the upper surface of the semiconductor substrate is a polygonal ring, and the corner of the polygon is a chamfer; alternatively, the projection of the trench on the upper surface of the semiconductor substrate is a circular ring shape.
Further, the projections of the plurality of grooves on the upper surface of the semiconductor substrate are concentrically arranged.
Further, the semiconductor substrate comprises a substrate and an epitaxial layer, and the doped region is located in the epitaxial layer.
Further, the field limiting ring further comprises an insulating layer located in the trench.
A second aspect of the utility model provides a chip comprising the power semiconductor device of the first aspect.
The power semiconductor device provided by the utility model has the following technical effects:
in the power semiconductor device, the distances between each field limiting ring and the element region are different, and the depth of the doped region formed at the bottom of the trench in the semiconductor substrate tends to be reduced as the distance between the field limiting ring and the element region is reduced from near to far. Therefore, compared with the existing field limiting ring, the electric field formed by the field limiting ring has larger curvature radius, so that the electric leakage problem of the power semiconductor device is improved on the premise of improving the pressure resistance of the power semiconductor device.
Furthermore, because the doped regions are formed at the bottom and the side of the trench, the depth of the doped regions can be adjusted by controlling the depth, the width and the like of the trench, so that the curvature radius of an electric field formed by the field limiting ring can be controlled, and the voltage resistance and the leakage problem of the power semiconductor device can be controlled.
Compared with the prior art that the doped region of the field limiting ring is formed by performing ion implantation and diffusion on the upper surface of the semiconductor substrate, the doped region of the field limiting ring is formed by performing ion implantation and diffusion through the groove, namely, an oxide layer does not need to grow on the surface of the semiconductor substrate in the process of manufacturing the field limiting ring, ions can be directly implanted into the groove and pushed to form the doped region at high temperature, the thermal budget is reduced, the diffusion of a transition region is reduced, and the withstand voltage of the power semiconductor device is further improved.
Drawings
Fig. 1 is a schematic structural diagram of a power semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a plurality of trenches in a power semiconductor device according to an embodiment of the present invention;
fig. 3 to fig. 7 are schematic structural diagrams of partial steps in a manufacturing process of a power semiconductor device according to an embodiment of the present invention.
Detailed Description
So that the manner in which the features and aspects of the embodiments of the present invention can be understood in detail, a more particular description of the embodiments of the utility model, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other cases, well-known structures may be shown simplified or even omitted to simplify the drawing. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
In the prior art, a process for forming a field limiting ring includes forming an oxide layer mask on a surface of a semiconductor substrate, and then performing ion implantation and high-temperature junction pushing, thereby forming a plurality of doping regions arranged in a concentric ring in the semiconductor substrate. The oxide layer mask is also used for protecting the semiconductor substrate in the ion implantation process so as to avoid damage. The curvature radius of the junction formed after the process is performed is small, and the electric field density is concentrated, so that the electric leakage is large.
Based on the above, the utility model provides a solution to reduce the leakage current while ensuring or improving the withstand voltage of the power semiconductor device.
Fig. 1 is a schematic structural diagram of a power semiconductor device according to an embodiment of the present invention. Fig. 1 is a cross-sectional view, which is exemplarily illustrated with a device region (not shown) located on the right side of fig. 1. Referring to fig. 1, the power semiconductor device provided in this embodiment includes a plurality of field limiting rings arranged at intervals, where an innermost field limiting ring defines an element region; each field limiting ring comprises a groove 30 formed on the upper surface of the semiconductor substrate and a doped region 40 extending from the bottom and the side of the groove 30 to the lower surface of the semiconductor substrate and to the ring side of the groove 30, and the doped regions 40 of adjacent field limiting rings are contacted or overlapped; in two adjacent field limiting rings, the distance from the bottom of the doped region 40 of the inner field limiting ring to the lower surface of the semiconductor substrate is not greater than the distance from the bottom of the doped region 40 of the outer field limiting ring to the lower surface of the semiconductor substrate; in the plurality of field limiting rings, the distances from the bottom of the doped region 40 of at least two field limiting rings to the lower surface of the semiconductor substrate are different.
In other words, in the power semiconductor device, the depth of the corresponding doped region 40 generally decreases as the distance between the field limiting ring and the device region decreases. Therefore, compared with the existing field limiting ring, under the condition that the semiconductor substrate is the same, the curvature radius of an electric field formed by the field limiting ring is larger, the density of the electric field is smaller, the voltage withstanding performance of the power semiconductor device is improved, and the electric leakage problem of the power semiconductor device is improved.
In this embodiment, the depth of the doped region 40 refers to the distance between the bottom of the doped region 40 and the upper surface of the semiconductor substrate along the thickness direction of the semiconductor substrate.
In this embodiment, since the doped region 40 is obtained by implanting ions into the semiconductor substrate through the trench 30 and diffusing the ions, in the specific implementation process, the depth of the doped region 40 can be controlled by controlling the depth of the trench 30 in addition to the process conditions such as the implantation energy during the ion implantation process, the temperature during the junction pushing process, and the time. As shown in fig. 1, in two adjacent trenches 30, the depth of the trench 30 close to the device region is greater than or equal to the depth of the trench 30 far from the device region; at least two of the plurality of grooves 30 have different depths.
Fig. 2 is a schematic diagram of a plurality of trenches in a power semiconductor device according to an embodiment of the present invention, where the shaded portions are portions of a semiconductor substrate that are not etched, and a space between two shaded portions is a trench. Fig. 2 is a cross-sectional view, schematically illustrated with a device region (not shown) on the right side of fig. 2. Referring to fig. 1 in conjunction with fig. 2, the plurality of trenches 30 are respectively denoted as a 1 st trench, a 2 nd trench, … th trench, an i-1 th trench, and an i-th trench in order from the near to the far of the trench 30 from the element region. Wherein the depth of the 1 st groove is recorded as D1The depth of the 2 nd trench is recorded as D2… … the depth of the i-1 st groove is recorded as Di-1The depth of the ith groove is recorded as Di. Wherein D isi≤Di-1And Di＜D1，i≥2。
In particular, the semiconductor substrate comprises an element region, which refers to the area where the function of a power semiconductor device is formed, such as for a MOSFET device, the element region is actually the active region, and a termination region surrounding the element region. A plurality of grooves 30 are formed on the upper surface of the terminal area, and the bottoms of the grooves 30 are positioned in the semiconductor substrate; the doped regions 40 extend from the bottom and the side of the trench 30 to the periphery, that is, the doped regions 40 extend longitudinally from the bottom of the trench 30 to the lower surface of the termination region and laterally from the side of the trench 30 to the surrounding region, and finally the adjacent doped regions 40 are contacted and even overlapped, so that the doped regions 40 of all the field limiting rings form the whole ion doped region in the semiconductor substrate. In other words, the orthographic projection of the doped region 40 on the upper surface of the termination region completely covers the orthographic projection of the trench 30 on the upper surface of the termination region, and the orthographic projections of adjacent doped regions 40 on the upper surface of the termination region contact or overlap.
In the power semiconductor device, as the distance between the trench 30 and the element region is reduced from near to far, the depth of the plurality of trenches 30 tends to be reduced as a whole, and accordingly, the depth of the doped region 40 in the semiconductor substrate also tends to be reduced as a whole. Therefore, compared with the existing field limiting ring, under the condition that the semiconductor substrate is the same, the curvature radius of an electric field formed by the field limiting ring is larger, the density of the electric field is smaller, the voltage withstanding performance of the power semiconductor device is improved, and the electric leakage problem of the power semiconductor device is improved.
Further, compared with the prior art that an oxide layer serving as a mask layer and a protection layer is formed on the surface of the semiconductor substrate before ion implantation, in the embodiment, the doped region 40 is formed at the bottom of the trench 30, and an oxide layer does not need to be grown on the surface of the semiconductor substrate during the process of manufacturing the field limiting ring, ions can be directly implanted into the trench 30 and junction is pushed at high temperature to form the doped region 40, so that the thermal budget is reduced.
The following describes each structure of the power semiconductor device in detail:
in this embodiment, an epitaxial wafer or a single wafer can be used as the semiconductor substrate. The epitaxial wafer may be commercially available, or may be obtained by forming the epitaxial layer 20 on the upper surface of the substrate 10 by using a Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process. The following description will be given by exemplifying the semiconductor substrate as an epitaxial wafer.
In the case of an epitaxial wafer as a semiconductor substrate, the upper surface of the semiconductor substrate refers to the surface of the epitaxial layer 20 on the side away from the substrate 10, that is, the upper surface of the semiconductor substrate refers to the upper surface of the epitaxial layer 20; accordingly, the lower surface of the semiconductor substrate refers to the lower surface of the substrate 10; the bottom of the semiconductor base refers to the position where the substrate 10 is located. The upper surface of the semiconductor substrate is formed with a plurality of trenches 30, that is, the upper surface of the epitaxial layer 20 is formed with a plurality of trenches 30, and the trenches 30 are formed by patterning the epitaxial layer 20 using a photoresist as a mask.
It should be understood that for the case of an epitaxial wafer as the semiconductor substrate, the depth of the trench 30 is less than the thickness of the epitaxial layer 20, and the bottom of the trench 30 is located within the epitaxial layer 20. The depth of the doped region 40 does not exceed the thickness of the epitaxial layer 20, i.e., the bottom of the doped region 40 is a certain distance from the upper surface of the substrate 10.
In the power semiconductor device, the field limiting ring is disposed around the element region. In the present embodiment, a plurality of trenches 30 are disposed around the device region, and more specifically, the innermost trench 30 defines the device region. In some embodiments, the projected shape of the plurality of trenches 30 on the upper surface of the semiconductor substrate matches the projected shape of the element region on the upper surface of the semiconductor substrate. For example, the projection of the element region on the upper surface of the semiconductor substrate is circular, and the projection of the trench 30 on the upper surface of the semiconductor substrate is circular; the projection of the device region on the upper surface of the semiconductor substrate is polygonal (e.g., square), the projection of the trench 30 on the upper surface of the semiconductor substrate is polygonal ring (e.g., square ring), and the corners of the polygon are chamfers. Of course, the groove 30 may also take other shapes, and accordingly, the element region may also take other suitable shapes, which is not limited in this embodiment. In other embodiments, the projection shape of the plurality of trenches 30 on the upper surface of the semiconductor substrate does not absolutely match the shape of the device region, such as the projection of the trenches 30 on the upper surface of the semiconductor substrate is a circle and the projection of the device region on the upper surface of the semiconductor substrate is a square ring.
Optionally, the plurality of trenches 30 are concentric trenches, the plurality of concentric trenches surrounding the device region; in other words, the plurality of trenches 30 are concentrically arranged in projection on the upper surface of the semiconductor substrate.
For example, according to the order of the distance between the trench 30 and the device region from near to far, the trenches are sequentially identified as a first trench 31, a second trench 32, a third trench 33 and a fourth trench 34, the first trench 31 defines the device region, the second trench 32 surrounds the outer side of the first groove 31, the third trench 33 surrounds the outer side of the second trench 32, the fourth trench 34 surrounds the outer side of the third trench 33, and the first trench 31, the second trench 32, the third trench 33 and the fourth trench 34 overlap each other in the projection center of the upper surface of the semiconductor substrate.
Correspondingly, according to the sequence from the near to the far of the doped region 40 and the device region, the doped regions 40 are sequentially marked as a first doped region 41, a second doped region 42, a third doped region 43 and a fourth doped region 44; the first doped region 41 defines a device region, the second doped region 42 surrounds the first doped region 41, the third doped region 43 surrounds the second doped region 42, the fourth doped region 44 surrounds the third doped region 43, and the first doped region 41, the second doped region 42, the third doped region 43, and the fourth doped region 44 overlap in the center of the projection of the upper surface of the semiconductor substrate.
Alternatively, the depth of the plurality of trenches 30 decreases as the plurality of trenches 30 are spaced closer to the device region, i.e., D1＞D2……＞Di-1＞Di. Such as depth D of a first trench 31 (corresponding to trench 1 in fig. 2, and similar to that described below, which is not repeated here)1Greater than the depth D of the second trench 322Depth D of the second groove 322Greater than the depth D of the third groove 333The depth D of the third groove 333Greater than the depth D of the fourth trench 344. Further, the depths of the trenches 30 are arranged in an arithmetic progression with the distance from the trenches 30 to the device region from near to far, for example, the depth D of the first trench 3114 μm, depth D of the second trench 3223 μm, depth D of the third trench 3332 microns, the depth D of the fourth trench 344Is 1 micron.
Accordingly, as the distance between the trenches 30 and the device region decreases from near to far, the depth of the doped regions 40 in the semiconductor substrate decreases, and the trenches are further arranged in an arithmetic progression. For example, the first doped region 41 has a depth of 5 microns in the semiconductor substrate, the second doped region 42 has a depth of 4 microns in the semiconductor substrate, the third doped region 43 has a depth of 3 microns in the semiconductor substrate, and the fourth doped region 44 has a depth of 2 microns in the semiconductor substrate. Therefore, the electric field curve formed by the field limiting rings (such as the wavy line surrounding the doped region in fig. 1) changes smoothly, the curvature radius is increased, the density of the electric field lines is reduced, the withstand voltage of the power semiconductor device is further improved, and the electric leakage is reduced.
Alternatively, the width of the plurality of trenches 30 is wide to narrow as the plurality of trenches 30 are closer to the device region. Specifically, the width of the 1 st trench is denoted as W1The width of the 2 nd trench is denoted as W2… … the width of the i-1 th groove is denoted as Wi-1The width of the ith groove is denoted as WiWherein W is1＞W2……＞Wi-1＞Wi. Thus, the curvature radius of the electric field formed by the field limiting rings can be further increased, the withstand voltage of the power semiconductor device is improved, and the electric leakage can be reduced.
Alternatively, the widths of the plurality of trenches 30 are arranged in an arithmetic progression as the distance between the plurality of trenches 30 and the device region is from near to far. Therefore, the electric field curve (such as the wave line in fig. 1) formed by the field limiting rings changes smoothly, the curvature radius is increased, the density of the electric field lines is reduced, the withstand voltage is further improved, and the electric leakage is reduced.
For example, the width W of the first trench 311Is 5.5 μm, and the width W of the second trench 322Is 5 μm, and the width W of the third trench 333Is 4.5 microns, and the width W of the fourth trench 344Is 4 microns.
Alternatively, the distance between the center positions of every two adjacent grooves 30 is a fixed preset value.
Referring to fig. 2, the plurality of trenches are respectively denoted as a 1 st trench, a 2 nd trench, …, an i-1 st trench, and an i-th trench in order of the distance from the trench to the element region from near to far. In this case, the 1 st groove has a center position x1The reserved width of the 1 st trench (the width between the 1 st trench and the 2 nd trench) is w1(ii) a The center position of the 2 nd groove is x2The reserved width of the 2 nd trench is w2(ii) a …, respectively; the central position of the (i-1) th groove is xi-1The reserved width of the i-1 th groove is wi-1(ii) a The central position of the ith groove is xiThe reserved width of the ith groove iswi。
In case of applying a Lateral Variation of Doping (VLD), the above fixed preset values satisfy:
where a is the distance between the center positions of every two adjacent grooves, x1Is the central position of the 1 st trench, xnIs the central position of the nth groove, and n is less than or equal to i; χ is the characteristic diffusion length; d is the diffusion coefficient of the impurity, and t is the high-temperature junction pushing time.
Optionally, the fixed preset value further satisfies:
wherein a is the distance between the center positions of every two adjacent grooves, WiIs the width of the ith trench, C0Maximum impurity concentration, x, of VLDiIs the central position of the ith groove, C (x)i) As a function of the impurity concentration profile of VLD.
By adopting the technical scheme, any doping concentration distribution of VLD can be realized.
The following exemplifies a method for manufacturing the aforementioned power semiconductor device, taking an epitaxial wafer as an example of a semiconductor substrate.
As shown in fig. 3, the semiconductor substrate includes a substrate 10 and an epitaxial layer 20 on a surface of the substrate 10.
As shown in fig. 4 and 5, a mask 60 is formed on the upper surface of the epitaxial layer 20. Specifically, a photoresist may be first coated on the upper surface of the semiconductor substrate, and then the photoresist may be patterned to obtain the mask 60. Wherein fig. 4 is a longitudinal sectional view of this step and fig. 5 is a top view of this step. The areas of the upper surface of epitaxial layer 20 not covered by mask 60 are shown as areas where trenches 30 are subsequently formed.
As shown in fig. 6, the epitaxial layer 20 is patterned by using the mask shown in fig. 5, the area not covered by the mask 60 is etched to form a plurality of trenches 30, and the deeper the depth of the trenches 30 is, the wider the width of the trenches 30 is, the closer to the device region (taking the device region on the right side in fig. 6 as an example). The wider the trench 30, the faster the etching rate due to the loading effect, so that the above-described morphology can be obtained on the basis of one-step etching by controlling the etching process or the like. Of course, it is also possible to etch several times to obtain the desired distribution of the trenches 30 according to actual requirements.
As shown in fig. 7, under the protection of the mask 60, the epitaxial layer 20 is ion-implanted through the trench 30, and after removing the mask 60, junction push-out by high temperature oxidation is performed, thereby forming a doped region 40. The wavy lines around the doped region in fig. 7 represent the electric field.
Referring further to fig. 7, the trench 30 is further filled with an insulating layer 50, which may be an oxide layer formed during a high temperature oxidation push junction process, the oxide layer being formed on the surface of the epitaxial layer 20 and in the trench 30. Since the oxidation rate in the trenches 30 is greater than the oxidation rate of the surface of the epitaxial layer 20, an oxide layer having a substantially flat surface can be formed. Of course, the insulating layer 50 may be formed by other deposition processes, and is not particularly limited.
In the above steps, before ion implantation, an oxide layer is not required to be formed on the epitaxial layer 20 to protect the epitaxial layer 20, but ions are directly implanted into the trench 30, so that the thermal budget is reduced, and the process cycle is shortened. And because the thermal budget is reduced, the diffusion of the transition region is reduced, and the withstand voltage of the power semiconductor device is further improved. In general, the doping concentration of the substrate 10 in the power semiconductor device is higher than that of the epitaxial layer 20, so that ions in the substrate 10 diffuse into the epitaxial layer 20, i.e., the transition region, under the influence of high temperature.
From another perspective, in order to obtain the same withstand voltage, the present invention can suitably reduce the thickness of the semiconductor substrate, and particularly, the thickness of the epitaxial layer 20, so that Rdson (resistance) is reduced. In addition, since the thickness of the epitaxial layer 20 and the semiconductor substrate is reduced, it is also advantageous to miniaturize the power semiconductor device.
A second aspect of the utility model provides a chip comprising the power semiconductor device of the preceding embodiments. Specifically, the chip may be a product obtained by packaging the power semiconductor device.
In the description of the present invention, the terms "upper", "lower", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present invention but do not require that the present invention must be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
The particular features, structures, materials, or characteristics described in this disclosure may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. A power semiconductor device, comprising:
a semiconductor substrate;
a plurality of field limiting rings arranged at intervals, wherein the innermost field limiting ring defines an element region;
each field limiting ring comprises a groove formed on the upper surface of the semiconductor substrate and doped regions extending from the side parts and the bottom parts of the grooves into the semiconductor substrate, and the doped regions of the adjacent field limiting rings are contacted or overlapped;
in two adjacent field limiting rings, the distance from the bottom of the doped region of the inner field limiting ring to the lower surface of the semiconductor substrate is not greater than the distance from the bottom of the doped region of the outer field limiting ring to the lower surface of the semiconductor substrate; and in the field limiting rings, the distances from the bottoms of the doped regions of at least two field limiting rings to the lower surface of the semiconductor substrate are different.
2. The power semiconductor device according to claim 1, wherein a depth of the trench closer to the element region is greater than or equal to a depth of the trench farther from the element region as the plurality of trenches are closer to the element region; at least two of the plurality of grooves have different depths.
3. The power semiconductor device of claim 2, wherein the plurality of trenches are arranged in an arithmetic progression of depths as the plurality of trenches are spaced from the device region from near to far.
4. The power semiconductor device according to claim 2, wherein the plurality of trenches have a width from wide to narrow as the plurality of trenches are located from close to far from the element region.
5. The power semiconductor device of claim 4, wherein the widths of the plurality of trenches are arranged in an arithmetic progression as the distance between the plurality of trenches and the device region is from near to far.
6. The power semiconductor device of claim 5, wherein a distance between center positions of every two adjacent trenches is a fixed preset value.
7. The power semiconductor device according to any one of claims 1 to 6, wherein a projection of the trench on the upper surface of the semiconductor substrate is a polygonal ring, and corners of the polygon are chamfers;
or the projection of the groove on the upper surface of the semiconductor substrate is in a ring shape.
8. The power semiconductor device of claim 7, wherein a projection of the plurality of trenches onto the upper surface of the semiconductor substrate is concentrically arranged.
9. The power semiconductor device of any of claims 1-6, wherein the field limiting ring further comprises an insulating layer in the trench.
10. A chip, comprising: a power semiconductor device according to any one of claims 1 to 9.
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| CN202123026017.9U CN216250738U (en) | 2021-12-02 | 2021-12-02 | Power semiconductor device and chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024109118A1 (en) * | 2022-11-22 | 2024-05-30 | 华润微电子（重庆）有限公司 | Self-aligned trench power device having controllable channel length, and manufacturing method therefor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024109118A1 (en) * | 2022-11-22 | 2024-05-30 | 华润微电子（重庆）有限公司 | Self-aligned trench power device having controllable channel length, and manufacturing method therefor |
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