CN216250741U

CN216250741U - MOSFET device and chip

Info

Publication number: CN216250741U
Application number: CN202123031598.5U
Authority: CN
Inventors: 常东旭; 王振达; 周源; 李静怡; 王超; 朱林迪; 梁维佳; 胡磊; 杨棂鑫; 邢岳
Original assignee: Beijing Yandong Microelectronic Technology Co ltd
Current assignee: Beijing Yandong Microelectronic Technology Co ltd
Priority date: 2021-12-02
Filing date: 2021-12-02
Publication date: 2022-04-08
Anticipated expiration: 2031-12-02

Abstract

The utility model provides a MOSFET device and a chip. The MOSFET device includes a semiconductor substrate; the field limiting rings comprise grooves formed on the upper surface of the semiconductor substrate and first doping regions extending into the semiconductor substrate, and adjacent first doping regions are contacted or overlapped; the junction terminal extension structure surrounds the outer side of the field limiting ring and comprises a second doping region, the second doping region extends from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate, and the second doping region is in contact with or overlapped with the first doping region in the outermost field limiting ring; in the adjacent field limiting rings, the depth of the first doped region of the inner field limiting ring is greater than or equal to that of the first doped region of the outer field limiting ring; the depth of at least two first doping regions in the field limiting rings is different, and the depth of the first doping region in the outermost field limiting ring is larger than or equal to the depth of the second doping region. The MOSFET device provided by the utility model has stronger voltage resistance.

Description

MOSFET device and chip

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a MOSFET device and a chip.

Background

A MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is a Field Effect Transistor in which a gate of a Metal layer (M) controls a Semiconductor (S) through an Oxide layer (O) by the Effect of an electric Field. The MOSFET has the advantages of high input impedance, low noise, good thermal stability, strong radiation resistance and the like, and has the characteristics of small volume, light weight, power saving, long service life and the like. In recent years, with rapid development of MOSFET devices, MOSFETs have been widely used in 4C industries represented by computers, general, consumer electronics, and automotive electronics.

In a MOSFET device, a Field Limiting Ring (FLR) is usually disposed in a termination region thereof to improve a withstand voltage of the device and meet a low power loss requirement. Taking an epitaxial wafer as an example, an oxide layer with a certain thickness can be grown on the surface of the epitaxial layer, patterning is performed on the oxide layer to form a plurality of injection windows, ion injection is performed on the epitaxial layer through the injection windows, and then high-temperature oxidation junction pushing is performed to form a plurality of doped regions with the same diffusion depth. Because the terminal region is slowly pulled open in a gradient manner in the transverse direction and the longitudinal direction, the electric field concentration is effectively slowed down, and the withstand voltage of the device can be improved by the field limiting ring.

However, as the market demands higher and higher performance of products such as computers, consumer electronics, and automotive electronics, higher requirements are also put on the performance, especially the voltage withstanding performance, of the MOSFET device, and therefore how to further increase the voltage withstanding of the MOSFET device is a problem to be solved at present.

SUMMERY OF THE UTILITY MODEL

In order to solve the above technical problem, the present invention provides a MOSFET device to improve the withstand voltage of the MOSFET device. The utility model also provides a chip comprising the MOSFET device.

To achieve the above object, a first aspect of the present invention provides a MOSFET device comprising:

a semiconductor substrate;

the field limiting rings are arranged at intervals, wherein the innermost field limiting ring defines an active region; each field limiting ring comprises a groove formed on the upper surface of the semiconductor substrate and first doping regions extending from the side parts and the bottom parts of the groove into the semiconductor substrate, and the first doping regions of the adjacent field limiting rings are contacted or overlapped;

the junction terminal extension structure surrounds the outer sides of the field limiting rings and comprises a second doping region, the second doping region extends inwards from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate, and the second doping region is in contact with or overlapped with the first doping region in the outermost field limiting ring;

in two adjacent field limiting rings, the depth of the first doped region of the inner field limiting ring is greater than or equal to that of the first doped region of the outer field limiting ring; in the field limiting rings, the depths of the first doped regions of at least two field limiting rings are different, and the depth of the first doped region in the outermost field limiting ring is greater than or equal to the depth of the second doped region.

Further, in two adjacent trenches, the depth of the trench close to the active region is greater than or equal to the depth of the trench far away from the active region; at least two of the plurality of grooves have different depths.

Further, the depth of the plurality of trenches is from deep to shallow as the plurality of trenches are closer to the active region.

Further, the depths of the trenches are arranged in an arithmetic progression with the distance between the trenches and the active region from near to far.

Further, the width of the plurality of trenches is from wide to narrow as the plurality of trenches are closer to the active region.

Further, as the distance between the plurality of trenches and the active region is from near to far, the widths of the plurality of trenches are arranged in an arithmetic progression.

Further, the distance between the center positions of every two adjacent grooves is a fixed preset value.

Further, the projections of the plurality of grooves on the upper surface of the semiconductor substrate are concentrically arranged.

Further, the second doping region comprises an ion implantation region and an ion diffusion region, wherein the ion diffusion region surrounds the ion implantation region; the width of the ion implantation area is larger than that of the groove in the field limiting ring at the outermost side.

A second aspect of the utility model provides a chip comprising the MOSFET device of the first aspect.

The MOSFET device provided by the utility model has the following technical effects:

by arranging the junction termination extension-field limiting ring composite structure in the termination region of the MOSFET device, the depth of the doped region tends to be reduced as a whole as the distance between the doped region (including the first doped region in the field limiting ring and the second doped region in the junction termination extension structure) and the active region in the composite structure is increased. Therefore, compared with the prior art, the curvature radius of an electric field formed by the composite structure is larger, so that the voltage resistance of the MOSFET device is improved.

The chip provided by the utility model also has good voltage resistance performance due to the fact that the chip comprises the MOSFET device.

Drawings

Fig. 1 is a schematic structural diagram of a MOSFET device according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a plurality of trenches in a MOSFET device according to an embodiment of the present invention;

fig. 3 to fig. 12 are schematic structural diagrams of a MOSFET device provided in an embodiment of the present invention in a partial step of a manufacturing process.

Detailed Description

So that the manner in which the features and aspects of the embodiments of the present invention can be understood in detail, a more particular description of the embodiments of the utility model, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures may be shown to simplify the drawing.

The terms "first," "second," and the like in the description and in the claims, and in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

In the prior art, a process for forming a field limiting ring includes forming an oxide layer mask on a surface of a semiconductor substrate, and then performing ion implantation and high-temperature junction pushing, thereby forming a plurality of doping regions arranged in a concentric ring in the semiconductor substrate. The oxide layer mask is also used for protecting the semiconductor substrate from being damaged in the ion implantation process. The curvature radius of the junction formed after the junction is pushed by the process is smaller, so that the voltage resistance of the MOSFET device is lower.

Based on this, the present invention provides a solution to increase the withstand voltage of MOSFET devices.

Fig. 1 is a schematic structural diagram of a MOSFET device according to an embodiment of the present invention, and fig. 1 is a partial cross-sectional view, which only shows the structure of a termination region, and is exemplarily illustrated with an active region located on the right side (not shown) of fig. 1. As shown in fig. 1, the MOSFET device provided in this embodiment includes: the semiconductor device includes a semiconductor substrate, a plurality of field limiting rings arranged at intervals, and a Junction Termination Extension (JTE) structure surrounding the outer sides of the plurality of field limiting rings. An innermost field limiting ring of the plurality of field limiting rings defines an active region. Each field limiting ring comprises a groove 30 formed on the upper surface of the semiconductor substrate and a first doping region 40 extending from the side part and the bottom part of the groove 30 into the semiconductor substrate, and the first doping regions 40 of the adjacent field limiting rings are contacted or overlapped; the junction termination extension structure includes a second doped region 50, the second doped region 50 extending inwardly of the semiconductor substrate from the upper surface thereof, the second doped region 50 contacting or overlapping the first doped region 40 in an adjacent field limiting ring.

In two adjacent field limiting rings, the depth of the first doped region 40 of the inner field limiting ring is greater than or equal to the depth of the first doped region 40 of the outer field limiting ring; in the plurality of field limiting rings, the depths of the first doped regions 40 of at least two field limiting rings are different, and the depth of the first doped region 40 in the outermost field limiting ring is greater than or equal to the depth of the second doped region 50.

Specifically, the semiconductor substrate includes an active region, which refers to a region where a function of a MOSFET device is formed, and a termination region surrounding the active region. A plurality of grooves 30 are formed on the upper surface of the terminal area, and the bottoms of the grooves 30 are positioned in the semiconductor substrate; the first doped regions 40 extend from the bottom and the side of the trench 30 to the periphery, that is, the first doped regions 40 extend longitudinally from the bottom of the trench 30 to the lower surface of the termination region and laterally from the side of the trench 30 to the surrounding region, and finally the adjacent first doped regions 40 are contacted and even overlapped, so that the first doped regions 40 of all the field limiting rings form the whole ion doped region in the semiconductor substrate. In other words, the orthographic projection of the first doped region 40 on the upper surface of the termination region completely covers the orthographic projection of the trench 30 on the upper surface of the termination region, and the orthographic projections of adjacent first doped regions 40 on the upper surface of the termination region contact or overlap.

The junction termination extension structure is located in the termination region and is further away from the active region relative to the plurality of field limiting rings. The junction termination extension structure includes a second doped region 50 having an orthographic projection of the second doped region 50 at the upper surface of the termination region contacting or overlapping an orthographic projection of the adjacent first doped region 40 at the upper surface of the termination region. In this way, the second doped region 50 and all of the first doped regions 40 together form the entire doped region within the semiconductor substrate.

In this embodiment, the depth of the doped region refers to the distance between the bottom of the doped region and the upper surface of the semiconductor substrate along the thickness direction of the semiconductor substrate. The depth of the first doped region 40 in the outermost field limiting ring is greater than or equal to the depth of the second doped region 50, which means that the distance from the bottom of the first doped region 40 to the upper surface of the semiconductor substrate is greater than or equal to the distance from the bottom of the second doped region 50 to the upper surface of the semiconductor substrate. In two adjacent field limiting rings, the depth of the first doped region 40 of the inner field limiting ring is greater than or equal to the depth of the first doped region 40 of the outer field limiting ring, which means that the distance from the bottom of the inner first doped region 40 to the upper surface of the semiconductor substrate is greater than or equal to the distance from the bottom of the outer first doped region 40 to the upper surface of the semiconductor substrate.

Compared with the prior art, in the MOSFET device provided by the embodiment, the junction terminal extension-field limiting ring composite structure is arranged in the terminal region, and the overall depth of the first doped region 40 and the second doped region 50 is reduced along with the increase of the distance from the active region, so that the curvature radius of a formed electric field is larger, and the voltage resistance of the MOSFET device is improved; in addition, the electric field curvature radius is increased, so that the electric field density is reduced, and the leakage problem of the MOSFET device is improved.

Further, compared with the prior art that an oxide layer serving as a mask layer and a protective layer is formed on the surface of the semiconductor substrate before ion implantation, in the embodiment, the first doped region 40 is formed through the trench 30, and an oxide layer does not need to be grown on the surface of the semiconductor substrate in the process of manufacturing the field limiting ring, ions can be directly implanted into the trench 30 and high-temperature junction is pushed to form the first doped region 40, so that the thermal budget is reduced, the diffusion of a transition region is reduced, and the withstand voltage of the power semiconductor device is further improved.

In this embodiment, since the first doped region 40 is obtained by implanting ions into the semiconductor substrate through the trench 30 and performing diffusion, in the specific implementation process, the depth of the first doped region 40 can be controlled by controlling the depth of the trench 30 in addition to controlling the process conditions such as the implantation depth, the junction push temperature, the junction push time, and the like. For example, in fig. 1, in two adjacent trenches 30, the depth of the trench 30 close to the active region is greater than or equal to the depth of the trench 30 far from the active region; of the plurality of trenches 30, at least two of the plurality of trenches 30 have different depths, i.e., the innermost (closest to the active area) trench 30 of the plurality of trenches 30 has a greater depth than the outermost (i.e., furthest from the active area) trench 30.

Fig. 2 is a schematic diagram of a plurality of trenches in a MOSFET device according to an embodiment of the present invention, in which the shaded portions are portions of a semiconductor substrate that are not etched, and a space between two shaded portions is a trench. The illustration is made with the active region (not shown) on the right side of fig. 2.

Referring to fig. 1 in conjunction with fig. 2, the plurality of trenches 30 are respectively denoted as a 1 st trench, a 2 nd trench, …, an i-1 th trench, and an i-th trench in order from the near to the far distance between the trenches 30 and the active region. The depth of the 1 st groove is recorded as D₁The depth of the 2 nd trench is recorded as D₂… … the depth of the i-1 st groove is recorded as D_i-1The depth of the ith groove is recorded as D_i. Wherein D is_i≤D_i-1And D_i＜D₁，i≥2。

In the MOSFET device provided in this embodiment, as the distance between the trench 30 and the active region is from near to far, the depth of the plurality of trenches 30 tends to decrease as a whole, and correspondingly, the depth of the first doped region 40 in the semiconductor substrate also tends to decrease as a whole; on the basis, the depth of the second doping region 50 does not exceed that of the adjacent first doping region 40, so that compared with the existing field limiting ring, the electric field curvature radius formed by the junction terminal extension-field limiting ring composite structure is larger, and the voltage resistance of the MOSFET device is improved. And because the radius of curvature of the electric field is larger, the electric field density is smaller, and therefore the problem of electric leakage of the MOSFET device is also improved.

The respective structures of the MOSFET device are explained in detail below:

in this embodiment, an epitaxial wafer or a single wafer can be used as the semiconductor substrate. The single crystal wafer can be a silicon single crystal wafer, a silicon carbide single crystal wafer and the like which are commonly used for preparing MOSFET devices. The epitaxial wafer may be commercially available, or may be obtained by depositing the epitaxial layer 20 on the surface of the substrate 10 by a process such as CVD (Chemical Vapor Deposition) or PVD (Physical Vapor Deposition).

In the case of an epitaxial wafer as a semiconductor substrate, the semiconductor substrate includes a substrate 10 and an epitaxial layer 20 located on an upper surface of the substrate 10, wherein the upper surface of the semiconductor substrate refers to a surface of the epitaxial layer 20 on a side far from the substrate 10, that is, an upper surface of the epitaxial layer 20; the bottom of the semiconductor base refers to the position where the substrate 10 is located; the lower surface of the semiconductor substrate refers to the lower surface of the substrate 10.

It should be understood that for a semiconductor substrate obtained by depositing epitaxial layer 20 on the surface of substrate 10, the depth of trench 30 is less than the thickness of epitaxial layer 20, and the bottom of trench 30 is located within epitaxial layer 20. The depth of the first doped region 40 does not exceed the thickness of the epitaxial layer 20, i.e., the bottom of the first doped region 40 is at a distance from the upper surface of the substrate 10.

Optionally, each field limiting ring comprises a trench 30 formed in the upper surface of the termination region of the semiconductor substrate, and a first doped region 40 extending from the bottom of the trench 30 to the lower surface of the semiconductor substrate, the first doped region 40 extending from the side of the trench 30 to the periphery.

Before ions are injected into the groove 30 to form the first doping region 40, an oxide layer does not need to be grown on the upper surface of the semiconductor substrate, so that the thermal budget of the MOSFET device in the preparation process is reduced, the diffusion of a transition region is reduced, and the withstand voltage of the MOSFET device is further improved.

In a MOSFET device, the field limiting rings define an active region. In the present embodiment, a plurality of trenches 30 are disposed around the active region, and more specifically, the innermost trench 30 defines the active region. In some embodiments, the projected shape of the plurality of trenches 30 on the upper surface of the semiconductor substrate matches the projected shape of the active region on the upper surface of the semiconductor substrate. For example, the projection of the active region on the upper surface of the semiconductor substrate is circular, and the projection of the trench 30 on the upper surface of the semiconductor substrate is circular; the projection of the active region on the upper surface of the semiconductor substrate is polygonal (e.g., square), the projection of the trench 30 on the upper surface of the semiconductor substrate is polygonal ring (e.g., square ring), and the corners of the polygon are chamfers. Of course, the trench 30 may also have other shapes, and accordingly, the active region may also have other adaptive shapes, which is not limited in this embodiment. In other embodiments, the projection shape of the plurality of trenches 30 on the upper surface of the semiconductor substrate does not absolutely match the shape of the active region, such as the projection of the trenches 30 on the upper surface of the semiconductor substrate is a circle and the projection of the active region on the upper surface of the semiconductor substrate is a square ring.

Optionally, the plurality of trenches 30 are concentric trenches, the plurality of concentric trenches surrounding the active region; in other words, the plurality of trenches 30 are concentrically arranged in projection on the upper surface of the semiconductor substrate.

For example, according to the order from the near to the far of the trench 30 from the active region, the plurality of trenches are the 1 st trench 31, the 2 nd trench 32, the 3 rd trench 33 and the 4 th trench 34 in sequence, the 1 st trench 31 defines the active region, the 2 nd trench 32 surrounds the 1 st trench 31, the 3 rd trench 33 surrounds the 2 nd trench 32, the 4 th trench 34 surrounds the 3 rd trench 33, and the 1 st trench 31, the 2 nd trench 32, the 3 rd trench 33 and the 4 th trench 34 overlap in the projection center of the upper surface of the semiconductor substrate.

Correspondingly, according to the sequence from the near to the far of the first doping region 40 from the active region, the plurality of first doping regions 40 are the 1 st first doping region 41, the 2 nd first doping region 42, the 3 rd first doping region 43 and the 4 th first doping region 44 in sequence; the 1 st first doping region 41, the 2 nd first doping region 42, the 3 rd first doping region 43 and the 4 th first doping region 44 are overlapped in the center of the projection of the upper surface of the semiconductor substrate.

Optionally, the depth of the plurality of trenches 30 decreases as the plurality of trenches 30 are closer to the active region, i.e., D₁＞D₂……＞D_i-1＞D_i. Such as depth D of the 1 st trench 30₁Greater than depth D of the 2 nd trench 32₂Depth D of 2 nd groove 32₂Greater than depth D of the 3 rd trench 33₃Depth D of the 3 rd groove 33₃Greater than depth D of the 4 th trench 34₄. Further, the depths of the trenches 30 are arranged in an arithmetic progression from near to far, for example, the depth D of the 1 st trench 31₁Is 4 microns, and the depth D of the 2 nd trench 32₂3 μm, depth D of the 3 rd trench 33₃2 microns, depth D of the 4 th trench 34₄Is 1 micron.

Accordingly, as the distance between the trenches 30 and the active region decreases from near to far, the depth of the doped regions 40 in the semiconductor substrate decreases, and the trenches are further arranged in an arithmetic progression. For example, the depth of the 1 st first doping region 41 in the semiconductor substrate is 5 micrometers, the depth of the 2 nd first doping region 42 in the semiconductor substrate is 4 micrometers, the depth of the 3 rd first doping region 43 in the semiconductor substrate is 3 micrometers, and the depth of the 4 th first doping region 44 in the semiconductor substrate is 2 micrometers. Thus, the electric field curve (such as the wavy line in fig. 1) formed by the plurality of field limiting rings changes smoothly, and the withstand voltage of the MOSFET device is further improved. And because the electric field curve changes smoothly, the electric field line density is reduced, and the electric leakage is reduced to a certain extent.

Alternatively, the width of the plurality of trenches 30 is wide to narrow as the plurality of trenches 30 are closer to the device region. Specifically, the width of the 1 st trench 30 is denoted as W₁The width of the 2 nd trench 30 is denoted as W₂… … the width of the i-1 st groove 30 is denoted as W_i-1The width of the ith groove 30 is denoted as W_iWherein W is₁＞W₂……＞W_i-1＞W_i. Thus, the curvature radius of the electric field formed by the field limiting rings can be further increased, the withstand voltage of the power semiconductor device is improved, and the electric leakage can be reduced.

Optionally, as the distance between the plurality of trenches 30 and the active region is from near to far, the widths of the plurality of trenches 30 are arranged in an arithmetic progression; for example, the width W of the 1 st trench 31₁Is 5.5 μm, and the width W of the 2 nd trench 32₂Is 5 μm, and the width W of the 3 rd trench 33₃Is 4.5 μm, and the width W of the 4 th trench 34₄And was 4 μm. Therefore, the electric field curve (such as the wavy line in fig. 1) formed by the field limiting rings changes more gradually, the curvature radius is further increased, the density of the electric field lines is further reduced, the withstand voltage is further improved, and the electric leakage is reduced.

Alternatively, the distance between the center positions of every two adjacent grooves 30 is a fixed preset value.

Referring to fig. 2, the plurality of trenches are a 1 st trench, a 2 nd trench, …, an i-1 st trench, and an i-th trench, respectively, in order of the distance from the trench to the element region from near to far. In this case, the 1 st groove has a center position x₁The reserved width of the 1 st trench (the width between the 1 st trench and the 2 nd trench) is w₁(ii) a The center position of the 2 nd groove is x₂The reserved width of the 2 nd trench is w₂(ii) a …, respectively; the central position of the (i-1) th groove is x_i-1The reserved width of the i-1 th groove is w_i-1(ii) a The central position of the ith groove is x_iThe reserved width of the ith groove is w_i。

In case of applying a Lateral Variation of Doping (VLD), the above fixed preset values satisfy:

where a is the distance between the center positions of every two adjacent grooves, x₁Is the central position of the 1 st trench, x_nIs the central position of the nth groove, and n is less than or equal to i; χ is the characteristic diffusion length; d is the diffusion coefficient of the impurity, and t is the high-temperature junction pushing time.

Optionally, the fixed preset value further satisfies:

wherein a is the distance between the center positions of every two adjacent grooves, W_iIs the width of the ith trench, C₀Maximum impurity concentration, x, of VLD_iIs the central position of the ith groove, C (x)_i) As a function of the impurity concentration profile of VLD.

By adopting the technical scheme, any doping concentration distribution of VLD can be realized.

The second doped region 50 of the junction termination extension structure extends from the upper surface of the semiconductor substrate into the semiconductor substrate and contacts or overlaps with the adjacent first doped region 40, so that the electric field of the junction termination extension structure and the electric field of the field limiting ring form a continuous electric field; the depth of the second doping region 50 is less than or equal to the depth of the first doping region 40 of the adjacent field limiting ring, so that the curvature radius of an electric field is increased, and the withstand voltage of the MOSFET device is improved.

In this embodiment, the second doped region 50 of the junction termination extension structure can be obtained by implanting ions and annealing. The second doped region 50 forming the junction termination extension structure is implanted with the same type of ions as the first doped region 40 forming the field limiting ring.

The relationship between the ion implantation dose concentration of the second doped region 50 of the junction termination extension structure and the voltage resistance curve of the MOSFET device is as follows: with the increase of the implantation dose concentration, the withstand voltage rises first and then falls. Generally, the higher the withstand voltage of the MOSFET device, the higher the required implantation dose; in the specific implementation process, the implantation dosage can be reasonably determined according to the voltage withstanding requirement of the MOSFET device.

With further reference to fig. 1, the second doped region 50 includes an ion implanted region and an ion diffusion region, wherein the ion implanted region refers to a doped region formed during an ion implantation process; the ion diffusion region refers to a doped region formed by further diffusion of ions into the semiconductor substrate during annealing. It will be appreciated that the ion diffusion region surrounds the ion implantation region. In this embodiment, the width of the ion implantation region is greater than the width of the trench 30 in the outermost field limiting ring. In a specific implementation, the above structure can be achieved by controlling the ion implantation window during the process of forming the second doping region 50, for example, the ion implantation window width is larger than the width of the adjacent trench 30. Through the structure, the electric field lines of the junction terminal extension-field limiting ring composite structure far away from the end part of the active area are more gentle, so that the voltage resistance of the MOSFET is favorably improved, the electric field line density of the junction of the second doping area 50 of the junction terminal extension structure and the adjacent first doping area 40 is reduced, and the electric leakage problem of the MOSFET device is improved.

The method for manufacturing the MOSFET device will be described below by taking an epitaxial wafer as a semiconductor substrate as an example.

As shown in fig. 3, the semiconductor substrate includes a substrate 10 and an epitaxial layer 20 on a surface of the substrate 10.

As shown in fig. 4, a mask 70 is formed on the upper surface of the epitaxial layer 20, and specifically, a photoresist may be first coated on the upper surface of the semiconductor substrate, and then the photoresist may be subjected to a patterning process to obtain the mask 70. Wherein fig. 4 is a longitudinal sectional view of this step and fig. 5 is a top view of this step. The areas of the upper surface of epitaxial layer 20 not covered by mask 70 are shown as areas where trenches 30 are subsequently formed.

As shown in fig. 6, a patterning process is performed using a mask as shown in fig. 5, and the epitaxial layer 20 not covered by the mask 70 is etched to form a plurality of trenches 30. Further, the deeper the depth of the trench 30, the wider the width of the trench 30, the closer to the active region (taking the active region on the right side in fig. 4 and 6 as an example). The wider the trench 30, the faster the etch rate due to the loading effect, so the above-described topography can be obtained by one-step etching by controlling the etch process or the like. Of course, it is also possible to etch several times to obtain the desired distribution of the trenches 30 according to actual requirements.

As shown in fig. 7, under the protection of the mask 70, the epitaxial layer 20 is ion implanted through the trench 30, then the mask 70 is removed, and then the junction is pushed by high temperature oxidation, thereby forming the doped region 40. The wave lines in fig. 7 represent the electric field.

With further reference to fig. 7, the trench 30 is further filled with an insulating layer 60, which may be an oxide layer formed during a high temperature oxidation push junction process, the oxide layer being formed on the surface of the epitaxial layer 20 and in the trench 30. Since the oxidation rate in the trenches 30 is greater than the oxidation rate of the surface of the epitaxial layer 20, an oxide layer having a substantially flat surface can be formed. Of course, the insulating layer 60 may be formed by other deposition processes, and is not particularly limited.

In the above steps, before ion implantation, an oxide layer is not required to be deposited on the epitaxial layer 20 for protection, but ions are directly implanted into the trench 30, so that the thermal budget is reduced, and the process cycle is shortened. And because the thermal budget is reduced, the diffusion of the transition region is reduced, and the withstand voltage of the power semiconductor device is further improved. In general, the doping concentration of the substrate 10 in the power semiconductor device is higher than that of the epitaxial layer 20, so that ions in the substrate 10 diffuse into the epitaxial layer 20, i.e., the transition region, under the influence of high temperature.

From another perspective, in order to obtain the same withstand voltage, the present invention can suitably reduce the thickness of the semiconductor substrate, and particularly, the thickness of the epitaxial layer 20, so that Rdson (resistance) is reduced. In addition, since the thickness of the epitaxial layer 20 and the semiconductor substrate is reduced, it is also advantageous to miniaturize the power semiconductor device.

As shown in fig. 8, a mask 70 is formed on the insulating layer 60, and specifically, a photoresist may be first coated on the upper surface of the insulating layer 60, and then the photoresist may be subjected to a patterning process, resulting in the mask 70. Wherein fig. 8 is a longitudinal sectional view of this step, and fig. 9 is a top view of this step. The areas of the top surface of the insulating layer 60 not covered by the mask 70 in fig. 8 are implantation windows for the subsequent formation of junction termination extension structures. During the process of etching the insulating layer 60 to form the implantation window, a certain thickness of the insulating layer 60 may be remained, for example, a thinner insulating layer 60 is remained on the surface of the epitaxial layer 20 in a region corresponding to the implantation window to protect the epitaxial layer 20 during the subsequent ion implantation process. It is of course also possible to etch the insulating layer 60 corresponding to the implantation window completely, resulting in the structure shown in fig. 10. Fig. 11 is used to illustrate the relative relationship of the implantation window of the junction termination extension structure to the trench 30 of the field limiting ring, as shown in fig. 11, the implantation window having a width greater than the width of the adjacent trench 30.

And performing ion implantation through the ion implantation window and annealing to form a second doped region 50 of the junction terminal extension structure shown in fig. 12, wherein the doping type of the second doped region 50 is the same as that of the first doped region 50, and an orthographic projection of the second doped region 50 on the upper surface of the terminal region is in contact with or overlaps with an orthographic projection of the adjacent first doped region 40 on the upper surface of the terminal region. In this way, the second doped region 50 and all of the first doped regions 40 together form the entire doped region within the semiconductor substrate. The depth of the second doped region 50 is less than or equal to the depth of the first doped region 40 of the outermost field limiting ring. The wavy lines in fig. 12 represent the electric field.

A second aspect of the utility model provides a chip comprising the MOSFET device of the previous embodiments.

In the description of the present invention, the terms "upper", "lower", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present invention but do not require that the present invention must be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

The particular features, structures, materials, or characteristics described in this disclosure may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. A MOSFET device, comprising:

a semiconductor substrate;

2. The MOSFET device of claim 1, wherein of two adjacent trenches, a depth of the trench closer to the active region is greater than or equal to a depth of the trench farther from the active region; at least two of the plurality of grooves have different depths.

3. The MOSFET device of claim 2, wherein the plurality of trenches have a depth from deep to shallow as the plurality of trenches are located from close to far from the active region.

4. The MOSFET device of claim 3, wherein the plurality of trenches are arranged in an arithmetic progression of depths as the plurality of trenches are spaced from the active region from near to far.

5. The MOSFET device of any of claims 1-4, wherein the plurality of trenches have a width that ranges from wide to narrow as the plurality of trenches are closer to the active region.

6. The MOSFET device of claim 5, wherein the plurality of trenches have widths arranged in an arithmetic progression as the plurality of trenches are spaced from the active region from a near distance to a far distance.

7. The MOSFET device of claim 5, wherein the distance between the center positions of each two adjacent trenches is a fixed preset value.

8. The MOSFET device of any one of claims 1-4, wherein a projection of the plurality of trenches onto the upper surface of the semiconductor substrate is concentrically arranged.

9. The MOSFET device of any of claims 1-4, wherein the second doped region comprises an ion implanted region and an ion diffusion region, wherein the ion diffusion region surrounds the ion implanted region; the width of the ion implantation area is larger than that of the groove in the field limiting ring at the outermost side.

10. A chip comprising a MOSFET device according to any of claims 1-9.