CN209592051U

CN209592051U - A kind of p-type high-efficiency battery of passivation on double surfaces contact

Info

Publication number: CN209592051U
Application number: CN201920755594.5U
Authority: CN
Inventors: 王涛; 余波; 杨蕾; 张鹏
Original assignee: Tongwei Solar Chengdu Co Ltd; Tongwei Solar Anhui Co Ltd
Current assignee: Tongwei Solar Chengdu Co Ltd; Tongwei Solar Anhui Co Ltd; Tongwei Solar Hefei Co Ltd
Priority date: 2019-05-24
Filing date: 2019-05-24
Publication date: 2019-11-05
Anticipated expiration: 2029-05-24

Abstract

The utility model discloses a kind of p-type high-efficiency batteries of passivation on double surfaces contact, including p type single crystal silicon, the p type single crystal silicon front is provided with N-type emitter, the N-type emitter is provided with the ultra-thin silicon oxide layer in front far from p type single crystal silicon, N-type polycrystalline silicon layer is provided with above the ultra-thin silicon oxide layer in front, and the ultra-thin conplane two sides of silicon oxide layer in front are provided with oxide layer；The p type single crystal silicon back side is provided with the ultra-thin silicon oxide layer in the back side, and the ultra-thin silicon oxide layer in the back side is provided with p-type polysilicon layer far from p type single crystal silicon side.The utility model utilizes tunnel oxidation layer to be passivated contact structures in the tow sides of battery, has good surface passivation effect, silicon face is passivated immediately below front metal grid line and below the Al-BSF of the back side, metal is avoided to contact with the direct of silicon substrate, reduce surface recombination, promotes battery conversion efficiency.

Description

A kind of p-type high-efficiency battery of passivation on double surfaces contact

Technical field

The utility model relates to battery passivation technical field, specially a kind of p-type high-efficiency battery of passivation on double surfaces contact.

Background technique

The efficiency of system crystal silicon solar batteries rises quickly in recent years, and demand of the market to high-efficiency battery and expectation are increasingly Height, various new technologies, new construction are employed in nearest high-efficiency battery production, such as heterojunction structure (HIT) and tunnel oxygen Change layer passivation contact (TOPCon) structure etc..

In every loss of solar battery, the loss of surface recombination occupies sizable specific gravity, and metal and silicon The recombination losses of base contact position are also difficult to ignore.

In traditional PERC battery, contact of the front gate line with emitter is inevitable, although selective hair can be used Emitter-base bandgap grading (SE) technology reduces surface recombination, but the disadvantage is that: contact of the metal with semiconductor still brings a large amount of compound, makes to open a way Voltage Voc and short circuit current Isc incur loss.

Although the oxidation aluminium coat at the back side plays the role of passivated surface, but itself has insulating properties, need using Laser, which is slotted, can just be such that back side Al-BSF contacts with silicon to collect carrier, and the size of laser aperture opening ratio influences whether table The compound degree in face, but the disadvantage is that: the fill factor FF that will lead to battery is relatively low, there is certain limitation, limits PERC battery The further promotion of efficiency.

The above-mentioned mode using selective emitter (SE) and laser slotting goes to reduce surface recombination reduction, and effect is inadequate Good, defect is more obvious, so a kind of battery of novel passivation on double surfaces contact is needed to go to reduce surface recombination.

Utility model content

The purpose of this utility model is to provide a kind of p-type high-efficiency batteries of passivation on double surfaces contact, to solve above-mentioned background The problem of being proposed in technology.

To achieve the above object, the utility model provides the following technical solutions:

A kind of p-type high-efficiency battery of passivation on double surfaces contact, including p type single crystal silicon, the p type single crystal silicon front are provided with N Type emitter, the N-type emitter are provided with the ultra-thin silicon oxide layer in front, the ultra-thin silica in front far from p type single crystal silicon Layer top is provided with N-type polycrystalline silicon layer, and the ultra-thin conplane two sides of silicon oxide layer in front are provided with oxide layer, the N-type Polysilicon layer and oxide layer are provided with SiNx antireflection layer, and Ag grid line is provided on N-type polycrystalline silicon layer, the Ag grid line It is connected on N-type polycrystalline silicon layer across SiNx antireflection layer；

The p type single crystal silicon back side is provided with the ultra-thin silicon oxide layer in the back side, and the ultra-thin silicon oxide layer in the back side is far from p-type list Crystal silicon side is provided with p-type polysilicon layer, is provided with Al back surface field below the p-type polysilicon layer.

Compared with prior art, the utility model has the beneficial effects that

Tunnel oxidation layer passivation contact (TOPCon) structure of the utility model not only has good chemical passivation effect, It is formed using the polysilicon that the oxide layer of one layer of ultra-thin permission electron hole tunnelling is adulterated with one layer of N-type or p-type, it is different Doping type has different carrier selectivity, while avoiding metal electrode and contacting with the direct of silicon substrate, reduces multiple It closes, improves battery efficiency.

The utility model utilizes tunnel oxidation layer to be passivated contact structures in the tow sides of battery, has good surface Passivation effect is passivated silicon face immediately below the front metal grid line and below the Al-BSF of the back side, avoid metal with The direct contact of silicon substrate reduces surface recombination, promotes battery conversion efficiency.

Detailed description of the invention

Fig. 1 is the overall structure diagram of the utility model；

Fig. 2 is the preparation method flow diagram of the utility model.

In figure: 1P type monocrystalline silicon, the ultra-thin silicon oxide layer in 2 fronts, 3N type polysilicon layer, 4N type emitter, 5 oxide layers, 6 back The ultra-thin silicon oxide layer in face, 7P type polysilicon layer, 8SiNx antireflection layer, 9Ag grid line, 10Al back surface field.

Specific embodiment

The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work Every other embodiment obtained, fall within the protection scope of the utility model.

The utility model provides a kind of technical solution referring to FIG. 1-2:

A kind of p-type high-efficiency battery of passivation on double surfaces contact, including p type single crystal silicon 1,1 front of p type single crystal silicon are provided with N-type Emitter 4, N-type emitter 4 are provided with the ultra-thin silicon oxide layer 2 in front, ultra-thin 2 top of silicon oxide layer in front far from p type single crystal silicon 1 It is provided with N-type polycrystalline silicon layer 3, the ultra-thin silicon oxide layer 2 in front and N-type polycrystalline silicon layer 3 are in same vertical plane, and N-type polycrystalline Silicon layer 3 covers the ultra-thin silicon oxide layer 2 in front completely, forms extraordinary tunnel oxidation layer passivation contact structures, the ultra-thin oxygen in front The conplane two sides of SiClx layer 2 are provided with oxide layer 5, aoxidize to be formed by subsequent anneal, and oxide layer 5 is silicon oxide layer, with Ultra-thin 2 thickness of silicon oxide layer in front is identical, and SiNx antireflection layer 8, and N-type are provided with above N-type polycrystalline silicon layer 3 and oxide layer 5 Ag grid line 9 is provided on polysilicon layer 3, Ag grid line 9 passes through SiNx antireflection layer 8 and is connected on N-type polycrystalline silicon layer 3.

1 back side of p type single crystal silicon is provided with the ultra-thin silicon oxide layer 6 in the back side, and the ultra-thin silicon oxide layer 6 in the back side is far from p type single crystal silicon 1 Side is provided with p-type polysilicon layer 7, forms the tunnel oxidation layer passivation contact structures at the back side, is arranged below p-type polysilicon layer 7 There is Al back surface field 10.

A kind of preparation method of the p-type high-efficiency battery of passivation on double surfaces contact, comprising the following steps: S1, cleaning and texturing: by P Type monocrystalline silicon 1 is once purged to prepare special suede structure, and suede structure includes pyramid and reverse pyramid, controls p-type list 1 surface reflectivity of crystal silicon is in 9-11%；

S2, the preparation of front polysilicon: in the 1 front one layer of ultra-thin oxidation in front of preparation of p type single crystal silicon for having prepared flannelette Silicon layer 2 and one layer of N-type polycrystalline silicon layer 3, the thickness control of the ultra-thin silicon oxide layer 2 in front use hot HNO in 1-2nm₃Solution oxygen Change or the preparation of dry oxidation method, the thickness control of N-type polycrystalline silicon layer 3 use PECVD to prepare in 30-50nm；

S3, it prepares exposure mask: preparing one layer of exposure mask, the figure and Ag of exposure mask in 3 surface screen printing of N-type polycrystalline silicon layer 9 figure of grid line is consistent；

S4, etching: HNO is used₃With the mixed solution of HF, used HNO₃It is 45%-50%:6%- with HF concentration ratio 8%, front side of silicon wafer is performed etching, the ultra-thin silicon oxide layer 2 in front and N-type polycrystalline silicon layer 3 of unmasked areas is removed, then goes Except exposure mask；

S5, diffusion: High temperature diffusion is carried out in the front of silicon wafer, forms N-type emitter 4；

S6, cleaning: the phosphorosilicate glass diffuseed to form and edge PN junction are removed；

S7, annealing: oxide layer 5 is formed in ultra-thin 2 plane of silicon oxide layer in front of silicon wafer；

S8, the preparation of back side polysilicon layer: the ultra-thin silicon oxide layer 6 in one layer of back side and one layer are prepared at the back side of p type single crystal silicon 1 P-type polysilicon layer 7, the thickness control of the ultra-thin silicon oxide layer 6 in the back side use hot HNO in 1-2nm₃Solution oxide or dry method oxygen The preparation of change method, the thickness control of p-type polysilicon layer 7 use PECVD to prepare in 30-50nm；

Prepared by S9, front SiNx antireflection layer 8: preparing SiNx antireflection layer 8 in front side of silicon wafer with PECVD, control is thick Degree is in 60-90nm, refractive index in 2.08-2.12；

S10, printing: printing Ag grid line 9 on positive N-type polycrystalline silicon layer 3, and figure is consistent with the mask pattern in S3, And Al back surface field 10 is printed on p-type polysilicon layer 7 overleaf.

Embodiment one:

A kind of preparation method of the p-type high-efficiency battery of passivation on double surfaces contact, comprising the following steps:

S1, cleaning and texturing: special suede structure is prepared by p type single crystal silicon 1 is once purged, suede structure includes pyramid And reverse pyramid, 1 surface reflectivity of p type single crystal silicon is controlled 10%；

S2, the preparation of front polysilicon: in the 1 front one layer of ultra-thin oxidation in front of preparation of p type single crystal silicon for having prepared flannelette Silicon layer 2 and one layer of N-type polycrystalline silicon layer 3, the thickness control of the ultra-thin silicon oxide layer 2 in front use dry oxidation legal system in 1nm Standby, the thickness control of N-type polycrystalline silicon layer 3 uses PECVD to prepare in 30nm；

S3, it prepares exposure mask: preparing one layer of exposure mask, the figure and Ag of exposure mask in 3 surface screen printing of N-type polycrystalline silicon layer 9 figure of grid line is consistent, and the ultra-thin silicon oxide layer 2 in front and N-type polycrystalline silicon layer 3 are hidden；

S4, etching: HNO is used₃With the mixed solution of HF, used HNO₃It is 50%:8% with HF concentration ratio, to silicon wafer Front performs etching, and removes the ultra-thin silicon oxide layer 2 in front and N-type polycrystalline silicon layer 3 of unmasked areas, i.e., by the ultra-thin oxidation in front The ultra-thin silicon oxide layer 2 in front and N-type polycrystalline silicon layer 3 of 2 two sides of silicon layer are got rid of, and covering on N-type polycrystalline silicon layer 3 is then removed Film；

S8, the preparation of back side polysilicon layer: the ultra-thin silicon oxide layer 6 in one layer of back side and one layer are prepared at the back side of p type single crystal silicon 1 P-type polysilicon layer 7, the thickness control of the ultra-thin silicon oxide layer 6 in the back side use hot HNO in 1nm₃Solution oxide or dry oxidation Method preparation, the thickness control of p-type polysilicon layer 7 use PECVD to prepare in 30nm；

Prepared by S9, front SiNx antireflection layer 8: preparing SiNx antireflection layer 8 in front side of silicon wafer with PECVD, control is thick Degree is in 60nm, refractive index 2.10；

S10, printing: Ag grid line 9 is printed on positive N-type polycrystalline silicon layer 3, and is printed on p-type polysilicon layer 7 overleaf Brush Al back surface field 10.

While there has been shown and described that the embodiments of the present invention, for the ordinary skill in the art, It is understood that these embodiments can be carried out with a variety of variations in the case where not departing from the principles of the present invention and spirit, repaired Change, replacement and variant, the scope of the utility model is defined by the appended claims and the equivalents thereof.

Claims

1. a kind of p-type high-efficiency battery of passivation on double surfaces contact, including p type single crystal silicon (1), it is characterised in that: the p type single crystal silicon (1) front is provided with N-type emitter (4), and the N-type emitter (4) is provided with the ultra-thin oxidation in front far from p type single crystal silicon (1) Silicon layer (2), the ultra-thin silicon oxide layer in front (2) top is provided with N-type polycrystalline silicon layer (3), and the ultra-thin silicon oxide layer (2) in front Conplane two sides are provided with oxide layer (5), are provided with SiNx anti-reflection above the N-type polycrystalline silicon layer (3) and oxide layer (5) It penetrates layer (8), and is provided with Ag grid line (9) on N-type polycrystalline silicon layer (3), the Ag grid line (9) connects across SiNx antireflection layer (8) It is connected on N-type polycrystalline silicon layer (3)；

P type single crystal silicon (1) back side is provided with the ultra-thin silicon oxide layer in the back side (6), and the ultra-thin silicon oxide layer in the back side (6) is separate P type single crystal silicon (1) side is provided with p-type polysilicon layer (7), is provided with Al back surface field (10) below the p-type polysilicon layer (7).