CN1842045A - A data communication method inside a device - Google Patents

Abstract

The invention discloses a inner data communicating method of device which provides different communicating interface circuit connection between the function unit and the exchanging center unit; when the processor of the function unit doesn't have the standard Ethernet MII interface, it provides the function unit which uses the bus interface type communicating interface circuit to connect with the exchanging center unit; when the processor of the function unit has the standard Ethernet MII interface, it provides the function unit which uses the MII interface type communicating interface circuit to connect with the exchanging center unit; it uses the low pressure differential signal transferring to send and receive the signal between the function unit and the exchanging center unit.

Description

A data communication method inside a device

technical field

The invention relates to the field of Ethernet frame format data communication, in particular to a communication method between various functional units in a rack of complex system equipment.

Background technique

Since the formal adoption of the 10BASE-T standard in 1990, Ethernet technology has been greatly improved due to its openness, simple structure, concise algorithm, good compatibility and smooth upgrade function, and the transmission bandwidth has also been greatly improved over time. The domain of the local area network has achieved a dominant position, and its territory has also expanded to the range of the metropolitan area network and the wide area network. Among them, because the total transmission bandwidth of switched Ethernet products is dozens of times that of a single port, and there is no media contention problem between ports, the overall performance is more prominent in heavy-load applications.

In complex equipment, in order to complete specific tasks, each functional unit needs to work together. In order to work together, there must be a smooth communication channel between the units. According to the existing multi-node communication technology, considering the transmission bandwidth, cost and technical complexity, switched Ethernet 10BASE-T/100BASE-TX is the best choice. This technology not only has a large bandwidth, but also adopts a star topology , good scalability, and can realize communication between any two points without disturbing other units. Therefore, switched Ethernet is widely used in complex communication equipment.

According to the IEEE802.3 specification, between the physical layer and the data link layer of the standard 10BASE-T/100BASE-TX Ethernet system, MII, or Media Independent Interface, is used. On the physical layer, CSMA/CD (Carrier Sense Multiple Access with Collision Detection, carrier sense multi-access with collision detection), this is one of the characteristics of Ethernet technology, using this mechanism, multiple Ethernet sites can share a piece of media, but when designing the internal communication scheme of the device , the standard Ethernet structure 10BASE-T/100BASE-TX has the following problems when used in complex communication equipment:

Problem 1: As an Ethernet switching center unit, each port of the switching center needs to use a pulse transformer and a corresponding matching network circuit. For the layout, we have to settle for the next best thing, and arrange another single board, which increases the complexity of the backplane and increases the overall cost.

Question 2: The Ethernet of each port uses a standard MII interface on the processor side. For some boards with simple functions, because they only use single-chip microcomputers or cheap processors without this interface, they cannot communicate through the Ethernet switching network. In addition, RS485 or RS232 is added for communication, resulting in the coexistence of two or three topological structures such as chain-type 485 communication structure, star-type Ethernet structure or star-type dual-port RAM communication structure in the whole device, which not only increases the complexity of the overall communication The degree and cost, and the communication efficiency is also greatly reduced.

Contents of the invention

The purpose of the present invention is in order to overcome the standard Ethernet technology physical layer configuration requirement too much in the prior art, the interface of physical layer and MAC (media access controller) layer is unfavorable for the shortcoming that is connected with common processor, solves the problem in the prior art There are too many physical layer devices, taking up a lot of space, and there are multiple communication structures in the whole device, so a data communication method inside the device is proposed.

In order to achieve the purpose of the above invention, a data communication method within the device proposed by the present invention includes the following steps:

Step 1. Construct a star structure with the switching center unit as the core between each functional unit and the switching center unit, and carry out two-way communication between the functional units through the switching center unit;

Step 2. According to the difference of the processor type of the functional unit, different communication interface circuit connections are provided between the functional unit and the switching center unit:

When the processor of the functional unit does not have a standard Ethernet MII interface, the functional unit is connected to the switching center unit through a bus interface type communication interface circuit;

When the processor of the functional unit has a standard Ethernet MII interface standard, the functional unit is connected to the switching center unit through the MII interface type communication interface circuit;

Step 3. Send and receive signals between the functional unit and the switching center unit using low-voltage differential signal transmission.

Using the method described in the present invention, each unit exclusively occupies an Ethernet segment during the internal communication of the device, adopts a full-duplex switching mode, and uses LVDS (Low Voltage Differential Signaling, Low Voltage Differential Signaling) for signal transmission and reception, and does not require complicated Modulation and demodulation and analog matching network, standard Ethernet signal, so that no modulation and demodulation and analog matching network are required, the physical layer circuit is simplified, and the processor used by the functional unit can be used regardless of whether it has an Ethernet MII interface. It is connected to the Ethernet switching circuit, thereby simplifying the communication topology of each unit of the whole machine, reducing the complexity of the overall communication software, and reducing the overall cost.

Description of drawings

Figure 1 overall communication topology structure diagram;

Fig. 2 bus interface type communication interface circuit diagram;

Fig. 3 MII interface type communication interface circuit diagram;

Fig. 4 bus interface type data transmission buffer control diagram;

Fig. 5 bus interface type frame data packaging and sending processing diagram;

Fig. 6 bus interface type data reception buffer control diagram;

Fig. 7 bus interface type frame reception processing diagram;

Figure 8 MII interface type communication interface circuit frame transmission processing diagram;

Fig. 9 is a frame receiving and processing diagram of the MII interface type communication interface circuit.

Detailed ways

Figure 1 is the overall communication topology, each functional unit and the Ethernet switching unit form a star network, in which the Ethernet switching unit is the center.

Fig. 2 is a kind of bus interface type communication interface circuit, this circuit model is suitable for that kind of processor does not have the standard MII interface, or the unit that MII interface number is not enough but needs to expand the Ethernet interface, this kind of interface, the processor is for The sending and receiving of Ethernet data frames is accomplished through the read and write access of the bus.

Fig. 3 is the MII interface type communication interface circuit, this circuit model is suitable for the unit with the standard MII interface of that kind of processor. In this interface, the processor sends and receives Ethernet data frames through communication with the internal communication processor.

Referring to accompanying drawing 2, bus interface type data communication circuit is made up of following circuit modules: bus type data receiving and dispatching buffer control module 22, sending clock 23, frame packaging and sending processing module 24, and frame extracting check processing module 25 are made up. The processor writes the data to be sent into the sending buffer of the bus type data transceiver buffer control module 22, then starts sending, then the frame packaging and sending processing module 24 completes the encapsulation of the data, and the encapsulated data passes through 4B/5B successively Conversion and parallel/serial conversion, and finally converted into LVDS signals and sent to the switching center unit. After a frame is sent, the underlying control circuit immediately sends an interrupt to the processor to notify the processor. This interrupt flag is cleared when the processor writes data to any buffer.

The switching center unit first performs LVDS level conversion on the data and converts it into an LVDS signal. After the frame extraction and verification processing module 25 goes through the whole process of frame extraction and CRC verification, the extracted frame signal content is written into the bus type transceiver. The receiving buffer of the buffer control module 22 is for the processor to read at any time. After writing these contents to the receiving buffer, the underlying control circuit immediately sends an interrupt to the processor to notify the processor. This interrupt flag is cleared when the processor reads data from the buffer.

Referring to accompanying drawing 3, MII interface type communication interface circuit is made up of following circuit modules: frame transmission processing module and frame extracting module, because standard MII interface, data packet is sent to MII interface, has been complete data packet (comprising CRC proofreading module) Check code) and frame interval and idle code, the data sent by the processor is converted into LVDS signal after 4B/5B code conversion, parallel/serial conversion and LVDS level conversion, and sent to the switching center unit, while the data sent from the switching center unit For the data, LVDS level conversion/clock data recovery (CDR), serial/parallel conversion, 5B/4B pattern conversion, and data frame boundary processing are performed successively, and the data is sent to the processor. These transformations are the transformation processing of the physical layer, and the CRC check part and the frame data extraction part are completed by the external interface and algorithm of the relevant functions of the processor.

Taking the frame structure of 100BASE-TX as an example, firstly, the specific structure of the bus interface data communication circuit is described in detail as follows:

Bus interface type data transmission buffer control module: referring to accompanying drawing 4, the core of described module is the dual-port RAM circuit 41 of the unequal mouth width of one-way transmission data, and its reading port width is 4, and processor interface side writes The width is subject to the actual bus width of the processor. Bus write mode outside the processor, write the destination address, source address, length/type field, data and filling PAD of the Ethernet data frame into the dual-port RAM, after writing a frame, start sending, controlled by the sending time slot The sub-module 42 generates the read permission signal at an appropriate time, through the "read address, read signal" module 43, combined with the clock, generates the read address of the dual-port RAM, reads the control signal, and reads the data. The 5-frequency division module 44 is used to divide the input 125M clock by 5 to generate a 25M 4-bit parallel port readout clock.

Bus interface type frame data packaging and sending processing module: refer to Figure 5 to generate sub-module 51 from "preamble/start code/end code/idle code", parallel/serial conversion sub-module 52, CRC check code generation sub-module 53 , 4B/5B conversion sub-module 54, parallel/serial conversion circuit sub-module 55, and LVDS level conversion sub-module 56. After the data in the send buffer has been written, the processor sends a "start sending" signal. First, the "preamble/start code/end code/idle code" generation sub-module 51 sends 7 preamble byte codes in the format of 25M frequency 5-BIT width, then sends the start code, and sends it to the parallel/serial conversion The circuit sub-module 55; then, the 4-bit parallel data output by the dual-port RAM 41 is transformed by the parallel/serial conversion sub-module 52 and then divided into two outputs; one road data is still sent to the 4B/5B conversion sub-module in the format of 4-bit width 54; Another road data is sent to CRC check code generation submodule 53 with the format of serial data, is used to generate CRC check code; While reading the content of dual-port RAM 41, start CRC check code generation submodule 53, generate 32-bit CRC check codes, and after the content of dual-port RAM 41 has been read, the CRC check codes are sent to the 4B/5B conversion submodule 54; The "start code/end code/idle code" generation sub-module 51 sends the frame end code and idle code, thereby completing the encapsulation process of a complete data frame. If there is no new data to send, the idle code has been sent. The encapsulated frame is carried out 4B/5B conversion by 4B/5B conversion sub-module 54, and the 5BIT width data after conversion is carried out parallel/serial conversion by parallel/serial conversion circuit sub-module 55 again, and finally serial data is carried out LVDS conversion, with 125M clock output to the backplane.

The used 4B/5B coding of the present invention except idle code, what all the other codings adopted is 802.3-2002, the standard subset of clause 24 (below the same), as shown in table 1:

Table 1 5B code 43210 name MII interface (TXD3: 0/RXD3: 0) 3210 explain

11110 0 0000 Data 0 01001 1 0001 Data 1 10100 2 0010 Data 2 10101 3 0011 Data 3 01010 4 0100 Data 4 01011 5 0101 Data 5 01110 6 0110 Data 6 01111 7 0111 Data 7 10010 8 1000 Data 8 10011 9 1001 Data 9 10110 A 1010 Data A 10111 B 1011 Data B 11010 C 1100 Data C 11011 D 1101 Data D 11100 E 1110 Data E 11101 F 1111 Data F 10000 I1 undefined Idle Code Part 1 10000 I2 undefined Idle Code Part 2 11000 J 0101 Preamble part 1 10001 K 0101 Preamble part 2 01011 SFD1 0101 Start Code Part 1 11011 SFD2 1101 Start Code Part 2 01101 T undefined Frame end code part 1 00111 R undefined Frame end code part 2

The CRC check code is generated by the 802.3 standard CRC polynomial generator, and the CRC polynomial is:

G(X)＝X ³² +X ²⁶ +X ²³ +X ²² +X ¹⁶ +X ¹² +X ¹¹ +X ¹⁰ +X 8 +X ⁷ +X ⁵ + ^{X 4 +} X ² +X ¹ +1;

Bus interface type data receiving buffer control module: see FIG. 6 , this module is composed of a write address generating submodule 61 and a dual-port RAM submodule 62 . The write address generation sub-module 61 generates the write address of the dual-port RAM at an appropriate time after the lower circuit receives the valid Ethernet data frame. The dual-port RAM sub-module 62 is a dual-port RAM with unequal port widths for one-way data transmission. Its write-in port width is 4, and the read-out width at the processor interface side is based on the actual bus width of the processor. After the lower circuit receives a frame, there will be an interrupt signal. In bus read mode outside the processor, the total length of the Ethernet data frame, CRC check result flag, destination address, source address, length/type field of the Ethernet data frame, and data and filling PAD are read from the dual-port RAM. The write address generating module 61 clears the interrupt signal when the processor executes the first read instruction, and the program should ensure that the time for reading the entire received data frame at one time is as short as possible to ensure the integrity of the Ethernet frame.

Bus interface type frame receiving and processing module: see as shown in Figure 7, by CDR (clock and data recovery circuit) submodule 71, 5 frequency division submodule 72, parallel/serial conversion submodule 73, CRC check code generation submodule 74 , "frame header/frame tail identification" submodule 75, frame extraction submodule 76, serial/parallel conversion submodule 77, 5B/4B conversion submodule 78, CRC comparison submodule 79 and frame length counting submodule 710. The CDR sub-module 71 is used to regenerate 125M data and clock signals from the LVDS signals from the backplane. The 5-frequency sub-module 72 is used to divide the recovered 125M clock signal into a 25M clock signal for internal parallel processing. The "frame head/frame tail identification" sub-module 75 is used to generate frame signal start and frame signal valid signals according to the data characteristics of the signal code stream. The frame extraction sub-module 76 is used to extract the serial code stream of the Ethernet frame from the destination address to the CRC check code. The serial/parallel conversion sub-module 77 performs serial/parallel conversion on the serial data from the frame extraction sub-module 76 to become parallel data with a width of 5B. The 5B/4B conversion sub-module 78 converts the parallel data into data with a width of 4B according to the comparison table shown in Table 1. On the one hand, it is written into the receiving buffer dual-port RAM, and on the other hand, it passes through the parallel/serial conversion sub-module 73 again Parallel/serial conversion is performed, and the serial data generates a CRC check code through the CRC check code generation sub-module 74 . The generated CRC check code is compared with the received CRC check code by the CRC comparison submodule 79, and according to the result of the comparison, the CRC check result is written to the byte with a fixed offset of 2 in the receiving buffer unit middle. The frame length counting sub-module 710 calculates the length of the received frame according to the signal generated by the "frame head/frame tail identification" sub-module 75, and writes this length data to the byte whose fixed offset of the receiving buffer unit is 0 middle. The generation algorithm of the CRC check code is the same as the above-mentioned sending process.

Taking the frame structure of 100BASE-TX as an example, each component module of the MII interface data communication circuit is described in detail:

MII interface type communication interface circuit frame transmission processing module: see Fig. 8, this module is composed of 4B/5B conversion sub-module 81, parallel/serial conversion sub-module 82, LVDS level conversion circuit 83, 5 frequency division sub-module 84. The 4B/5B conversion sub-module 81 converts the 4-bit parallel data from the MII interface into a 5B code, and the conversion rules are shown in Table 1. The parallel/serial conversion sub-module 82 sends out the 5B coded data serially at a rate of 125MHz.

MII interface type communication interface circuit frame receiving and processing module: see Fig. 9, this module is made up of CDR submodule 91, 5 frequency division submodule 92, "frame head/frame tail identification" submodule 93, frame extraction submodule 94, string/ And the conversion sub-module 95 and the 5B/4B conversion sub-module 96 are formed. The CDR sub-module 91 regenerates the LVDS signal stream from the line into 125MHz data and clock, and generates a CRS signal. The 5-frequency sub-module 92 divides the frequency of the line clock to obtain RX_CLK, the "frame head/frame tail identification" sub-module 93 processes the RX_DV signal, and the frame extraction sub-module 94 extracts the complete Ethernet start code and the complete Ethernet frame, The serial/parallel conversion sub-module 95 performs serial/parallel conversion on the 5B code of the line to become parallel data of 5-BIT width, and then outputs it to the 5B/4B conversion sub-module 96 to restore the 4B code. The conversion rules are shown in Table 1 . Get the RXD3:0 signal of the MII interface.

The processing steps of the software part are as follows: the MAC address adopts the form of a local effective address, that is, the second bit of the address is fixed to 1. In the case of local settings, the present invention adopts that after each unit board is powered on, the processor can generate it in a system according to the chassis/slot signal obtained from the backplane through a certain algorithm. Unique MAC address for Ethernet communication between boards. For the higher-level network address, such as the corresponding communication IP address of the board, it is obtained through DHCP, and can also be bound with the slot information of the board in a similar manner.

The present invention is mainly aimed at changing the physical layer below the MII interface of the 802.3 100BASE-TX standard, which is completely transparent to the upper layer protocol, so it is completely feasible to still use the TYPE 1 method specified in the 802.2 LLC protocol for the interface of the network layer of. In terms of flow control, according to Appendix 31B of the 802.3 standard, the unit that needs to perform flow control can send a PAUSE frame after receiving one or several frames of data according to the processing performance. The length of the pause is written to the request_operand field of the PAUSE frame. Before each board sends information to the outside, it needs to analyze whether the sending target has a flow control request. If so, the sending is delayed according to the time declared by the peer. In the case of broadcast or multicast, the sender delay is determined by the largest interval value.

The data communication of the present invention is limited to the data exchange of the second layer, as long as the MAC addresses of each functional unit are not repeated, the data exchange of each unit can be completed through the switching center. Since the underlying link adopts the 100M full-duplex mode, when communicating with a single-chip microcomputer or a low-performance processor and a high-performance processor with an MII interface, a flow control mechanism needs to be introduced according to different processing capabilities. The flow control mechanism adopts 802.3 The standard PAUSE frame is completed in conjunction with the upper layer application programs of each unit.

Claims (8)

1, a kind of data communication method of device interior is characterized in that, comprises the steps:

Step 1, structure is the hub-and-spoke configuration of core with the switching center unit between each functional unit and switching center unit, carries out both-way communication by the switching center unit between the functional unit;

Step 2, according to the difference of the processor type of functional unit, between functional unit and switching center unit, provide different communication interface circuit to connect:

When the processor of functional unit does not have standard ethernet MII interface, this functional unit is connected with the switching center unit by bus interface shape of the mouth as one speaks communication interface circuit;

When the processor of functional unit has standard ethernet MII interface, this functional unit is connected with the switching center unit by MII interface type communication interface circuit;

Step 3, use Low Voltage Differential Signal transmission the carrying out transmitting-receiving of signal between functional unit and switching center unit.

2, the means of communication according to claim 1 is characterized in that, carry out the frame structure of the The data 100BASE-TX of communication; In the described step 2, when the processor of functional unit did not have standard ethernet MII interface, the communication step between this functional unit and switching center unit was as follows:

Bus interface shape of the mouth as one speaks circuit sends data:

A, processor are written to the data that will send in the transmission buffering area of bus-type data transmit-receive buffering control module (22);

B, processor send " start and send " signal, the frame packing is provided and sends the encapsulation that processing module (24) is finished data, and to the encapsulation after data carry out 4B/5B conversion, parallel/serial conversion and LVDS level conversion, convert the LVDS signal to and send to the switching center unit;

After C, a frame send, send an interrupt notification processor by the bottom control circuit to processor immediately, this interrupt identification is eliminated when processor is write arbitrary buffer data;

Bus interface shape of the mouth as one speaks circuit receives data:

After D, switching center unit become the LVDS signal to data transaction, extract the overall process that checking treatment module (25) is finished frame extraction and CRC check through frame;

E, the reception buffering area of the frame signal content write bus type that extracts transmitting-receiving buffering control module (22), read at any time for processor;

F, after receiving buffering area and having write these contents, immediately by the bottom control circuit to interrupt notification processor of processor transmission, this interrupt identification is eliminated when processor is read buffer data.

3, method according to claim 2, it is characterized in that, in the described steps A, processor is the core that the PAD of the destination address of ethernet data frame, source address, length/type field and data and filling is written to transmission buffering control module (22) the dual port RAM circuit storage in the mode of external bus.

4, method according to claim 2 is characterized in that, among the described step B, frame data packing and transmission are handled and comprised:

B1, " lead code/initial code/end code/bell idles " generation submodule (51) successively send lead code and initial code arrives parallel/serial translation circuit submodule (52);

B2, dual port RAM (41) output 4 parallel-by-bit data, one the tunnel outputs to 4B/5B transformation submodule (54) through parallel/serial translation circuit submodule (52) carries out conversion, another road sends to CRC check sign indicating number generation submodule (53) with the form of serial data, generates the CRC check sign indicating number;

B3, the content of dual port RAM (41) read finish after, the CRC check sign indicating number is sent to 4B/5B transformation submodule (54);

After B4, CRC sent and finish, " lead code/initial code/end code/bell idles " generated submodule (51) and sends end code and bell idles, thereby finished the encapsulation process of data;

B5, packaged frame is carried out 4B/5B conversion, parallel/serial conversion and LVDS level conversion, convert the LVDS signal to and send to the switching center unit.

5, method according to claim 2 is characterized in that, among the described step D, provides the frame receiving processing module to finish that frame extracts and the CRC check process comprises:

D1, provide CDR module (71) will become data and the clock signal of 125M from the LVDS signal regeneration that backboard comes;

D2,5 frequency division submodules (72) are provided is the clock signal of 25M with 125M data and the clock signal frequency division that circuit recovers;

D3, provide " frame head/postamble identification " submodule (75) to produce frame signal to begin and the frame signal useful signal;

D4, provide frame to extract submodule (76) to extract Ethernet data frames and lead serial code stream till the CRC check sign indicating number from destination address;

D5, data that step D4 is extracted are by serial/parallel conversion, the 5B/4B conversion;

D6, the data after the step D5 conversion are carried out parallel/serial conversion,, produce the CRC check sign indicating number the input of the serial data after conversion CRC check submodule (74);

D7, the CRC check sign indicating number that step D6 is generated and the check code that receives compare by CRC comparison sub-module (79), and it is 2 byte that comparing result is put into the constant offset amount;

D8, the length that provides frame length counting submodule (710) to calculate the frame that receives, and length data is written to the reception buffer cell.

6, the means of communication according to claim 1 is characterized in that, carry out the frame structure of the The data 100BASE-TX of communication; In the described step 2, when the processor of functional unit had standard ethernet MII interface, the communication step of this functional unit and switching center unit was as follows:

G, processor are sent out interface by MII and are sent the data to frame transmission processing module, and frame sends processing module by the 4B/5B code conversion, and parallel/serial conversion becomes the LVDS signal data with the LVDS level translation with data transaction and sends out;

The data that H, switching center unit send are successively carried out the LVDS level translation, clock and data recovery, and serial/parallel conversion, the 5B/4B code conversion is received interface by MII after the Frame BORDER PROCESSING data is sent to processor.

7, the means of communication according to claim 6 is characterized in that, described step G comprises:

G1, provide 4B/5B transformation submodule (81), will become the 5B coding from 4 parallel-by-bit data conversions of MII interface;

G2, provide parallel/serial transformation submodule (82), the data transaction behind the 5B coding is become the multirate serial data of 125MHz;

G3, provide LVDS level-conversion circuit (83), the serial data that obtains among the step G2 is transformed to the LVDS signal sends to the switching center unit.

8, the means of communication according to claim 6 is characterized in that, described step H comprises:

H1, provide data and the clock of the LVDS signal flow regeneration 125MHz that CDR submodule (91) comes circuit, and produce the CRS signal;

H2, provide 5 frequency division submodules (92) that the line clock frequency division is obtained RX_CL;

H3, provide " frame head/postamble identification " submodule (93) to handle to obtain the RX_DV signal;

H4, provide frame to extract the extraction that submodule (94) carries out complete ether initial code and complete Ether frame;

H5, provide serial/parallel transformation submodule (95) that the 5B of circuit coding is carried out serial/parallel conversion, become the parallel data of 5-BIT width, output to 5B/4B transformation submodule (96) then and carry out the reduction of 4B coding, obtain the RXD3:0 signal of MII interface.

Images