WO2022042396A1

WO2022042396A1 - Data transmission method and system, and chip

Info

Publication number: WO2022042396A1
Application number: PCT/CN2021/113286
Authority: WO
Inventors: 潘德灿; 马永吉; 王小东
Original assignee: 中兴通讯股份有限公司
Priority date: 2020-08-28
Filing date: 2021-08-18
Publication date: 2022-03-03
Also published as: CN114124594A

Abstract

The present application provides a data transmission method and system, a chip, and a computer readable medium. The data transmission method is applied in a chip, and comprises: receiving an on-chip bus write access request, wherein the on-chip bus write access request comprises valid data; obtaining configuration information of an encapsulation header; and encapsulating the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and sending the first Ethernet packet, wherein the first Ethernet packet comprises the encapsulation header and the valid data.

Description

Data transmission method and system, chip

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. 202010902743.3 filed on August 28, 2020, the entire contents of which are incorporated herein by reference in their entirety.

technical field

The embodiments of the present disclosure relate to the field of integrated circuit design, and in particular, to a data transmission method, system, and chip.

Background technique

At present, the most widely used and mature way of inter-chip data transfer (or inter-chip direct data access) is to use the high-speed serial computer expansion bus standard (PCIE, Peripheral Component Interconnect Express) interface, but the PCIE interface only supports point-to-point access, The topology is inflexible and can only support data transfer between on-board chips, and is mainly used in X86 computer systems. In addition, the PCIE interface has high operating frequency, complex interface implementation and debugging, and limited single-channel bandwidth.

As Ethernet technology becomes more and more widely used, the transmission bandwidth of Ethernet becomes higher and higher, and the Ethernetization of chip interfaces becomes more and more obvious. The use of Ethernet packets for inter-chip data transmission will be an important trend. Great advantage. Inter-chip data transfer based on Ethernet packets can utilize the flexible routing characteristics of Ethernet packets to build a flexible topology by relying on independent switching chips on or between boards or switching accelerators embedded in chips. However, the implementation process of the traditional method of inter-chip data transfer based on Ethernet packets is too complicated, which increases the complexity of chip design, consumes more resources, and has a relatively large chip area and power consumption. , thereby increasing the cost of the chip.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure provide a data transmission method, system, and chip.

According to a first aspect, an embodiment of the present disclosure provides a data transmission method, which is applied to a first chip. The method includes: receiving an on-chip bus write access request; wherein the on-chip bus write access request includes: valid data; obtaining a package header and encapsulate the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and send the first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data.

According to a second aspect, an embodiment of the present disclosure provides a data transmission method, applied to a second chip, the method includes: receiving a first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data; The header includes: a custom header, and the custom header includes: when the valid data length and the access address are obtained, the valid data length and the access address are obtained from the first Ethernet packet; wherein, the access address is that the valid data is in the memory of the second chip. and obtaining valid data from the first Ethernet packet according to the valid data length, and writing the obtained valid data into the access address.

According to a third aspect, an embodiment of the present disclosure provides a chip, where the chip includes: at least one Ethernet sending module. Each Ethernet sending module includes: an on-chip bus write access request receiving sub-module, a configuration information acquiring sub-module and an Ethernet packet encapsulation sending sub-module; wherein, the on-chip bus write access request receiving sub-module is configured to receive the on-chip bus write access request; wherein, the on-chip bus write access request includes: valid data; the configuration information acquisition sub-module is configured to obtain the configuration information of the encapsulation header; The valid data is encapsulated into a first Ethernet packet, and the first Ethernet packet is sent; wherein the first Ethernet packet includes: an encapsulation header and valid data.

According to a fourth aspect, an embodiment of the present disclosure provides a chip, where the chip includes: at least one Ethernet receiving module. Each Ethernet receiving module includes: an Ethernet packet receiving submodule and a data writing submodule; wherein, the Ethernet packet receiving submodule is configured to receive a first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data; wherein, the data writing submodule is configured to obtain the valid data length and access address from the first Ethernet packet when the encapsulation header includes: a custom header, and the custom header includes: valid data length and access address address; wherein, the access address is the address of the valid data in the memory of the second chip; and the valid data is obtained from the first Ethernet packet according to the length of the valid data, and the obtained valid data is written into the address range.

According to a fifth aspect, an embodiment of the present disclosure provides a chip, including: at least one of the above-mentioned Ethernet sending modules, and at least one of the above-mentioned Ethernet receiving modules.

According to a sixth aspect, an embodiment of the present disclosure provides a data transmission system, including: a first chip and a third chip. The first chip is configured to receive an on-chip bus write access request; wherein, the on-chip bus write access request includes: valid data; obtain configuration information of the package header; and package the valid data into the first Ethernet according to the configuration information of the package header packet, and send the first Ethernet packet; wherein, the first Ethernet packet includes: an encapsulation header and valid data; the third chip is configured to receive the first Ethernet packet, and write the first Ethernet packet into the memory for random allocation After classifying the first Ethernet packet, it is listed in the queue designated by the central processing unit.

According to a seventh aspect, an embodiment of the present disclosure provides a data transmission system, including: a first chip and a second chip. The first chip is configured to receive an on-chip bus write access request; wherein, the on-chip bus write access request includes: valid data, valid data length and access address; wherein, the access address is the address of the valid data in the memory of the second chip ; Obtain the configuration information of the encapsulation header; and encapsulate the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and send the first Ethernet packet; wherein, the first Ethernet packet includes: an encapsulation header and valid data; encapsulation The header includes: a custom header, and the custom header includes: valid data length and access address; the second chip is configured to receive the first Ethernet packet; obtain the valid data length and access address from the first Ethernet packet; According to the valid data The length obtains valid data from the first Ethernet packet, and writes the obtained valid data into the access address.

According to an eighth aspect, an embodiment of the present disclosure provides a computer-readable medium, where the computer-readable medium stores a computer program, and the computer program is used to execute any one of the foregoing data transmission methods.

According to a ninth aspect, an embodiment of the present disclosure provides a chip including a CPU and a computer-readable medium, where the computer-readable medium stores a computer program, and when the computer program is run by the CPU, any one of the above data transmissions is performed method.

Description of drawings

Fig. 1 is the composition block diagram of the traditional inter-chip data mutual transmission system;

2 is a flowchart of a data transmission method provided by an embodiment of the present disclosure;

3 is a flowchart of a data transmission method provided by another embodiment of the present disclosure;

FIG. 4 is a block diagram of a chip provided by another embodiment of the present disclosure;

FIG. 5 is a block diagram of a chip provided by another embodiment of the present disclosure;

6 is a block diagram of a data transmission system provided by another embodiment of the present disclosure;

FIG. 7 is a block diagram of a data transmission system according to another embodiment of the present disclosure.

detailed description

In order to make those skilled in the art better understand the technical solutions of the present disclosure, the data transmission method, system, and chip provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

Example embodiments are described more fully hereinafter with reference to the accompanying drawings, but which may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

Various embodiments of the present disclosure and various features of the embodiments may be combined with each other without conflict.

As used herein, the term "and/or" includes any and all combinations of at least one of the associated listed items.

The terminology used herein is used to describe particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that when the terms "comprising" and/or "made of" are used in this specification, the stated features, integers, steps, operations, elements and/or components are specified to be present, but not precluded or Add at least one other feature, integer, step, operation, element, component, and/or group thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in common dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present disclosure, and will not be construed as having idealized or over-formal meanings, unless expressly so limited herein.

Figure 1 is a block diagram of a traditional inter-chip data mutual transmission system. As shown in Figure 1, the data processed by the subsystem (SUBSYS) of chip 1 needs to be transmitted to the memory (MEM, MEMory) of chip 2. The process is as follows:

The SUBSYS of chip 1 writes the processed data into the double rate (DDR, Double Data Rate) according to the instructions of the central processing unit (CPU, Central Processing Unit), and the Ethernet packet transmission accelerator (ETH_TX_ACC) according to the instructions of the CPU from the DDR The data to be sent is read from the corresponding address, and the read data is encapsulated into an Ethernet packet and sent to chip 2.

Chip 2 receives the Ethernet packet sent by chip 1, and the Ethernet packet receiving accelerator (ETH_RX_ACC) writes the received packet to a randomly assigned address in the memory, parses and classifies the packet and enters it into the queue designated by the CPU. The message queue ID (ID, Identity) is taken out from the queue, and the message is read and processed according to the message queue ID.

There are the following problems in the process of inter-chip data transfer:

(1) Assuming that the traffic demand for data mutual transmission is 50Gbps, then chip 1 needs to reserve 125Gbps (gigabit per second, Gbit per second) DDR bandwidth for the data mutual transmission channel in design (at 40% DDR utilization rate) For evaluation), assuming that the frequency of a DDR controller is 3200 megahertz (MHz) and the data bit width is 32 bits (bit), at least one more DDR controller (not shown in Figure 1) and reserved corresponding This will undoubtedly increase the complexity of the chip design, increase the chip area, and increase the power consumption of the chip, which will lead to an increase in the cost of chip applications (for example, the larger the chip area, the higher the cost of tape-out, and the larger the chip power consumption, the more heat dissipation required more devices, and additional DDR particles are required).

(2) In the process of data mutual transmission of chip 1, the CPU needs to participate in the whole process, that is, the CPU needs to issue a sending command to ETH_TX_ACC, and construct the description or message header structure required for message sending. Considering that the data flow of mutual transmission is relatively large, at least one CPU core is required to complete the work. Therefore, in the design of chip 1, it is necessary to reserve a CPU core for the data mutual transmission channel, and the introduction of the increase of CPU cores leads to the complexity of chip design. The increase in speed, the increase in the chip area, and the increase in the power consumption of the chip lead to an increase in the cost of the chip.

(3) After chip 2 receives the message, it needs ETH_RX_ACC to parse and classify the message, which will introduce complex logic, increase the complexity of chip design, increase the area of the chip, and increase the power consumption of the chip, thus causing the chip increase in cost.

FIG. 2 is a flowchart of a data transmission method provided by an embodiment of the present disclosure.

Referring to FIG. 2, an embodiment of the present disclosure provides a data transmission method, which is applied to a first chip. It should be noted that the first chip refers to a chip that needs to perform inter-chip data transmission, and may be any type of chip, such as Baseband processing chips, CPU chips, etc.

The method includes the following steps 200-202.

In step 200, an on-chip bus write access request is received; wherein, the on-chip bus write access request includes: valid data.

In some exemplary embodiments, the on-chip bus write access request may be initiated by any other data processing module (for example, the aforementioned SUBSYS) in the first chip after processing the data, and the valid data is the The data is obtained after the data is processed and needs to be transmitted to the second chip.

It should be noted that after the data processing module processes the data, it generally initiates multiple on-chip bus write access requests for the processed data, that is, the valid data in each on-chip bus write access request initiated. Only a small part of the processed data. The data processing module can periodically initiate an on-chip bus write access request. After receiving the on-chip bus write access request, if it is too late to process the on-chip bus write access request, it can temporarily store the on-chip bus write access request in random access memory. (RAM, Random Access Memory). Since the valid data in the on-chip bus write access request is only a small part of the processed data, temporarily storing the on-chip bus write access request in RAM does not take up too much storage space, that is, it does not take up much storage space. Too much storage space needs to be reserved for data transfer.

It should be noted that the size of the valid data in each on-chip bus write access request initiated can be set according to the actual situation or set arbitrarily, and can be set to an integer multiple of the bus bit width in general.

In some exemplary embodiments, since the current mainstream chip designs are mostly based on Advanced Reduced Instruction Set (RISC, Reduced Instruction Set Computing) (ARM, Advanced RISC Machine) cores, the on-chip interconnection adopts Advanced eXtensible Interface (AXI, Advanced eXtensible Interface) Therefore, the on-chip bus write access request can be initiated through the AXI bus, so as to realize the combination of the AXI bus and the Ethernet transmission technology, and realize efficient, simple and flexible direct data mutual transmission.

It should be noted that, with the development of technology, if other types of buses (non-AXI buses) are used for the on-chip interconnection, on-chip bus write access requests can also be initiated through other types of buses. The embodiment of the present disclosure does not limit the specific type of bus used to receive the write access request, and the specific bus type is not used to limit the protection scope of the embodiment of the present disclosure.

In some example embodiments, the on-chip bus write access request includes only valid data.

In some other exemplary embodiments, the on-chip bus write access request includes: valid data, valid data length (that is, the data length of the valid data above) and an access address; wherein, the access address is the valid data in the memory of the second chip address, such as an AXI bus write access request.

It should be noted that if the on-chip bus write access request does not include the effective data length and access address, the receiving chip needs to use the existing receiving chip to realize the reception of the first Ethernet packet. The second chip may not be able to write valid data. This is because there is no valid data length and access address in the first Ethernet packet, so the second chip cannot know where the valid data should be written in the memory. ; If the write access request includes the effective data length and the access address, the receiving chip can be implemented by using the second chip proposed by the embodiment of the present disclosure.

In step 201, configuration information of the encapsulation header is obtained.

In some exemplary embodiments, if the write access request includes the valid data length and the access address, the encapsulation header includes: a custom header, and the custom header includes: the valid data length DATA_LEN and the access address DST_ADDR; Including the effective data length DATA_LEN and the access address DST_ADDR, the package header does not include the custom header.

In some exemplary embodiments, the custom header further includes: a reserved field RESERVE. This reserved field can be used to adjust the length of the custom header or fill in other information that needs attention.

It should be noted that the specific positions of the valid data length DATA_LEN and the access address DST_ADDR in the custom header in the custom header can be arbitrarily set, and the bit width occupied in the custom header can also be arbitrarily set.

In some exemplary embodiments, the encapsulation header further includes at least one of the following: an Ethernet header, an Internet Protocol (IP, Internet Protocol) header, a User Datagram Protocol (UDP, User Datagram Protocol) header, a Transmission Control Protocol (TCP, Transmission Control Protocol) header.

In some exemplary embodiments, IP may be Internet Protocol Version 4 (IPV4, Internet Protocol Version 4) or Internet Protocol Version 6 (IPV6, Internet Protocol Version 6).

In some exemplary embodiments, the configuration information of the package header may be obtained from the CPU of the first chip.

In some exemplary embodiments, custom headers may be carried on any layer. For example, custom headers can be carried on top of L2 (ie data link layer) or L3 (ie network layer) or L4 (ie transport layer).

Specifically, if the custom header is carried at L2, the format of the encapsulation header is: Ethernet header + custom header; then, the configuration information of the encapsulation header includes: configuration information of the Ethernet header and configuration information of the custom header.

If the custom header is carried at L3, the format of the encapsulation header is: Ethernet header + IP header + custom header; then, the configuration information of the encapsulation header includes: configuration information of the Ethernet header, configuration information of the IP header, and custom header Header configuration information.

If the custom header is carried at L4, the format of the encapsulation header is: Ethernet header + IP header + UDP header or TCP header + custom header; then the configuration information of the encapsulation header includes: configuration information of the Ethernet header, configuration information of the IP header Configuration information, configuration information of UDP header or configuration information of TCP header, configuration information of custom header.

In some exemplary embodiments, the configuration information of the Ethernet header includes: a Media Access Control (MAC, Media Access Controll) destination address, a MAC source address, and an EtherType (EtherType) field.

The configuration information of the IP header includes: IP header type (such as 4 for IPV4, 6 for IPV6), IP header length and specific IP header field content, which will not be described in detail here; the format and content of the configuration IPV4 header conform to the RFC791 protocol, where , the total length (Total Length) field and the header checksum (HeaderChecksum) field can be configured as 0, and updated by the Ethernet sending module in the first chip; the format and content of the configured IPV6 header conform to the RFC8200 protocol, wherein, The payload length (PayloadLength) may be configured as 0, and is updated by the Ethernet sending module in the first chip.

The format and content of the configured UDP header conform to the RFC768 protocol, wherein the length (Length) and checksum (Checksum) fields are configured as 0, and are updated by the Ethernet sending module in the first chip.

The configuration information of the TCP header conforms to the RFC793 protocol.

The configuration information of the custom header includes: the length of the custom header, reserved fields, DATA_LEN and DST_ADDR, wherein DATA_LEN and DST_ADDR are configured to be 0, and are updated by the Ethernet sending module in the first chip.

In step 202, the valid data is encapsulated into a first Ethernet packet according to the configuration information of the encapsulation header, and the first Ethernet packet is sent; wherein the first Ethernet packet includes: an encapsulation header and valid data.

Specifically, if the custom header is carried on L2, the format of the first Ethernet packet is: Ethernet header + custom header + valid data; if the custom header is carried on L3, the format of the first Ethernet packet is: Ethernet header+IP header+custom header+valid data; if the custom header is carried in L4, the format of the first Ethernet packet is: Ethernet header+IP header+UDP header or TCP header+custom header+valid data.

In some exemplary embodiments, encapsulating the valid data into the first Ethernet packet according to the configuration information of the encapsulation header includes: selecting an Ethernet header, an IP header, a UDP header or a TCP for encapsulating the first Ethernet packet according to the access address At least one of the headers, and at least one of the selected Ethernet header, IP header, UDP header or TCP header and the custom header, and the valid data are encapsulated into a first Ethernet packet.

In some exemplary embodiments, selecting at least one of an Ethernet header, an IP header, a UDP header or a TCP header for encapsulating the first Ethernet packet according to the access address includes: In the correspondence between at least one of the Ethernet header, IP header, UDP header or TCP header of the network packet and the address range, find the Ethernet header used to encapsulate the first Ethernet packet corresponding to the address range where the access address is located. At least one of a net header, an IP header, a UDP header, or a TCP header.

It should be noted that different address ranges correspond to different MAC addresses and IP addresses in at least one of the Ethernet header, IP header, UDP header or TCP header used to encapsulate the first Ethernet packet.

It should be noted that since the MAC address and IP address of different chips are different, however, the chip cannot know the MAC address and IP address of the chip when encapsulating the first Ethernet packet, so the memory addresses of different chips can be changed. The ranges are set to non-overlapping areas so that different chips can be distinguished.

In some exemplary implementations, if the first chip does not include the first switching module, nor does the first chip and the second chip include a switching chip, sending the first Ethernet packet includes: sending the first Ethernet packet To the media access control (MAC, Media Access Control) layer, the MAC layer obtains the second Ethernet packet after corresponding processing on the first Ethernet packet (such as adding a cyclic redundancy check code (CRC, Cyclic Redundancy Check), adding preamble, stuffing bytes, etc.), the second Ethernet packet is sent to the second chip through the first Ethernet transmission interface of the first chip. In this manner, the reason why a switch chip or a first switch module is not required to implement the transmission of the first Ethernet packet is for the case of point-to-point data transmission with a simple topology.

In some other exemplary embodiments, if the first chip includes a first switch module and a switch chip is not included between the first chip and the second chip, sending the first Ethernet packet includes: sending the first Ethernet packet to The first switching module of the first chip, the first switching module of the first chip sends the first Ethernet packet to the MAC layer, and the MAC layer performs corresponding processing on the first Ethernet packet to obtain the second Ethernet packet, and passes the first Ethernet packet. The first Ethernet transmission interface of one chip sends the second Ethernet packet to the second chip.

In some other exemplary embodiments, if a switch chip is included between the first chip and the second chip, and the first chip does not include the first switch module, sending the first Ethernet packet includes: sending the first Ethernet packet to The MAC layer obtains a second Ethernet packet after the MAC layer performs corresponding processing on the first Ethernet packet, and sends the second Ethernet packet to the switching chip through the first Ethernet transmission interface of the first chip.

The switch chip sends the second Ethernet packet to the second chip.

In some exemplary implementations, the first Ethernet transmission interface of the first chip may be a standard 50 or 25 or 10 or 5 Gbps Ethernet transmission interface, and may also be an Ethernet transmission interface of other rates. The specific rate of the first Ethernet transmission interface is not limited, and the size of the specific rate is not used to limit the protection scope of the embodiments of the present disclosure.

In the data transmission method provided by the embodiments of the present disclosure, when valid data needs to be sent, the valid data is directly encapsulated into a first Ethernet packet and sent out, without first writing the valid data into a double rate (DDR, Double Data Packet). Rate), effectively reducing the bandwidth of DDR; no CPU participation is required in the process of transmitting valid data, that is, no additional CPU core resources are occupied; thus reducing the complexity of chip design and effectively reducing the area and power of the chip. consumption, which reduces the cost of the chip.

FIG. 3 is a flowchart of a data transmission method provided by another embodiment of the present disclosure.

Referring to FIG. 3 , another embodiment of the present disclosure provides a data transmission method, which is applied to a second chip. It should be noted that the second chip refers to a chip that needs to perform inter-chip data transmission, and may be any type of chip. Such as baseband processing chips, CPU chips, etc.

The method includes the following steps 300-302.

In step 300, a first Ethernet packet is received; wherein the first Ethernet packet includes: an encapsulation header and valid data.

In some exemplary embodiments, if the second chip does not include the second switching module, and the switching chip is not included between the first chip and the second chip, the received first Ethernet packet refers to the first Ethernet packet passing through the second chip. The first Ethernet packet is received by the second Ethernet transmission interface and processed by the MAC layer of the second chip, and the Ethernet packet received by the second Ethernet transmission interface of the second chip is sent by the first chip. Second Ethernet packet.

In some exemplary embodiments, if the second chip includes a second switch module and no switch chip is included between the first chip and the second chip, the received first Ethernet packet refers to the second Ethernet packet passing through the second chip The network transmission interface receives the first Ethernet packet after corresponding processing by the MAC layer of the second chip, and transmits the first Ethernet packet through the second switching module of the second chip, and the second Ethernet transmission interface of the second chip receives the first Ethernet packet. The Ethernet packet is the second Ethernet packet sent by the first chip.

In some exemplary embodiments, if a switch chip is included between the first chip and the second chip, and the second chip does not include a second switch module, the received first Ethernet packet refers to the second Ethernet packet passing through the second chip. The first Ethernet packet received by the network transmission interface and correspondingly processed by the MAC layer of the second chip, and the Ethernet packets received by the second Ethernet transmission interface of the second chip are the first chip and the second chip. The second Ethernet packet is sent between the switch chips.

In some exemplary implementations, the second Ethernet transmission interface of the second chip may be a standard 50 or 25 or 10 or 5 Gbps Ethernet transmission interface, and may also be an Ethernet transmission interface of other rates. The specific rate of the second Ethernet transmission interface is not limited, and the size of the specific rate is not used to limit the protection scope of the embodiments of the present disclosure.

In some exemplary embodiments, after receiving the first Ethernet packet, if it is too late to process the first Ethernet packet, the first Ethernet packet may be temporarily stored in RAM.

In some exemplary embodiments, the encapsulation header may or may not include a custom header.

In some exemplary embodiments, the custom header includes: effective data length DATA_LEN and access address DST_ADDR.

In some exemplary embodiments, the encapsulation header further includes at least one of the following: an Ethernet header, an IP header, a UDP header, and a TCP header.

In some exemplary embodiments, the IP may be IPV4 or IPV6.

In step 301, when the encapsulation header includes: a custom header, and the custom header includes: valid data length and access address, obtain the valid data length and access address from the first Ethernet packet; wherein, the access address is valid data in Access address in memory.

In some exemplary embodiments, when the encapsulation header does not include the custom header, the received first Ethernet packet may be directly discarded.

In some exemplary embodiments, before acquiring the effective data length and the access address from the first Ethernet packet, the method further includes: acquiring position offset information of the custom header in the first Ethernet packet.

Acquiring the effective data length and the access address from the first Ethernet packet includes: acquiring the effective data length and the access address from the first Ethernet packet according to the position offset information. Specifically, the user-defined header may be obtained from the first Ethernet packet according to the position offset information, and the effective length and the access address may be obtained from the user-defined header.

In some exemplary embodiments, the position offset information refers to the offset of the custom header from the starting position of the encapsulation header of the first Ethernet packet.

In some exemplary embodiments, the position offset information of the custom header in the first Ethernet packet may be acquired from the CPU.

In step 302, valid data is obtained from the first Ethernet packet according to the valid data length, and the obtained valid data is written into the access address.

In some exemplary embodiments, obtaining the valid data from the first Ethernet packet according to the valid data length includes: intercepting data whose length is the valid data length from the payload data of the first Ethernet packet, which is the valid data.

In some exemplary embodiments, since most of the current mainstream chip designs are based on ARM cores, and the on-chip interconnection adopts AXI bus, the obtained valid data can be written into the access address through the AXI bus, thereby realizing the connection between the AXI bus and the Ethernet Network transmission technology is combined to achieve efficient, simple and flexible direct data mutual transmission.

It should be noted that, with the development of technology, if other types of buses (non-AXI buses) are used for the on-chip interconnection, the obtained valid data can also be written into the access address through other types of buses. The embodiment of the present disclosure does not limit the specific type of bus used to write the obtained valid data into the access address, and the specific bus type is not used to limit the protection scope of the embodiment of the present disclosure.

In the data transmission method provided by the embodiments of the present disclosure, when the first Ethernet packet is received, valid data is directly obtained from the first Ethernet packet and written into the corresponding access address, without the need to perform any processing on the first Ethernet packet. Analysis and classification, the realization of logic is relatively simple, thereby reducing the complexity of chip design, effectively reducing the area and power consumption of the chip, and also reducing the cost of the chip.

FIG. 4 is a block diagram of a chip provided by another embodiment of the present disclosure.

4, another embodiment of the present disclosure provides a chip, including: at least one Ethernet sending module; each Ethernet sending module includes: an on-chip bus write access request receiving sub-module 401, a configuration information obtaining sub-module 402 and Ethernet packet encapsulation and transmission sub-module 403 .

Wherein, the on-chip bus write access request receiving sub-module 401 is configured to receive the on-chip bus write access request; wherein, the on-chip bus write access request includes: valid data; the configuration information obtaining sub-module 402 is configured to obtain the configuration of the package header information; the Ethernet packet encapsulation and transmission submodule 403 is configured to encapsulate the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and send the first Ethernet packet; wherein, the first Ethernet packet includes: the encapsulation header and the valid data.

In some exemplary embodiments, the on-chip bus write access request may be initiated by any other data processing module (for example, the aforementioned SUBSYS) in the first chip after processing the data, and the valid data is the The data is obtained after the data is processed and needs to be transmitted to the second chip. That is to say, the chip further includes: a data processing module 404, which is configured to perform corresponding processing on the data to obtain valid data, and initiate a write access request to the on-chip bus.

It should be noted that, after the data processing module 404 processes the data, it generally initiates multiple on-chip bus write access requests for the processed data, that is to say, the valid on-chip bus write access request initiated each time is valid. The data is only a small part of the processed data. The data processing module 404 can periodically initiate an on-chip bus write access request. After receiving the on-chip bus write access request, if it is too late to process the on-chip bus write access request, it can temporarily store the on-chip bus write access request to the on-chip bus. The write access request is received in the RAM of the sub-module 401 . Since the valid data in the on-chip bus write access request is only a small part of the processed data, temporarily storing the on-chip bus write access request in the RAM of the request receiving sub-module 401 will not occupy too much space Storage space, that is, there is no need to reserve too much storage space for data transmission.

It should be noted that the size of the valid data in each on-chip bus write access request initiated can be set according to the actual situation or can be set at will. Generally, it can be set as the bus connecting the data processing module 404 and the Ethernet sending module. Integer multiple of the bit width.

In some exemplary embodiments, since most of the current mainstream chip designs are based on ARM cores, and the on-chip interconnection adopts AXI bus, therefore, an on-chip bus write access request can be initiated through the AXI bus, that is, between the data processing module 404 and the Ethernet sending module. They are interconnected through the AXI bus, so as to realize the combination of the AXI bus and the Ethernet transmission technology to achieve efficient, simple and flexible direct data mutual transmission.

It should be noted that, with the development of technology, if other types of buses (non-AXI buses) are used for the on-chip interconnection, the data processing module 404 and the Ethernet transmission module may also be connected through other types of buses. The embodiment of the present disclosure does not limit what type of bus is used to connect the data processing module 404 and the Ethernet sending module, and the specific bus type is not used to limit the protection scope of the embodiment of the present disclosure.

In other exemplary embodiments, the on-chip bus write access request includes: valid data and an address range of the valid data in the memory of the second chip.

In other exemplary embodiments, the write access request includes valid data.

In other exemplary embodiments, the on-chip bus write access request includes: valid data, valid data length and access address; wherein, the access address is the address of the valid data in the memory of the second chip, such as an AXI bus write access request .

It should be noted that if the on-chip bus write access request does not include the effective data length and access address, the receiving chip needs to use the existing receiving chip to realize the reception of the first Ethernet packet. The second chip cannot realize the writing of valid data, because there is no valid data length and access address in the first Ethernet packet, so the second chip cannot know where the valid data should be written in the memory; If the write access request includes the effective data length and the access address, the receiving chip may be implemented by using the second chip provided by the embodiment of the present disclosure.

In some exemplary embodiments, the IP may be IPV4 or IPV6.

In some exemplary embodiments, the configuration information of the Ethernet header includes: a MAC destination address, a MAC source address, and an EtherType (EtherType) field.

The configuration information of the IP header includes: IP header type (such as 4 for IPV4, 6 for IPV6), IP header length and specific IP header field content, which will not be described in detail here; the format and content of the configuration IPV4 header conform to the RFC791 protocol, where , the Total Length field and the HeaderChecksum field can be set to 0, which is updated by the Ethernet sending module in the first chip; the format and content of the configured IPV6 header conform to the RFC8200 protocol, and the PayloadLength can be set to 0, and the first The Ethernet sending module in the chip is updated.

The format and content of the configured UDP header conform to the RFC768 protocol, wherein the Length and Checksum fields are configured as 0, and are updated by the Ethernet sending module in the first chip.

Specifically, if the custom header is carried on L2, the format of the first Ethernet packet is: Ethernet header + custom header + valid data;

If the custom header is carried at L3, the format of the first Ethernet packet is: Ethernet header+IP header+custom header+valid data;

If the custom header is carried at L4, the format of the first Ethernet packet is: Ethernet header+IP header+UDP header or TCP header+custom header+valid data.

In some exemplary implementations, the first Ethernet packet encapsulation and transmission sub-module 403 is configured to implement encapsulation of valid data into the first Ethernet packet according to the configuration information of the encapsulation header in the following manner: selecting the first Ethernet packet for encapsulating the first Ethernet packet according to the access address At least one of the Ethernet header, IP header, UDP header or TCP header of the Ethernet packet, at least one of the selected Ethernet header, IP header, UDP header or TCP header and custom header, and valid data Encapsulated into a first Ethernet packet.

In some exemplary implementations, the first Ethernet packet encapsulation and sending sub-module 403 is configured to select the Ethernet header, IP header, UDP header or TCP header for encapsulating the first Ethernet packet according to the access address in the following manner At least one of: in the preset at least one of the Ethernet header, IP header, UDP header or TCP header for encapsulating the first Ethernet packet, and the corresponding relationship between the address range, find where the access address is located The address range corresponding to at least one of an Ethernet header, an IP header, a UDP header or a TCP header for encapsulating the first Ethernet packet.

In some exemplary embodiments, if the first chip does not include the first switch module, nor does the first chip and the second chip include a switch chip, the Ethernet packet encapsulation sending sub-module 403 is configured to be implemented in the following manner Sending the first Ethernet packet: sending the first Ethernet packet to the MAC layer, and the MAC layer performs corresponding processing on the first Ethernet packet to obtain a second Ethernet packet, and sends the second Ethernet packet through the first Ethernet transmission interface of the first chip. The second Ethernet packet is sent to the second chip. In this manner, the reason why a switch chip or a switch module is not needed to realize the transmission of the first Ethernet packet is for the case of point-to-point data transmission with a simple topology. That is, the chip further includes: the first Ethernet transmission interface 405, which is configured to send the second Ethernet packet output by the MAC layer to the second chip.

In some other exemplary embodiments, if the first chip includes a first switch module and no switch chip is included between the first chip and the second chip, the Ethernet packet encapsulation sending sub-module 403 is configured to implement sending in the following manner The first Ethernet packet: the first Ethernet packet is sent to the first switching module of the first chip, and the first switching module of the first chip sends the first Ethernet packet to the MAC layer, and the MAC layer responds to the first Ethernet packet. After corresponding processing, a second Ethernet packet is obtained, and the second Ethernet packet is sent to the second chip through the first Ethernet transmission interface of the first chip. That is to say, the chip further includes the first switching module 406 and the second Ethernet transmission interface 405 .

The first switching module 406 is configured to send the first Ethernet packet output by the Ethernet packet encapsulation and sending sub-module 403 to the MAC layer, and the MAC layer performs corresponding processing on the first Ethernet packet to obtain the second Ethernet packet.

The first Ethernet transport interface 405 is configured to send the second Ethernet packet output by the MAC layer to the second chip.

In other exemplary embodiments, if a switch chip is included between the first chip and the second chip, and the first chip does not include the first switch module, the Ethernet packet encapsulation sending sub-module 403 is configured to implement sending in the following manner The first Ethernet packet: the first Ethernet packet is sent to the MAC layer, and the MAC layer performs corresponding processing on the Ethernet packet to obtain the second Ethernet packet, and the second Ethernet packet is transmitted through the first Ethernet transmission interface of the first chip. The network packet is sent to the switch chip. That is to say, the chip further includes: the first Ethernet transmission interface 405, which is configured to send the second Ethernet packet output by the MAC layer to the switching chip.

The switch chip sends the second Ethernet packet to the second chip.

In the chip provided by the embodiment of the present disclosure, when valid data needs to be sent, the valid data is directly encapsulated into a first Ethernet packet and sent out, without first writing the valid data into Double Data Rate (DDR, Double Data Rate). , effectively reducing the bandwidth of the DDR; the process of transmitting valid data does not require CPU participation, that is, does not require additional CPU core resources; thus reducing the complexity of chip design, effectively reducing chip area and power consumption, It also reduces the cost of the chip.

It should be noted that all modules and sub-modules on the chip are implemented in hardware, which can be designed in a hardware description language (such as Verilog or VHDL, Very-High-Speed Integrated Circuit Hardware Description Language) Implementation, specific implementation circuit The embodiments of the present disclosure are not limited, nor are they intended to limit the protection scope of the embodiments of the present disclosure.

FIG. 5 is a block diagram of a chip provided by another embodiment of the present disclosure.

5 , another embodiment of the present disclosure provides a chip, the chip includes: at least one Ethernet receiving module; each Ethernet receiving module includes: an Ethernet packet receiving submodule 501 and a data writing submodule 502 .

The Ethernet packet receiving sub-module 501 is configured to receive a first Ethernet packet, wherein the first Ethernet packet includes: an encapsulation header and valid data.

The data writing submodule 502 is configured to obtain the effective data length and the access address from the first Ethernet packet when the encapsulation header includes: a custom header, and the custom header includes: the effective data length and the access address; wherein, the access address is the address of the valid data in the memory; the valid data is obtained from the first Ethernet packet according to the length of the valid data, and the obtained valid data is written into the access address.

In some exemplary embodiments, if the second chip does not include the second switching module, and the switching chip is not included between the first chip and the second chip, the received first Ethernet packet refers to the first Ethernet packet passing through the second chip. The first Ethernet packet is received by the second Ethernet transmission interface and processed by the MAC layer of the second chip, and the Ethernet packet received by the second Ethernet transmission interface of the second chip is sent by the first chip. Second Ethernet packet. That is to say, the chip further includes: a second Ethernet transmission interface 503, which is configured to receive the second Ethernet packet sent by the first chip, and send the received second Ethernet packet to the MAC layer, and the MAC layer performs corresponding processing After processing, the first Ethernet packet is obtained, and the first Ethernet packet is sent to the Ethernet packet receiving sub-module 501 .

In some exemplary embodiments, if the second chip includes a second switch module and no switch chip is included between the first chip and the second chip, the received first Ethernet packet refers to the second Ethernet packet passing through the second chip The network transmission interface receives the first Ethernet packet after corresponding processing by the MAC layer of the second chip, and transmits the first Ethernet packet through the second switching module of the second chip, and the second Ethernet transmission interface of the second chip receives the first Ethernet packet. The first Ethernet packet is the second Ethernet packet sent by the first chip. That is to say, the chip further includes a second Ethernet transmission interface 503 and a second switching module 504 .

The second Ethernet transmission interface 503 is configured to receive the second Ethernet packet sent by the first chip, send the received second Ethernet packet to the MAC layer, and the MAC layer performs corresponding processing to obtain the first Ethernet packet, The first Ethernet is sent to the second switching module 504 .

The second switching module 504 is configured to send the first Ethernet packet to the Ethernet packet receiving sub-module 501 .

In some exemplary embodiments, if a switch chip is included between the first chip and the second chip, and the second chip does not include a second switch module, the received first Ethernet packet refers to the second Ethernet packet passing through the second chip. The first Ethernet packet received by the network transmission interface and correspondingly processed by the MAC layer of the second chip, and the Ethernet packets received by the second Ethernet transmission interface of the second chip are the first chip and the second chip. The second Ethernet packet is sent between the switch chips. That is to say, the chip further includes: a second Ethernet transmission interface 503, which is configured to receive the second Ethernet packet sent by the switching chip, and send the received second Ethernet packet to the MAC layer, and the MAC layer performs corresponding processing. After processing, the first Ethernet packet is obtained, and the first Ethernet packet is sent to the Ethernet packet receiving sub-module 501 .

In some exemplary embodiments, the second Ethernet transmission interface 503 of the second chip may be a standard 50 or 25 or 10 or 5 Gbps Ethernet transmission interface, and may also be an Ethernet transmission interface of other rates. The example does not limit the specific rate of the second Ethernet transmission interface 503, and the size of the specific rate is not used to limit the protection scope of the embodiments of the present disclosure.

In some exemplary embodiments, after the Ethernet packet receiving sub-module 501 receives the first Ethernet packet, if the Ethernet packet receiving sub-module 501 is too late to process the first Ethernet packet, the first Ethernet packet may be temporarily Stored in the RAM of the Ethernet packet receiving sub-module 501 .

It should be noted that the specific positions of the valid data length DATA_LEN and the address range DST_ADDR in the custom header can be set arbitrarily in the custom header, and the bit width occupied in the custom header can also be arbitrarily set.

In some exemplary embodiments, the IP may be IPV4 or IPV6.

In some exemplary embodiments, when the encapsulation header does not include a custom header, the data writing sub-module 502 may directly discard the received first Ethernet packet.

In some exemplary embodiments, the chip further includes: a position offset information obtaining module 505, which is configured to obtain position offset information of the custom header in the first Ethernet packet.

Correspondingly, the data writing sub-module 502 is configured to obtain the effective data length and the access address from the first Ethernet packet according to the position offset information. Specifically, the user-defined header may be obtained from the first Ethernet packet according to the position offset information, and the effective length and the access address may be obtained from the user-defined header.

In some exemplary embodiments, the position offset information of the custom header in the first Ethernet packet may be obtained from the CPU.

In some exemplary implementations, since most of the current mainstream chip designs are based on ARM cores, and the on-chip interconnection adopts AXI bus, the data writing sub-module 502 and the memory can be connected through the AXI bus, so as to realize the transmission between the AXI bus and the Ethernet Technologies are combined to achieve efficient, simple and flexible direct data transfer.

It should be noted that, with the development of technology, if other types of buses are used for the on-chip interconnection, data writing to the sub-module 502 and the memory may also be connected through other types of buses. The embodiment of the present disclosure does not limit the specific type of bus used to connect the data writing sub-module 502 and the memory, and the specific bus type is not used to limit the protection scope of the embodiment of the present disclosure.

The chip provided by the embodiment of the present disclosure, when receiving the first Ethernet packet, directly obtains valid data from the first Ethernet packet and writes it into the corresponding access address, without analyzing and classifying the first Ethernet packet , the implementation logic is relatively simple, thereby reducing the complexity of chip design, effectively reducing the area and power consumption of the chip, and also reducing the cost of the chip.

It should be noted that all modules and sub-modules on the chip are implemented in hardware, which can be designed and implemented by using a hardware description language (such as Verilog or VHDL). Scope of protection of the embodiments.

Another embodiment of the present disclosure provides a chip, including: at least one any of the foregoing Ethernet sending modules, and at least one any of the foregoing Ethernet receiving modules.

FIG. 6 is a block diagram of a data transmission system according to another embodiment of the present disclosure.

Referring to FIG. 6 , another embodiment of the present disclosure provides a data transmission system, where the data transmission system includes a first chip 601 and a third chip 602 .

The first chip 601 is configured to receive an on-chip bus write access request; wherein, the on-chip bus write access request includes: valid data; obtain configuration information of the package header; package the valid data into a first Ethernet according to the configuration information of the package header packet, and send the first Ethernet packet; wherein, the first Ethernet packet includes: an encapsulation header and valid data.

The third chip 602 is configured to receive the first Ethernet packet, write the first Ethernet packet into a randomly assigned address in the memory, classify the first Ethernet packet and enqueue it into a queue designated by the central processing unit.

In some exemplary embodiments, the on-chip bus write access request may be initiated by any other data processing module (for example, the aforementioned SUBSYS) in the first chip after processing the data, and the valid data is the The data is obtained after the data is processed and needs to be transmitted to the second chip. That is to say, the first chip 601 is further configured to: perform corresponding processing on the data to obtain valid data, and initiate an on-chip bus write access request.

It should be noted that, after processing the data, the first chip 601 generally initiates multiple on-chip bus write access requests for the processed data, that is to say, the valid on-chip bus write access request initiated each time is valid. The data is only a small part of the processed data. The first chip 601 can periodically initiate an on-chip bus write access request. After receiving the on-chip bus write access request, if it is too late to process the on-chip bus write access request, it can temporarily store the on-chip bus write access request to the first chip. 601 in RAM. Since the valid data in the on-chip bus write access request is only a small part of the processed data, temporarily storing the on-chip bus write access request in the RAM of the first chip 601 does not take up too much storage Space, that is, there is no need to reserve too much storage space for data transmission.

It should be noted that the size of the valid data in each on-chip bus write access request initiated can be arbitrarily set according to the actual situation. Generally, it can be set to be equal to the bit width of the bus connecting the data processing module 404 and the Ethernet sending module. integer multiples.

It should be noted that, with the development of technology, if other types of buses are used for the on-chip interconnection, the data processing module 404 and the Ethernet sending module may also be connected through other types of buses. The embodiment of the present disclosure does not limit what type of bus is used to connect the data processing module 404 and the Ethernet sending module, and the specific bus type is not used to limit the protection scope of the embodiment of the present disclosure.

In some other exemplary embodiments, the on-chip bus write access request includes: valid data, valid data length and access address.

In some exemplary embodiments, the encapsulation header includes at least one of the following: an Ethernet header, an IP header, a UDP header, and a TCP header.

In some exemplary embodiments, the IP may be IPV4 or IPV6.

In some exemplary implementations, if the first chip does not include the first switching module, nor does the first chip and the third chip include a switching chip, the first chip 601 is configured to implement sending the first Ethernet in the following manner Net packet: send the first Ethernet packet to the MAC layer, the MAC layer obtains the second Ethernet packet after corresponding processing of the Ethernet packet, and sends the second Ethernet packet through the first Ethernet transmission interface of the first chip to the third chip. In this manner, the reason why a switch chip or a switch module is not needed to realize the transmission of the first Ethernet packet is for the case of point-to-point data transmission with a simple topology.

In some other exemplary embodiments, if the first chip includes a first switch module and no switch chip is included between the first chip and the third chip, the first chip 601 is configured to implement sending the first Ethernet in the following manner Packet: send the first Ethernet packet to the first switching module of the first chip, the first switching module of the first chip sends the first Ethernet packet to the MAC layer, and the MAC layer performs corresponding processing on the first Ethernet packet Then, the second Ethernet packet is obtained, and the second Ethernet packet is sent to the third chip through the first Ethernet transmission interface of the first chip.

In other exemplary implementations, the data transmission system according to this embodiment further includes an exchange chip 603 located between the first chip and the third chip. In this case, the first chip 601 does not include the first switching module, and the first chip 601 is configured to implement the sending of the first Ethernet packet in the following manner: the first Ethernet packet is sent to the MAC layer, and the MAC layer pairs After the Ethernet packet is processed correspondingly, a second Ethernet packet is obtained, and the second Ethernet packet is sent to the switching chip 603 through the first Ethernet transmission interface of the first chip.

Switch chip 603 is configured to send the second Ethernet packet to the third chip.

In the data transmission system provided by the embodiments of the present disclosure, when valid data needs to be sent, the valid data is directly encapsulated into a first Ethernet packet and sent out, without first writing the valid data into a double rate (DDR, Double Data Packet). Rate), effectively reducing the bandwidth of DDR; no CPU participation is required in the process of transmitting valid data, that is, no additional CPU core resources are occupied; thus reducing the complexity of chip design and effectively reducing the area and power of the chip. consumption, which reduces the cost of the chip.

Referring to FIG. 7 , another embodiment of the present disclosure provides a data transmission system including a first chip 601 and a second chip 701 .

The first chip 601 is configured to receive an on-chip bus write access request; wherein, the on-chip bus write access request includes: valid data, valid data length and access address; obtain configuration information of the package header; The data is encapsulated into a first Ethernet packet, and the first Ethernet packet is sent; wherein, the first Ethernet packet includes: an encapsulation header and valid data; the encapsulation header includes: a custom header, and the custom header includes: valid data length and access address.

The second chip 701 is configured to receive a first Ethernet packet; wherein the first Ethernet packet includes: an encapsulation header and valid data; when the encapsulation header includes: a custom header, and the custom header includes: an effective data length and an access address , obtain the valid data length and the access address from the first Ethernet packet; obtain valid data from the first Ethernet packet according to the valid data length, and write the obtained valid data into the access address.

In some exemplary embodiments, the write access request may be initiated by any other data processing module (for example, the aforementioned SUBSYS) in the first chip after processing the data, and valid data is the processing of the data. After that, the data that needs to be transmitted to the second chip is obtained. That is to say, the first chip 601 is further configured to: perform corresponding processing on the data to obtain valid data, and initiate a write access request.

It should be noted that, after processing the data, the first chip 601 generally initiates multiple on-chip bus write access requests for the processed data, that is to say, the valid on-chip bus write access request initiated each time is valid. The data is only a small part of the processed data. The first chip 601 can periodically initiate an on-chip bus write access request. After receiving the on-chip bus write access request, if it is too late to process the on-chip bus write access request, it can The on-chip bus write access request is temporarily stored in the RAM of the first chip 601. Since the valid data in the on-chip bus write access request is only a small part of the processed data, the on-chip bus write access request is Temporarily storing in the RAM of the first chip 601 does not take up too much storage space, that is, it does not need to reserve too much storage space for data transmission.

In some exemplary embodiments, the IP may be IPV4 or IPV6.

Specifically, if the custom header is carried on L2, the format of the encapsulation header is: Ethernet header + custom header; then, the configuration information of the encapsulation header includes: configuration information of the Ethernet header and configuration information of the custom header;

If the custom header is carried at L3, the format of the encapsulation header is: Ethernet header + IP header + custom header; then, the configuration information of the encapsulation header includes: configuration information of the Ethernet header, configuration information of the IP header, and custom header header configuration information;

In some exemplary embodiments, the first chip 601 is configured to implement the encapsulation of valid data into a first Ethernet packet according to the configuration information of the encapsulation header in the following manner: selecting an Ethernet packet for encapsulating the first Ethernet packet according to an access address At least one of the network header, IP header, UDP header or TCP header, and at least one of the selected Ethernet header, IP header, UDP header or TCP header and the custom header, and the valid data are encapsulated into the first Ethernet header Net package.

In some exemplary embodiments, the first chip 601 is configured to select at least one of an Ethernet header, an IP header, a UDP header or a TCP header for encapsulating the first Ethernet packet according to the access address in the following manner: In the preset correspondence between at least one of the Ethernet header, IP header, UDP header, or TCP header used to encapsulate the first Ethernet packet and the address range, search for the address corresponding to the address range where the access address is located. At least one of an Ethernet header, an IP header, a UDP header, or a TCP header for encapsulating the first Ethernet packet.

In some exemplary embodiments, if the first chip does not include the first switch module, and neither does the first chip and the second chip include a switch chip, the first chip 601 is configured to implement sending the first Ethernet in the following manner Net packet: send the first Ethernet packet to the MAC layer, the MAC layer obtains the second Ethernet packet after corresponding processing of the Ethernet packet, and sends the second Ethernet packet through the first Ethernet transmission interface of the first chip to the second chip. In this manner, the reason why a switch chip or a switch module is not needed to realize the transmission of the first Ethernet packet is for the case of point-to-point data transmission with a simple topology.

In some other exemplary embodiments, if the first chip includes a first switch module and no switch chip is included between the first chip and the second chip, the first chip 601 is configured to implement sending the first Ethernet in the following manner Packet: send the first Ethernet packet to the first switching module of the first chip, the first switching module of the first chip sends the first Ethernet packet to the MAC layer, and the MAC layer performs corresponding processing on the first Ethernet packet Then, the second Ethernet packet is obtained, and the second Ethernet packet is sent to the second chip through the first Ethernet transmission interface of the first chip.

In other exemplary embodiments, the data transmission system according to this embodiment further includes a switch chip 603 located between the first chip 601 and the second chip 701 . In this case, the first chip 601 does not include the first switching module, and the first chip 601 is configured to implement the sending of the first Ethernet packet in the following manner: sending the first Ethernet packet to the MAC layer, and the MAC layer to After the Ethernet packet is processed correspondingly, a second Ethernet packet is obtained, and the second Ethernet packet is sent to the switching chip 603 through the first Ethernet transmission interface of the first chip.

The switch chip 603 is configured to send the second Ethernet packet to the second chip for the second Ethernet packet.

In some exemplary embodiments, after the second chip 701 receives the first Ethernet packet, if the second chip 701 is too late to process the first Ethernet packet, the first Ethernet packet may be temporarily stored to the second chip 701 in the RAM.

In some exemplary embodiments, when the encapsulation header does not include the custom header, the second chip 701 may directly discard the received first Ethernet packet.

In some exemplary embodiments, the second chip 701 is further configured to: obtain position offset information of the custom header in the first Ethernet packet, and obtain valid data from the first Ethernet packet according to the position offset information length and access address. Specifically, the second chip 701 can obtain the custom header from the first Ethernet packet according to the position offset information, and obtain the effective length and the access address from the custom header.

In the data transmission system provided by the embodiments of the present disclosure, when valid data needs to be sent, the valid data is directly encapsulated into a first Ethernet packet and sent out, without first writing the valid data into a double rate (DDR, Double Data Packet). Rate), effectively reducing the bandwidth of DDR; no CPU participation is required in the process of transmitting valid data, that is, no additional CPU core resources are occupied; thus reducing the complexity of chip design and effectively reducing the area and power of the chip. consumption, which reduces the cost of the chip. When the first Ethernet packet is received, valid data is directly obtained from the first Ethernet packet and written into the corresponding access address, without the need to parse and classify the first Ethernet packet, and the implementation logic is relatively simple, thereby reducing the cost of The complexity of chip design is reduced, the area and power consumption of the chip are effectively reduced, and the cost of the chip is also reduced.

Another embodiment of the present disclosure provides a computer-readable medium, where a computer program is stored in the computer-readable medium, and the computer program is used to execute any one of the foregoing data transmission methods.

Another embodiment of the present disclosure provides a chip, where the chip includes a CPU and a computer-readable medium, where the computer-readable medium stores a computer program, and the computer program executes any one of the above data transmission methods when executed by the CPU.

Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, functional modules/units in the system, and the apparatus can be implemented as computer programs, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components Components execute cooperatively. Some or all of the physical components may be implemented as hardware, or as circuits, such as application specific integrated circuits. In particular, unless otherwise indicated or contradicted, the systems, subsystems, chips, modules, sub-modules disclosed above may all be implemented as circuits, such as integrated circuits. The computer program described above may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As is known to those of ordinary skill in the art, the term computer storage media includes both volatile and nonvolatile implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data flexible, removable and non-removable media. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage, or may Any other medium that stores the desired information and can be accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery media, as is well known to those of ordinary skill in the art .

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should only be construed in a general descriptive sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics and/or elements described in connection with a particular embodiment/implementation may be used alone or in combination with other embodiments/implementations unless expressly stated otherwise. Features, characteristics and/or elements described in combination are used in combination. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

A data transmission method applied to a first chip, the method comprising:

Receive an on-chip bus write access request; wherein, the on-chip bus write access request includes: valid data;

Get configuration information for the wrapper header; and

The valid data is encapsulated into a first Ethernet packet according to the configuration information of the encapsulation header, and the first Ethernet packet is sent; wherein the first Ethernet packet includes: the encapsulation header and the valid data data.
The data transmission method according to claim 1, wherein the on-chip bus write access request further comprises: an access address and a valid data length; wherein, the access address is the address of the valid data in the memory of the second chip address;

The encapsulation header includes: a custom header, and the custom header includes: the effective data length and the access address.
The data transmission method according to claim 2, wherein the custom header further comprises: a reserved field.
The data transmission method according to claim 2, wherein the encapsulation header further comprises at least one of the following:

Ethernet header, Internet Protocol header, User Datagram Protocol header, Transmission Control Protocol header.
A data transmission method applied to a second chip, the method comprising:

receiving a first Ethernet packet; wherein, the first Ethernet packet includes: an encapsulation header and valid data;

When the encapsulation header includes: a custom header, and the custom header includes: an effective data length and an access address, the effective data length and the access address are obtained from the first Ethernet packet; wherein, The access address is the address of the valid data in the memory of the second chip; and

The valid data is obtained from the first Ethernet packet according to the valid data length, and the obtained valid data is written into the access address.
The data transmission method according to claim 5, wherein, before the step of obtaining the effective data length and the access address from the first Ethernet packet, the method further comprises: obtaining the user-defined header in the first Ethernet packet. position offset information in the Ethernet packet; and

The step of acquiring the effective data length and the access address from the first Ethernet packet includes: acquiring the effective data length and the access address from the first Ethernet packet according to the position offset information.
A chip, comprising: at least one Ethernet transmission module; each of the Ethernet transmission modules includes: an on-chip bus write access request receiving submodule, a configuration information acquiring submodule, and an Ethernet packet encapsulation sending submodule;

Wherein, the on-chip bus write access request receiving sub-module is configured to receive the on-chip bus write access request; wherein, the on-chip bus write access request includes: valid data;

The configuration information obtaining submodule is configured to obtain configuration information of the encapsulation header; and

The Ethernet packet encapsulation and sending submodule is configured to encapsulate the valid data into a first Ethernet packet according to the configuration information of the encapsulation header, and send the first Ethernet packet; wherein the first Ethernet packet is The net packet includes: the encapsulation header and the valid data.
The chip according to claim 7, wherein the on-chip bus write access request further comprises: an access address and a valid data length; wherein, the access address is an address of the valid data in the memory of the second chip;

The encapsulation header includes: a custom header, and the custom header includes: the effective data length and the access address.
A chip, comprising: at least one Ethernet receiving module; each of the Ethernet receiving modules includes: an Ethernet packet receiving submodule and a data writing submodule;

Wherein, the Ethernet packet receiving submodule is configured to receive the first Ethernet packet; Wherein, the first Ethernet packet includes: an encapsulation header and valid data;

The data writing submodule is configured to:

When the encapsulation header includes: a custom header, and the custom header includes: an effective data length and an access address, the effective data length and the access address are obtained from the first Ethernet packet; wherein, The access address is the address of the valid data in the memory of the second chip; and

Obtain valid data from the first Ethernet packet according to the valid data length, and write the obtained valid data into the access address.
The chip according to claim 9, wherein the Ethernet receiving module further comprises: a position offset information acquisition sub-module;

The position offset information obtaining submodule is configured to obtain the position offset information of the custom header in the first Ethernet packet;

The data writing submodule is configured to acquire the effective data length and the access address from the first Ethernet packet according to the position offset information.
A chip, comprising: at least one Ethernet sending module according to any one of claims 7-8, and at least one Ethernet receiving module according to any one of claims 9-10.
A data transmission system comprising:

The first chip, which is configured to:

Receive an on-chip bus write access request; wherein, the on-chip bus write access request includes: valid data;

obtain configuration information for the encapsulation header; and

The valid data is encapsulated into a first Ethernet packet according to the configuration information of the encapsulation header, and the first Ethernet packet is sent; wherein the first Ethernet packet includes: the encapsulation header and the valid data data; and

The third chip, which is configured to:

Receive the first Ethernet packet, write the first Ethernet packet into a randomly assigned address in the memory, classify the first Ethernet packet and enqueue it into a queue designated by the central processing unit.
A data transmission system comprising:

The first chip, which is configured to:

Receive an on-chip bus write access request; wherein, the on-chip bus write access request includes: valid data, valid data length and access address; wherein, the access address is the address of the valid data in the memory of the second chip ;

obtain configuration information for the encapsulation header; and

The valid data is encapsulated into a first Ethernet packet according to the configuration information of the encapsulation header, and the first Ethernet packet is sent; wherein the first Ethernet packet includes: the encapsulation header and the valid data data; the encapsulation header includes: a custom header, and the custom header includes: the effective data length and the access address; and

The second chip, which is configured to:

receive the first Ethernet packet;

obtain the effective data length and the access address from the first Ethernet packet; and

Obtain valid data from the first Ethernet packet according to the valid data length, and write the obtained valid data into the access address.
A computer-readable medium storing a computer program for executing the data transmission method according to any one of claims 1-6.
A chip comprising a CPU and a computer-readable medium, the computer-readable medium storing a computer program, the computer program executing the data transmission according to any one of claims 1-6 when executed by the CPU method.