CN100393060C

CN100393060C - Data communication method for device interior

Info

Publication number: CN100393060C
Application number: CNB200510058896XA
Authority: CN
Inventors: 刘友义; 杨源新
Original assignee: ZTE Corp
Current assignee: State Grid Shanghai Electric Power Co Ltd
Priority date: 2005-04-01
Filing date: 2005-04-01
Publication date: 2008-06-04
Anticipated expiration: 2025-04-01
Also published as: CN1842045A

Abstract

The present invention discloses a data communication method in a device, which provides the connection of different communicating interface circuits between a function unit and an exchange center unit, wherein when a processor of the function unit is not provided with a standard ethernet MII interface, the function unit is connected with the exchange center unit through a bus interface type communication interface circuit; when the processor of the function unit is provided with a standard ethernet MII interface standard, the function unit is connected with the exchange center unit through an MII interface type communication interface circuit; the transmission and the reception of signals between the function unit and the exchange center unit is transmitted by low voltage differential signals. The method of the present invention simplifies the communication topological structure of each unit of the whole machine, and reduces the complicated degree of integration communication software and total cost.

Description

A kind of data communication method of device interior

Technical field

The present invention relates to a kind of ethernet frame format data communication field, refer more particularly to the means of communication between each functional unit in the frame of complication system equipment.

Background technology

Ethernet technology is since nineteen ninety, the 10base-T standard was formally passed through, because its opening, simple in structure, algorithm are succinct, favorable compatibility and level and smooth upgrade function, and As time goes on and significantly transmission bandwidth is also promoting, not only obtain the dominance in the local area network (LAN) field, its territory also expands to metropolitan area network and wide area network scope.Wherein the switching Ethernet product is tens of times of single port owing to its total transmission bandwidth, and does not also have the media contention problem between each port, and under the heavy duty use occasion, overall performance is more outstanding.

In complex apparatus, in order to finish specific task, need each functional unit collaborative work, for collaborative work, between each unit unimpeded service channel must be arranged.According to present existing multinode mechanics of communication, take all factors into consideration transmission bandwidth and cost and technical sophistication degree, switching Ethernet 10base-T/100BASE-TX is a best choice, this technology not only bandwidth is big, adopt star topology, favorable expandability, and can realize communication between any 2 and do not disturb other unit.Therefore, switching Ethernet is widely used in the complicated communication apparatus.

According to the IEEE802.3 standard, between the 10base-T of standard/100BASE-TX Ethernet system physical layer and the data link layer, having adopted MII is Media Independent Interface, physical layer, then adopted CSMA/CD (Carrier Sense MultipleAccess with Collision Detection, the Carrier Sense Multiple Access of band collision detection), this is one of characteristic of ethernet technology, adopt this mechanism, make a plurality of ethernet stations can share one section media, but when designing apparatus internal communication scheme, the Ethernet structure 10base-T/100BASE-TX of standard uses in the communication apparatus of complexity and has following problem:

Problem one: as Ethernet switching center unit, each port of switching center all needs to use a pulse transformer and corresponding matching network circuit, sometimes the switching center unit is because of PCB (Printed Circuit Board, circuit printing plate) reason of usable area often can't layout, have to have to take the second best, arrange a veneer in addition, increased the complexity of backboard, increased overall cost.

Problem two: the Ethernet of each port uses the MII interface of standard in processor one side, for the simple veneer of some functions, because of only making single-chip microcomputer or cheap processor not possess this interface, can't pass through the communication of ether switching network, have to set up RS485 in addition or RS232 comes communication, cause two or three topological structures such as occurring chain 485 communication structures, star-like Ethernet structure or star-like dual port RAM communication structure in the whole set equipment and deposit, so not only increased overall communication complexity and cost, and communication efficiency is also reduced greatly.

Summary of the invention

The objective of the invention is to require too much in order to overcome in the prior art standard ethernet technology physical layer configurations, the interface of physical layer and MAC (MAC controller) layer is unfavorable for the shortcoming that is connected with ordinary processor, it is too much to solve the physical layer device that exists in the prior art, it is big to take up room, and there is the problem of multiple communication structure in whole set equipment, and proposes a kind of data communication method of device interior.

In order to realize the foregoing invention purpose, the data communication method of a kind of device interior that the present invention proposes comprises that step is as follows:

Step 1, structure is the hub-and-spoke configuration of core with the switching center unit between each functional unit and switching center unit, carries out both-way communication by the switching center unit between the functional unit;

Step 2, according to the difference of the processor type of functional unit, between functional unit and switching center unit, provide different communication interface circuit to connect:

When the processor of functional unit does not have standard ethernet MII interface, this functional unit is connected with the switching center unit by bus interface shape of the mouth as one speaks communication interface circuit;

When the processor of functional unit has standard ethernet MII interface standard, this functional unit is connected with the switching center unit by MII interface type communication interface circuit;

Step 3, use Low Voltage Differential Signal transmission the carrying out transmitting-receiving of signal between functional unit and switching center unit.

Adopt method of the present invention, when the device interior communication, an ethernet segment is monopolized in each unit, adopt the full duplex exchanged form, signal transmitting and receiving has adopted LVDS (Low Voltage Differential Signaling, the Low Voltage Differential Signal transmission), do not need complicated modulation and simulation matching network, the ethernet signal of standard, do not need modulation and simulation matching network like this, simplified physical layer circuit, and no matter whether the processor that makes functional unit use possess Ethernet MII interface, all can be linked into the Ethernet switched circuit, thereby simplify the topological structure of each unit communications of complete machine, reduce the complexity of whole bitcom, and reduced cost on the whole.

Description of drawings

The whole communication topology diagram of Fig. 1;

Fig. 2 bus interface shape of the mouth as one speaks communication interface circuit diagram;

Fig. 3 MII interface type communication interface circuit diagram;

Fig. 4 bus interface shape of the mouth as one speaks data send the buffering control chart;

Figure is handled in Fig. 5 bus interface shape of the mouth as one speaks frame data packing and transmission;

Fig. 6 bus interface shape of the mouth as one speaks Data Receiving buffering control chart;

Fig. 7 bus interface shape of the mouth as one speaks frame receives handles figure;

Fig. 8 MII interface type communication interface circuit frame sends handles figure;

Fig. 9 MII interface type communication interface circuit frame receives handles figure.

Embodiment

Fig. 1 is whole communication topological structure, and each functional unit and Ethernet crosspoint constitute a star network, and wherein the Ethernet crosspoint is the center.

Fig. 2 is a kind of bus interface shape of the mouth as one speaks communication interface circuit, this circuit model is suitable for the MII interface that the sort of processor does not have standard, perhaps MII interface quantity is not enough but need the unit of expansion Ethernet interface, this kind interface, processor is to finish by the read and write access of bus for the transmitting-receiving of ethernet data frame.

Fig. 3 is a MII interface type communication interface circuit, and this circuit model is suitable for the unit that the sort of processor has the MII interface of standard.This kind interface, processor are by finishing with the Communication processor communication of inside for the transmitting-receiving of ethernet data frame.

Referring to accompanying drawing 2, bus interface shape of the mouth as one speaks data communication circuit is made up of following circuit module: bus-type data transmit-receive buffering control module 22, and tranmitting data register 23, frame packing and transmission processing module 24, and frame extracts checking treatment module 25 compositions.Processor is written to the data that will send in the transmission buffering area of bus-type data transmit-receive buffering control module 22, start then and send, then frame packing and transmission processing module 24 are finished the encapsulation of data, data after the encapsulation are successively passed through 4B/5B conversion and parallel/serial conversion, convert the LVDS signal at last to and send to the switching center unit.After one frame sends, send an interruption, notification processor by the bottom control circuit to processor immediately.This interrupt identification is eliminated when processor is write arbitrary buffer data.

The switching center unit carries out the LVDS level translation to data earlier, after converting the LVDS signal to, extract the overall process of 25 process frames extractions of checking treatment module and CRC check through frame after, the reception buffering area of the frame signal content write bus type transmitting-receiving buffering control module of extracting 22, read at any time for processor.After the reception buffering area has been write these contents, send an interruption, notification processor by the bottom control circuit to processor immediately.This interrupt identification is eliminated when processor is read buffer data.

Referring to accompanying drawing 3, MII interface type communication interface circuit is made up of following circuit module: frame sends processing module and frame extraction module, because the MII interface of standard, packet sends to the MII interface, be complete packet (comprising the CRC check sign indicating number) and frame period and bell idles, the data that processor sends are through the 4B/5B code conversion, be converted to the LVDS signal after parallel/serial conversion and the LVDS level translation and send to the switching center unit, the data that send from the switching center unit are then successively carried out LVDS level translation/clock and data recovery (CDR), serial/parallel conversion, the 5B/4B code conversion sends to processor to data after the Frame BORDER PROCESSING.These conversion all are the conversion process of physical layer, and CRC check part and frame data extract part, are then finished by processor correlation function external interface and algorithm.

Frame structure with structure 100BASE-TX is an example, at first the concrete structure of bus interface shape of the mouth as one speaks data communication circuit is done detailed being described below:

Bus interface shape of the mouth as one speaks data send the buffering control module: referring to accompanying drawing 4, the core of described module is mouthful wide dual port RAM circuit 41 of not waiting of unidirectional delivery data, its readout window width is 4, and the processor interface sidelights on are gone into width and are as the criterion with the actual bus width of processor.Processor is with the external bus WriteMode, the destination address of ethernet data frame, source address, length/type field and data and fill PAD and be written to dual port RAM, write a frame after, start and send, read to allow signal by sending time slots control submodule 42 in the reasonable time generation, by " reading the address, read signal " module 43, in conjunction with clock, produce the address of reading of dual port RAM, read control signal is read data.5 frequency division modules 44 are used for the 125M clock of input is carried out 5 frequency divisions, produce 4 parallel port readout clocks of 25M.

Bus interface shape of the mouth as one speaks frame data packing and transmission processing module: generate submodule 51 by " lead code/initial code/end code/bell idles " referring to Fig. 5, parallel/serial transformation submodule 52, the CRC check sign indicating number produces

submodule

53,4B/5B transformation submodule 54, parallel/serial translation circuit submodule 55 and LVDS level translation submodule 56 are formed.After the data of transmission buffer had been write, processor sent " start and send " signal.At first, " lead code/initial code/end code/bell idles " generates submodule 51 7 lead byte sign indicating numbers of form transmission with the frequency 5-BIT width of 25M, and then transmitter start code (TSC) sends to parallel/serial translation circuit submodule 55; Then, export through dividing two-way after parallel/serial transformation submodule 52 conversion by 4 parallel-by-bit data of dual port RAM 41 outputs; One circuit-switched data still sends to 4B/5B transformation submodule 54 with the form of 4 bit widths; Another circuit-switched data sends to CRC check sign indicating number generation submodule 53 with the form of serial data, is used to generate the CRC check sign indicating number; In the content of reading dual port RAM 41, start the CRC check sign indicating number and produce submodule 53, produce 32 CRC check sign indicating number, and the content of dual port RAM 41 read finish after, the CRC check sign indicating number is sent to 4B/5B transformation submodule 54; CRC generates submodule 51 transmit frame end code and bell idles by " lead code/initial code/end code/bell idles " after sending and finishing again, thereby finishes the encapsulation process of a complete data frame.If there are not new data to send, then bell idles is sending always.Packaged frame carries out the 4B/5B conversion by 4B/5B transformation submodule 54, and the 5-BIT width data after the conversion carries out parallel/serial conversion by parallel/serial translation circuit submodule 55 again, at last serial data is carried out the LVDS conversion, outputs to backboard with the clock of 125M.

4B/5B coding used in the present invention is except that bell idles, and that all the other codings adopt is 802.3-2002, and the standard subclass (as follows) of clause 24 is as shown in table 1:

Table 1

5B encodes 43210

Title

MII interface (TXD3:0/RXD3:0) 3210

Explain

1 1 1 1 0	0	0 0 0 0	Data 0
1 1 1 1 0	0	0 0 0 0	Data 0	0 1 0 0 1	1	0 0 0 1	Data 1
1 0 1 0 0	2	0 0 1 0	Data 2	0 1 0 0 1	1	0 0 0 1	Data 1
1 0 1 0 0	2	0 0 1 0	Data 2	1 0 1 0 1	3	0 0 1 1	Data 3
0 1 0 1 0	4	0 1 0 0	Data 4	1 0 1 0 1	3	0 0 1 1	Data 3
0 1 0 1 0	4	0 1 0 0	Data 4	0 1 0 1 1	5	0 1 0 1	Data 5
0 1 1 1 0	6	0 1 1 0	Data 6	0 1 0 1 1	5	0 1 0 1	Data 5
0 1 1 1 0	6	0 1 1 0	Data 6	0 1 1 1 1	7	0 1 1 1	Data 7
1 0 0 1 0	8	1 0 0 0	Data 8	0 1 1 1 1	7	0 1 1 1	Data 7
1 0 0 1 0	8	1 0 0 0	Data 8	1 0 0 1 1	9	1 0 0 1	Data 9
1 0 1 1 0	A	1 0 1 0	Data A	1 0 0 1 1	9	1 0 0 1	Data 9
1 0 1 1 0	A	1 0 1 0	Data A	1 0 1 1 1	B	1 0 1 1	Data B
1 1 0 1 0	C	1 1 0 0	Data C	1 0 1 1 1	B	1 0 1 1	Data B
1 1 0 1 0	C	1 1 0 0	Data C	1 1 0 1 1	D	1 1 0 1	Data D
1 1 1 0 0	E	1 1 1 0	Data E	1 1 0 1 1	D	1 1 0 1	Data D
1 1 1 0 0	E	1 1 1 0	Data E	1 1 1 0 1	F	1 1 1 1	Data F
1 0 0 0 0	I 1	There is not definition	The bell idles part 1	1 1 1 0 1	F	1 1 1 1	Data F
1 0 0 0 0	I 1	There is not definition	The bell idles part 1	1 0 0 0 0	I2	There is not definition	The bell idles part 2
1 1 0 0 0	J	0 1 0 1	The lead code part 1	1 0 0 0 0	I2	There is not definition	The bell idles part 2
1 1 0 0 0	J	0 1 0 1	The lead code part 1	1 0 0 0 1	K	0 1 0 1	The lead code part 2
0 1 0 1 1	SFD1	0 1 0 1	The initial code part 1	1 0 0 0 1	K	0 1 0 1	The lead code part 2
0 1 0 1 1	SFD1	0 1 0 1	The initial code part 1	1 1 0 1 1	SFD2	1 1 0 1	The initial code part 2
0 1 1 0 1	T	There is not definition	Frame end sign indicating number part 1	1 1 0 1 1	SFD2	1 1 0 1	The initial code part 2
0 1 1 0 1	T	There is not definition	Frame end sign indicating number part 1	0 0 1 1 1	R	There is not definition	Frame end sign indicating number part 2

The CRC check sign indicating number adopts the CRC polynomial generator of 802.3 standards to generate, and this CRC multinomial is:

G(X)＝X ³²+X ²⁶+X ²³+X ²²+X ¹⁶+X ¹²+X ¹¹+X ¹⁰+X ⁸+X ⁷+X ⁵+X ⁴+X ²+X ¹+1；

Bus interface shape of the mouth as one speaks Data Receiving buffering control module: referring to Fig. 6, this module generates submodule 61 by write address and dual port RAM submodule 62 is formed.Write address generates submodule 61 after lower circuit receives effective ethernet data frame, at reasonable time, generates the dual port RAM write address.Dual port RAM submodule 62 is mouthful wide dual port RAMs of not waiting of unidirectional delivery data, and it writes the inlet width is 4, and the processor interface side is read width and is as the criterion with the actual bus width of processor.After lower floor's circuit is received a frame, an interrupt signal will be arranged.Processor is read mode with external bus, the total length of ethernet data frame, CRC check destination address, source address, the length/type field of sign, ethernet data frame as a result, read from dual port RAM with data and filling PAD, write address generation module 61 is carried out the 1st the removing interrupt signal that reads instruction at processor, it is short as far as possible that program should guarantee once to run through the whole time that receives Frame, to guarantee the integrality of Ether frame.

Bus interface shape of the mouth as one speaks frame receiving processing module: referring to shown in Figure 7, by CDR (clock and data recovery circuit)

submodule

71,5 frequency division submodules 72, parallel/serial transformation submodule 73, the CRC check sign indicating number produces submodule 74, " frame head/postamble identification " submodule 75, frame extracts submodule 76, serial/

parallel transformation submodule

77,5B/4B transformation submodule 78, CRC comparison sub-module 79 and frame length counting submodule 710 are formed.Wherein CDR submodule 71 is used for from data and the clock signal of the next LVDS signal regeneration 125M of backboard.The 125M clock signal frequency division that 5 frequency division submodules 72 are used for circuit is recovered is the clock signal of 25M, uses for inner parallel processing." frame head/postamble identification " submodule 75 is used for the data characteristics according to signal code stream, produces frame signal and begins and the frame signal useful signal.Frame extracts submodule 76 and is used to extract the serial code stream of Ether frame till from destination address to the CRC check sign indicating number.Serial/parallel transformation submodule 77 is carried out serial/parallel conversion to the serial data that frame extracts submodule 76, becomes the parallel data of 5B width.78 of 5B/4B transformation submodule are according to the table of comparisons shown in the table 1, parallel data is transformed into the data of 4B width, be written on the one hand and receive the buffering dual port RAM, carry out parallel/serial conversion by parallel/serial transformation submodule 73 once more on the other hand, the data of serial produce submodule 74 by the CRC check sign indicating number and produce the CRC check sign indicating number.The CRC check sign indicating number of this generation compares by CRC comparison sub-module 79 and the CRC check sign indicating number that receives, and according to the result of contrast, it is in 2 the byte that the CRC check result is represented to write the constant offset amount that receives buffer cell.710 bases of frame length counting submodule " frame head/postamble identification " signal that submodule 75 produces calculates the length that receives frame, and this length data is write the constant offset amount that receives buffer cell is in 0 the byte.The generation algorithm of CRC check sign indicating number is identical with above-mentioned process of transmitting.

To be example form module to each of MII interface type data communication circuit is described in detail with the frame structure of structure 100BASE-TX:

MII interface type communication interface circuit frame sends processing module: referring to Fig. 8, this module is by 4B/5B transformation submodule 81, parallel/serial transformation submodule 82, and LVDS level-

conversion circuit

83,5 frequency division submodules 84 are formed.4B/5B transformation submodule 81 becomes the 5B coding to 4 parallel-by-bit data conversions from the MII interface, and transformation rule is as shown in table 1.82 of the parallel/serial transformation submodule data after the 5B coding send with the multirate serial of 125MHz.

MII interface type communication interface circuit frame receiving processing module: referring to Fig. 9, this module is by

CDR submodule

91,5 frequency division submodules 92, " frame head/postamble identification " submodule 93, frame extracts submodule 94, and serial/

parallel transformation submodule

95 and 5B/4B transformation submodule 96 are formed.CDR submodule 91 is data and the clock of the next LVDS signal flow regeneration 125MHz of circuit, and generation CRS signal.5 frequency division submodules 92 obtain RX_CLK to the line clock frequency division, " frame head/postamble identification " 93 processing of submodule obtain the RX_DV signal, frame extracts 94 of submodules and extracts complete ether initial code and complete Ether frame, serial/parallel transformation submodule 95 is carried out serial/parallel conversion to the 5B of circuit coding, become the parallel data of 5-BIT width, output to 5B/4B transformation submodule 96 then and carry out the reduction of 4B coding, transformation rule is as shown in table 1.Obtain the RXD3:0 signal of MII interface.

The treatment step of software section is as follows: MAC Address adopts the mode of local effective address, is about to second of address and fixedly is changed to 1.Adopting under the local situation about setting, the present invention adopts after every module unit plate powers on, and processor comes by certain algorithm according to the machine frame/groove position signal that obtains from backboard, can be created on unique MAC Address in the system, be used for the ethernet communication between plate.For the network address on upper strata more, for example the IP address used of the corresponding communication of veneer then adopts the mode of DHCP to obtain, also can be with the similarly groove position information binding of mode and veneer.

The present invention changes at the physical layer below the MII interface of 802.3100BASE-TX standard, to upper-layer protocol is fully transparent, and regulation TYPE 1 mode is fully feasible in the 802.2LLC agreement so the interface of network layer still adopted.The flow control aspect according to 802.3 standard appendix 31B, need flow into the unit of control, can after whenever receiving a frame or number frame data, send a PAUSE frame according to the performance of handling.The time span of suspending then is written to the request_operand field of PAUSE frame.Every veneer externally sends before the information, and whether need to analyze the transmission target has flow control request, if any, then the time of accusing according to the Shen, opposite end, postpones sending.If broadcasting or multicast, the originating party time delay is determined by the spacing value of maximum.

Data communication of the present invention is limited to the 2nd layer exchanges data, as long as the MAC Address of each functional unit does not repeat, just can finish the exchanges data of each unit by switching center.Because the bottom link has adopted the mode of 100M full duplex, make single-chip microcomputer or low performance processor and have the high-performance processor of MII interface when communication, introduce the mechanism of Flow Control at the disposal ability different needs, flow-control mechanism adopts 802.3 standard P AUSE frames, finishes in conjunction with each unit upper level applications.

Claims

1. the data communication method of a device interior is characterized in that, comprises the steps:

When the processor of functional unit has standard ethernet MII interface, this functional unit is connected with the switching center unit by MII interface type communication interface circuit;

Step 3, use Low Voltage Differential Signal LVDS transmission the carrying out transmitting-receiving of signal between functional unit and switching center unit.

2. the means of communication according to claim 1 is characterized in that, carry out the frame structure of the The data 100BASE-TX of communication; In the described step 2, when the processor of functional unit did not have standard ethernet MII interface, the communication step between this functional unit and switching center unit was as follows:

Bus interface shape of the mouth as one speaks communication interface circuit sends data:

A, processor are written to the data that will send in the transmission buffering area of bus-type data transmit-receive buffering control module (22);

B, processor send " start and send " signal, the frame packing is provided and sends the encapsulation that processing module (24) is finished data, and to the encapsulation after data carry out 4B/5B conversion, parallel/serial conversion and LVDS level conversion, convert the LVDS signal to and send to the switching center unit;

After C, a frame send, send an interrupt notification processor by the bottom control circuit to processor immediately, this interrupt identification is eliminated when processor is write arbitrary buffer data;

Bus interface shape of the mouth as one speaks circuit receives data:

After D, switching center unit become the LVDS signal to data transaction, extract the overall process that checking treatment module (25) is finished frame extraction and CRC check through frame;

E, the reception buffering area of the frame signal content write bus type data transmit-receive that extracts buffering control module (22), read at any time for processor;

F, after receiving buffering area and having write these contents, immediately by the bottom control circuit to interrupt notification processor of processor transmission, this interrupt identification is eliminated when processor is read buffer data.

3. method according to claim 2, it is characterized in that, in the described steps A, processor is the core that the PAD of the destination address of ethernet data frame, source address, length/type field and data and filling is written to bus-type data transmit-receive buffering control module (22) the dual port RAM storage in the mode of external bus.

4. method according to claim 2 is characterized in that, among the described step B, frame data packing and transmission are handled and comprised:

B1, " lead code/initial code/end code/bell idles " generation submodule (51) successively send lead code and initial code arrives parallel/serial translation circuit submodule (52);

B2, dual port RAM (41) output 4 parallel-by-bit data, one the tunnel outputs to 4B/5B transformation submodule (54) through parallel/serial translation circuit submodule (52) carries out conversion, another road sends to CRC check sign indicating number generation submodule (53) with the form of serial data, generates the CRC check sign indicating number;

B3, the content of dual port RAM (41) read finish after, the CRC check sign indicating number is sent to 4B/5B transformation submodule (54);

After B4, CRC sent and finish, " lead code/initial code/end code/bell idles " generated submodule (51) and sends end code and bell idles, thereby finished the encapsulation process of data;

B5, packaged frame is carried out 4B/5B conversion, parallel/serial conversion and LVDS level conversion, convert the LVDS signal to and send to the switching center unit.

5. method according to claim 2 is characterized in that, among the described step D, provides frame to extract the check processing module and finishes that frame extracts and the CRC check process comprises:

D1, provide clock and data recovery CDR module (71) will become data and the clock signal of 125M from the LVDS signal regeneration that backboard comes;

D2,5 frequency division submodules (72) are provided is the clock signal of 25M with 125M data and the clock signal frequency division that circuit recovers;

D3, provide " frame head/postamble identification " submodule (75) to produce frame signal to begin and the frame signal useful signal;

D4, provide frame to extract submodule (76) to extract the serial code stream of Ethernet data frames till from destination address to the CRC check sign indicating number;

D5, data that step D4 is extracted are by serial/parallel conversion, the 5B/4B conversion;

D6, the data after the step D5 conversion are carried out parallel/serial conversion,, produce the CRC check sign indicating number the input of the serial data after conversion CRC check submodule (74);

D7, the CRC check sign indicating number that step D6 is generated and the check code that receives compare by CRC comparison sub-module (79), and it is 2 byte that comparing result is put into the constant offset amount;

D8, the length that provides frame length counting submodule (710) to calculate the frame that receives, and length data is written to the reception buffer cell.

6. the means of communication according to claim 1 is characterized in that, carry out the frame structure of the The data 100BASE-TX of communication; In the described step 2, when the processor of functional unit had standard ethernet MII interface, the communication step of this functional unit and switching center unit was as follows:

G, processor are sent out interface by MII and are sent the data to frame transmission processing module, and frame sends processing module by the 4B/5B code conversion, and parallel/serial conversion becomes the LVDS signal data with the LVDS level translation with data transaction and sends out;

The data that H, switching center unit send are successively carried out the LVDS level translation, clock and data recovery, and serial/parallel conversion, the 5B/4B code conversion is received interface by MII after the Frame BORDER PROCESSING data is sent to processor.

7. the means of communication according to claim 6 is characterized in that, described step G comprises:

G1, provide 4B/5B transformation submodule (81), will become the 5B coding from 4 parallel-by-bit data conversions of MII interface;

G2, provide parallel/serial transformation submodule (82), the data transaction behind the 5B coding is become the multirate serial data of 125MHz;

G3, provide LVDS level-conversion circuit (83), the serial data that obtains among the step G2 is transformed to the LVDS signal sends to the switching center unit.

8. the means of communication according to claim 6 is characterized in that, described step H comprises:

H1, provide data and the clock of the LVDS signal flow regeneration 125MHz that CDR submodule (91) comes circuit, and produce the CRS signal;

H2, provide 5 frequency division submodules (92) that the line clock frequency division is obtained receive clock RX_CLK;

H3, provide " frame head/postamble identification " submodule (93) to handle to obtain receiving the effective RX_DV signal of data;

H4, provide frame to extract the extraction that submodule (94) carries out complete ether initial code and complete Ether frame;

H5, provide serial/parallel transformation submodule (95) that the 5B of circuit coding is carried out serial/parallel conversion, become the parallel data of 5-BIT width, output to 5B/4B transformation submodule (96) then and carry out the reduction of 4B coding, obtain the RXD3:0 signal of MII interface.