CN1254739C - 处理器和操作处理器的方法 - Google Patents
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- 238000012546 transfer Methods 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 28
- 239000000203 mixture Substances 0.000 claims description 12
- 230000008878 coupling Effects 0.000 claims description 9
- 238000010168 coupling process Methods 0.000 claims description 9
- 238000005859 coupling reaction Methods 0.000 claims description 9
- 238000000605 extraction Methods 0.000 claims 2
- 230000013011 mating Effects 0.000 claims 1
- 238000012545 processing Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 9
- 238000004891 communication Methods 0.000 description 3
- 239000000284 extract Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000002699 waste material Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- LHMQDVIHBXWNII-UHFFFAOYSA-N 3-amino-4-methoxy-n-phenylbenzamide Chemical compound C1=C(N)C(OC)=CC=C1C(=O)NC1=CC=CC=C1 LHMQDVIHBXWNII-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005755 formation reaction Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- QNXAVFXEJCPCJO-UHFFFAOYSA-N Diclosulam Chemical compound N=1N2C(OCC)=NC(F)=CC2=NC=1S(=O)(=O)NC1=C(Cl)C=CC=C1Cl QNXAVFXEJCPCJO-UHFFFAOYSA-N 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000003137 locomotive effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
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-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/321—Program or instruction counter, e.g. incrementing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Multimedia (AREA)
- Advance Control (AREA)
- Multi Processors (AREA)
- Executing Machine-Instructions (AREA)
- Debugging And Monitoring (AREA)
- Image Processing (AREA)
- Stored Programmes (AREA)
- Fittings On The Vehicle Exterior For Carrying Loads, And Devices For Holding Or Mounting Articles (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Control Of Transmission Device (AREA)
- Document Processing Apparatus (AREA)
- Harvester Elements (AREA)
Abstract
描述了诸如基于平行硬件的多线程处理器(12)之类的处理器。处理器(12)可以执行一条计算机指令，它就是转移指令，该转移指令基于指定字节等于或不等于寄存器(80，78，76b)中的字节，使处理器(12)中的指令序列确定寄存器(80，78，76b)中的字节是否等于或不等于包含在指令中的指定字节值，并执行由转移指令指定的转移操作。
Description
技术领域
本发明涉及转移指令。
背景技术
并行处理是在计算机处理中关于并发事件的信息处理的有效形式。并行处理要求在计算机处理中同时执行许多程序。顺序处理或串行处理使所有任务顺序地在单个工作站上执行，而流水线处理使任务在专用的工作站上执行。无论在并行处理机，流水线或顺序处理机上执行的计算机代码都涉及转移指令，其中指令流可以在一个序列中执行而从该序列转移到不同的指令序列。
发明内容
本发明提供了一种操作处理器的方法，它包括：基于寄存器中的一字节等于或不等于指定字节值，所述指定字节是否与该字节值匹配或不匹配，引导处理器从执行第一指令顺序系列转移到不同的指令顺序系列。
本发明还提供了一种处理器，包括：一寄存器堆；一与寄存器堆耦合的算术逻辑单元，以及存储转移指令的程序控制存储器，所述转移指令使处理器：提取存储在寄存器中的一字节；确定寄存器中的该字节是否等于或不等于包含在该指令中的指定的字节值；以及基于所述指定的字节等于或不等于寄存器中的该字节引导转移操作。
本发明还提供了一种操作处理器的方法，它包括：提取存储在寄存器中的一字节；确定寄存器中的该字节是否等于或不等于包含在指令中的指定的字节值；以及基于所述指定的字节等于或不等于寄存器中的该字节进行由所述指令指定的转移操作。
附图说明
图1是使用处理器的通信系统框图。
图2是处理器的详细框图。
图3是图1和2的处理器中使用的微引擎的方框图。
图4是微引擎中的流水线图。
图5是转移指令的示例格式。
图6是通用寄存器的方框图。
具体实施方式
参考图1，通信系统10包括一处理器12。在一个实施例中，处理器是基于硬件的多线程处理器12。处理器12与一总线，例如PCI总线14、存储系统16和第二总线耦合。系统10对于能分解成平行的子任务或功能的各种任务特别有用。具体说基于硬件的多线程处理器12对于基于带宽而不是基于执行时间的任务是有用的。基于硬件的多线程处理器12有多个微引擎22，每个都具有硬件控制的线程，它们能同时激活并独立地执行任务。
基于硬件的多线程处理器12还包括一中央控制器20，帮助用于基于多线程处理器12的其它资源的加载微代码控制和执行其它通用目的的计算机类型功能，例如处理协议，意外事件、数据包处理的额外支持，其中微引擎传送该数据包以用于更详细的处理，例如边界条件。在一个实施例中，处理器20是基于Strory ArmR (Arm是英国ARM有限公司的商标)的结构。通用微处理器20有一操作系统。通过操作系统微处理器20可调用在微引擎22a-22f上操作的功能。处理器20可使用任何支持的操作系统，较佳的是实时操作系统。对于按Strory Arm结构实现的核心处理器，可使用诸如因特网上可获得的Microsoft NT实时操作系统、VXMork和□CUS，自由件操作系统。
基于硬件的多线程处理器12还包括多个功能微引擎22a-22f。功能性微引擎(微引擎)22a-22f中的每个都保持有多个硬件方式的程序计数器和与程序计算器相关的状态。实际上，在每个微引擎22a-22f上可同时有相应的多组线程在活动，然而在任何时刻仅只有一个线程实际在工作。
微引擎22a-22f每个都有能力处理4个硬件线程。微引擎22a-22f与包括存储器系统16和总线接口24和28的共享资源一起工作。存储器系统16包括同步动态随机访问存储器(SDRAM)控制器26a和静态随机访问存储器(SRAM)控制器26b。SDRAM存储器16a和SRAM控制器26a典型地用于处理大容量数据，例如处理来自网络数据包的网络有效负荷。SRAM控制器26b和SRAM存储器16b用于例如网络数据包处理，后文本处理器，或作为存储子系统，即RAID磁盘存储的处理器，或用于核心处理器20的低等待，快访问任务，例如访问查找表，存储器，等等。
处理器12包括将处理器与第二总线18耦合的总线接口28。总线28在一个实施例中把处理器12耦合到所谓FBUS(FIFO总线)。处理器12包括一个第二接口，例如PCI总线接口24。它将驻存在PCI14总线上的其它系统元件耦合到处理器12。PCI总线接口24提供了一条到SDRAM存储器的高速数据通路24a。通过该通路数据可经直接存储器访问(DMA)传送器从SDRAM快速通过PCI总线14移动。
每个功能单元被耦合到一个或多个内部总线。内部总线是双32位总线(即一条总线用于读，另一条用于写)。基于硬件的多线程处理器还被构造成使得处理器12中的内部总线的带宽之和超过耦合到处理器12外部总线的带宽。处理器12包括一内部核心处理器总线32，例如ASB总线(Advanced SystemBus)，如下所述它将内部处理器核心20耦合到存储器控制器26a、26c和到一个ASB转移器30。ASB总线是所谓AMBA总线的一个子集，AMBA总线与StrongArm处理器核心一起使用。处理器12还包括一个将微引擎单元与SRAM控制器26b、ASB转换器30和FBUS接口28耦合的专用总线34。存储器总线38将存储器控制器26a、26b与总线接口24和28以及包括用于启动操作的快闪只读存储器16c的存储器系统16等耦合。
参考图2，每个微引擎22a-22f包括一仲裁器，它检查标志以确定要工作的可用线程。任何来自微引擎22a-22f的线程可访问SDRAM控制器26a，SDRAM控制器26b或FBUS接口28。存储器控制器26a和26b中的每个都包括多个队列以存储待执行的存储器引用请求。FBUS接口28支持由MAC装置支持的每个端口的发送和接收标志，以及指示何时保证服务的中断标志。FBUS接口28还包括执行来自FBUS18的进入数据包的标头处理。控制器28a提取数据包标头并在SRAM中执行微可编程源/目标/协议的散列查找(用于地址平滑)。
核心处理器20访问该共享资源。核心处理器20通过总线32与到总线接口24的SDRAM控制器26a和SRAM控制器26b直接通信。然而，为了访问微引擎22a-22f和位于任何一个微引擎22a-22f中的转移寄存器，核心处理器20经总线34上的ASB转换器30访问微引擎22a-22f。ASB转换器30可物理上驻留在FBUS接口28中，但逻辑上可不同。ASB转换器30执行在FBUS微引擎转移寄存器位置和核心处理器地址(即ASB总线)间的地址转换使得核心处理器20能访问属于微引擎22a-22f的寄存器。
虽然微引擎22可如下所述使用寄存器组交换数据，但还是提供一便笺式高速缓冲存储器27以允许微引擎写入数据到存储器以供其它微引擎读取。便笺式高速缓冲器存储器27耦合到总线34。
处理器核心20包括一由五级流水线实现的RISC核心50，在单个周期内执行一个操作数或二个操作数的单个周期移位，提供乘法支持和32位桶移位支持。这一RISC核心50是一标准Strong ArmR结构但出于性能理由它用五级流水线实现。处理器核心20还包括一16K字节的指令高速缓冲存储器52，一8K字节数据高速缓存储冲器54和一预提取流缓冲器56。核心处理器20与寄存器写和指令提取并行地执行算术操作。核心处理器20通过ARM定义的ASB总线与其它功能单元形成接口。ASB总线是32位双向总线32。
参照图3，一个示例微引擎22f包括一控制存储器70，它包括一个存储微程序的RAM。微程序可由核心处理器20加载。微引擎22f还包括控制器逻辑72。控制器逻辑包括一指令译码器73和程序计计数器(PC)单元72a-72d。四个微程序计数器72a-72d被保持在硬件中。微引擎22f还包括前后事件切换逻辑74。前后事件逻辑74接收来自每一个共享资源，例如SRAM26a，SRAM26b，或处理器IS20控制和状态寄存器等等的信息(例如，SEQ-#-EVENT-RESPONSE；FBI-EVENT-RESPONSE；SRAM-EVENT-RESPONSE；SDRAM-EVENT-RESPONSE；和ASB-EVENT-RESPONSE)。这些信息提供了关于请求的功能是否已完成的消息。基于由线程所请求的功能是否已完成和已发出完成信号，线程必须等待完成信号，并且如果线程被启动操作，则该线程被置于可用线程列表中(未示出)。微引擎22f最大可具有例如4个线程可供使用。
除了执行的线程是本地的事件信号外，微引擎22使用了全局的信号状态。使用信号状态，执行着的线程可以向所有微引擎22广播一信号状态。接收请求或可用信号、在微引擎中的任何或全部线程可根据这些信号状态转移。这些信号状态可用于确定资源的可供使用性或资源是否应该用于服务。
前后事件逻辑74为四个(4)线程仲裁。在一个实施例中，仲裁是一种轮流机制。其它技术也可使用，包括优先队列或加权公正队列。微引擎22f还包括一执行盒(EBOX)数据通路76，它包括一算术逻辑单元76a和通用目的寄存器76b。算术逻辑76a执行算术和逻辑功能以及移动功能。算术逻辑单元包括如下所述的由指令使用的条件码位。寄存器组76b具有相对大数目的通用寄存器，它们按如下所述被窗口化，使得它们能相对或绝对地被寻址。微引擎22f还包括一写转移器寄存器堆78和一读转移器寄存器堆80，这些寄存器也被窗口化使得它们能相对或绝对地被寻址。写转移器寄存器堆78是到资源的写数据所在地。类似地读转移器寄存器80是用于来自共享资源的返回数据。数据到达时或之后，来自各个共享资源，例如SRAM控制器26a，SDRAM控制器26b或核心处理器20的事件信号将被提供给前后事件仲裁器74，它随后将警示该线程数据可供使用或已被送出。两个转移寄存器组78和80通过数据通路与执行盒(EBOX)76相连。
参考图4，微引擎数据通路保持了一个5级微流水线82。这一流水线包括了微指令字82a的查找，寄存器文件地址82b的格式、从寄存器文件82c读取操作数、ALU、移位或比较操作82d、以及向寄存器82e写回结果。通过提供写回数据的旁通到ALU/移位器单元，并假设寄存器是用寄存器文件(而不是RAM)实现，微引擎可执行同步的寄存器文件读和写，这完全隐藏了写操作。
在微引擎22a-22f中被支持的指令集支持条件转移。最坏情况下的条件转移等待时间(不包括跳转)出现在转移判决是由先前微控制指令设定的条件码的结果时。等待时间如下表1所示：
表1
|1|2|3|4|5|6|7|8|
-----------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n2|XX|b1|b2|b3|b4|
寄存器地址生成 | |n1|cb|XX|XX|b1|b2|b3|
寄存器文件查找 | | |n1|cb|XX|XX|b1|b2|
ALU/shifter/cc | | | |n1|cb|XX|XX|b1|
写回 | | |m2| |n1|cb|XX|XX|
其中nx是预转移微字(n1设置cc‘s)，
cb是条件转移，
bx是后转移微字以及
XX是中止的微字。
如表1所示，直到周期4才设定条件码n1，并能作出转移判决(在这种情况下，使转移路经在周期5中被查找)。微引擎22f引起2个周期的转移延迟损失，因为在转移路经开始用操作b1填充流水管道前它必须终止流水管道中的操作n2和n3(直接在转移后的2个微字)。如果不采取该转移，无微字可被终止，执行将继续正常进行。微引擎具有若干机制来减小或消除有效的转移延迟等待。
微引擎支持可选的延期转移。可选的延期转移是在转移执行后并在转移生效之前微引擎允许1或2条微指令的时间(即转移生效被“延期”的时间)。因而，如果可找到有用的工作填入转移微字后浪费的周期中，则就可隐蔽转移延迟。1周延期转移示于下述表2中，其中允许在cb之后但在b1前执行n2：
表2
|1|2|3|4|5|6|7|8|
-------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n2|XX|b1|b2|b3|b4|
寄存器地址生成 | |n1|cb|n2|XX|b1|b2|b3|
寄存器文件查找 | | |n1|cb|n2|XX|b1|b2|
ALU/shifter/cc | | | |n1|cb|n2|XX|b1|
写回 | | | | |n1|cb|n2|XX|
2周延迟转移示于表3，其中在出现转移到b1之前，允许完成n2和n3。注意当条件码在转移前的微字中被设置时只允许有2周的转移延期。
表3
|1|2|3|4|5|6|7|8|9|
-------------------+----+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n2|n3|b1|b2|b3|b4|b5|
寄存器地址生成 | |n1|cb|n2|n3|b1|b2|b3|b4|
寄存器文件查找 | | |n1|cb|n2|n3|b1|b2|b3|
ALU/shifter/cc | | | |n1|cb|n2|n3|b1|b2|
写回 | | | | |n1|cb|n2|n3|b1|
微引擎还支持条件码的计算。如果作出转移判决所基于的条件码在转移前2个或多个微字前设定，则可消除1周的转移，因为如表4所示可提前1周作出转移判决。
表4
|1|2|3|4|5|6|7|8|
------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|n2|cb|XX|b1|b2|b3|b4|
寄存器地址生成 | |n1|n2|cb|XX|b1|b2|b3|
寄存器文件查找 | | |n1|n2|cb|XX|b1|b2|
ALU/shifter/cc | | | |n1|n2|cb|XX|b1|
写回 | | | | |n1|n2|cb|XX|
在此示例中，n1设置条件码而n2未设置条件码。因而，可在周期4作出转移判决(而不是5)以消除1个周期的转移延迟。在表5的示例中1周的转移延迟和提前设置条件码被组合来完成隐蔽转移延迟。亦即，条件码(cc)在1周延迟转移前2周被设置。
表5
|1|2|3|4|5|6|7|8|
--------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|n2|cb|n3|b1|b2|b3|b4|
寄存器地址生成 | |n1|n2|cb|n3|b1|b2|b3|
寄存器文件查找 | | |n1|n2|cb|n3|b1|b2|
ALU/shifter/cc | | | |n1|n2|cb|n3|b1|
写回 | | | | |n1|n2|cb|n3|
在条件码不能早设置的情况下(即将它们设置在先于转移的微字中)，微引擎支持转移推测，该推测试图将已暴露但仍保留的转移延迟减少一周。通过“推测”转移路经或顺序路经，微顺序器在它确定知道执行哪条路经前提前1周预先提取推测路经。如果推测正确，如表6所示1周的转移延迟被消除了。
表6
推测转移被采取/转移被采取
|1|2|3|4|5|6|7|8|
---------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n1|b1|b2|b3|b4|b5|
寄存器地址生成 | |n1|cb|XX|b1|b2|b3|b4|
寄存器文件查找 | | |n1|cb|XX|b1|b2|b3|
ALU/shifter/cc | | | |n1|cb|XX|b1|b2|
写回 | | | | |n1|cb|XX|b1|
如果微码正确地推测采取的转移，微引擎仍要浪费1周，如表7所示。
表7
推测转移被采取/转移不被采取
|1|2|3|4|5|6|7|8|
-------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n1|XX|n2|n3|n4|n5|
寄存器地址生成 | |n1|cb|n1|XX|n2|n3|n4|
寄存器文件查找 | | |n1|cb|n1|XX|n2|n3|
ALU/shifter/cc | | | |n1|cb|n1|XX|n2|
写回 | | | | |n1|cb|n1|XX|
然而，当微码推测的转移未被采取时，延迟损失的分布不同。对于推测转移不采取/转移不采取，如图8所示没有浪费周期。
表8
|1|2|3|4|5|6|7|8|
--------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n1|n2|n3|n4|n5|n6|
寄存器地址生成 | |n1|cb|n1|n2|n3|n4|n5|
寄存器文件查找 | | |n1|cb|n1|n2|n1|b4|
ALU/shifter/cc | | | |n1|cb|n1|n2|n3|
写回 | | | | |n1|cb|n1|n2|
然而，对于推测转移不采取/转移被采取，如表9所示有二个周期浪费。
表9
|1|2|3|4|5|6|7|8|
--------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n1|XX|b1|b2|b3|b4|
寄存器地址生成 | |n1|cb|XX|XX|b1|b2|b3|
寄存器文件查找 | | |n1|cb|XX|XX|b1|b2|
ALU/shifter/cc | | | |n1|cb|XX|XX|b1|
写回 | | | | |n1|cb|XX|XX|
微引擎可将转移推测与1周转移延迟相组合以进一步改进结果。对于推测转移采用有一周延期转移/转移被采取如表10所示。
表10
|1|2|3|4|5|6|7|8|
-------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n2|b1|b2|b3|b4|b5|
寄存器地址生成 | |n1|cb|n2|b1|b2|b3|b4|
寄存器文件查找 | | |n1|cb|n2|b1|b2|b3|
ALU/shifter/cc | | | |n1|cb|n2|b1|b2|
写回 | | | | |n1|cb|n2|b1|
在上述情况下，通过执行n2，和正确推测转移方向隐含了2周的转移延迟。
如果微码推测正确，如表11所示仍暴露了1周的转移延迟(推测转移采取1周延期转移/转移不采取)。
表11
|1|2|3|4|5|6|7|8|9|
----------------------+----+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n2|XX|n3|n4|n5|n6|n7|
寄存器地址生成 | |n1|cb|n2|XX|n3|n4|n5|n6|
寄存器文件查找 | | |n1|cb|n2|XX|n3|n4|n5|
ALU/shifter/cc | | | |n1|cb|n2|XX|n3|n4|
写回 | | | | |n1|cb|n2|XX|n3|
如果微码正确地推测转移不被采取，则流水线以正常的未打扰情况顺序流动。如果微码不正确地推测转移未被采取，如表12所示微码再次暴露了有1周无成效的执行。
表12
推测转移未被采取/转移被采取
|1|2|3|4|5|6|7|8|9|
------------------+----+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n2|XX|b1|b2|b3|b4|b5|
寄存器地址生成 | |n1|cb|n2|XX|b1|b2|b3|b4|
寄存器文件查找 | | |n1|cb|n2|XX|b1|b2|b3|
ALU/shifter/cc | | | |n1|cb|n2|XX|b1|b2|
写回 | | | | |n1|cb|n2|XX|b1|
其中nx是预转移微码(n1设置cc)
cb是条件转移
bx是后转移微字
XX是终止微字
在跳转指令的情况下，因为在直到跳转所在的ALU级的周期结束前不知道转移地址，引起了3个周期的额外等待延迟(表13)。
表13
|1|2|3|4|5|6|7|8|9|
------------------+----+----+----+----+----+----+----+----+----+
微存储查找 |n1|jp|XX|XX|XX|j1|j2|j3|j4|
寄存器地址生成 | |n1|jp|XX|XX|XX|j1|j2|j3|
寄存器文件查找 | | |n1|jp|XX|XX|XX|j1|j2|
ALU/shifter/cc | | | |n1|jp|XX|XX|XX|j1|
写回 | | | ||n1|jp|XX|XX|XX|
参考图5，微引擎支持各种转移指令，诸如根据条件码转移的转移指令。此外，微引擎还支持根据一字节等于或不等于指定字节而转移的转移指令。根据字节的转移指令“BR＝BYTE”包括一字节_说明字段。
BR＝BYTE，BR！＝BYTE
如果在长字中的指定字节匹配或不匹配字节_比较_值，这一转移指令转移到指定标号处的指令。该br＝byte指令预提取“转移采取”条件的指令而不是下一条件指令。br！＝byte指令预提取下一顺序指令。这些指令设置了微引擎中的条件码。格式：
br＝byte[reg，byte_spec，byte_compare_value，label#]，optional_oken
br！＝byte[reg，byte_spec，byte_compare_value，label#]，optional_token
寄存器A是前后文相关转移寄存器或保持操作数的通用寄存器。字节_说明数指定了寄存器中与字节_比较_值比较的一个字节。有效的字节说明_值是0到3。0值指最右字节。
字节_比较_值是用于比较的值。有效的字节_比较_值是0到255。标号#是与指令地址对应的符号标号。字令还能包括任选项_标志。在该例子中任选项标志可被推迟一个值，该值将在执行转移操作前执行跟随在该转移指令前的一条指令。另一方面，任选项标志可被推迟二条指令。这允许用br！＝byte指令实现并在执行转移操作前执行跟随在这一转移指令后的二条指令。另一方面任选项标志也可推迟三条指令，它允许用br！＝byte指令实现并在执行转移操作前使处理器执行跟随在这一转移指令后的三条指令。
例子：br！＝byte[reg，byte_spec，byte_compare_value，label#]，defer[3]
这一指令表示一指令，该指令将寄存器操作数的对齐字节与立即的指定字节值比较。字节_说明参数表示要比较的对齐字节(0是最右字节，3是最左字节)。ALU条件码通过从指定寄存器字节减去指定值而设置。如果值匹配，采取指定的转移。有3周转移延迟与这一微码相关，既然条件码被计算出来，因而为了用有用的工作填充该等待延迟，允许有1、2和3的转移确定。寄存器可以是A或B组寄存器。
参照图6，存在二个寄存器地址空间是可被所有微引擎访问的局部可访问寄存器，和全局可访问寄存器。通用寄存器(GPR)实现为两个分开的组(A组和B组)它们的地址按逐字方式交织使得个A组寄存器有lsb＝0，B寄存器lsb＝1，每个组能够对各组中的二个不同字同时执行读和写。
跨越整个组A和B，寄存器组76b的32个寄存器还组织成四个窗口76b。一76b3，它们可由每个线程相对寻址。因而线程_0在77a处找到其寄存器_0(寄存器0)，线程_1将在77b处找到其寄存器_0(寄存器32)，线程_2将在77c处找到其寄存器_0(寄存器64)，而线程_3在77d处找(寄存器96)。支持相对寻址使得多线程能使用完成相同的控制存储和位置，但访问不同的寄存器窗口并执行不同的功能。使用寄存器窗口寻址和分组寻址，便可在微引擎22f中仅使用双端口RAM，就可提供必不可少的读带宽。
这些窗口化的寄存器在从前后文切换到前后文切换的过程中不必保存数据，从而不必作前后文交换文件或堆栈的正常压入或弹出。前后文交换在这里从一个前后文文本改变为另一文本时有0周的附加开销。相对寄存器寻址将寄存器组整个通用寄存器组的地址宽度分成窗口。相对寻址允许相对于窗口起始点访问任何一个窗口。在该结构也支持绝对寻址，其中通过提供精确的寄存器地址，任何一个绝对寄存器均可被任何线程访问。
根据微字格式通用寄存器78的寻址可在2个模式中出现。这二个模式是绝对模式和相对模式。在绝对模式中，寄存器地址的寻址直接以7位源字段(a6-a0或b6-b0)指定，如下表14所示：
表14
7 6 5 4 3 2 1 0
+…+…+…+…+…+…+…+…+
A GPR： |a6|0|a5|a4|a3|a2|a1|a0| a6＝0
B GPR： |b6|1|b5|b4|b3|b2|b1|b0| b6＝0
SRAM/ASB：|a6|a5|a4|0|a3|a2|a1|a0| a6＝1，a5＝0，a4＝0
SDRAM： |a6|a5|a4|0|a3|a2|a1|a0| a6＝1，a5＝0，a4＝1
寄存器地址直接以表15中8位目标字段(d7-d0)指定：
表15
7 6 5 4 3 2 1 0
+…+…+…+…+…+…+…+…+
A GPR： |d7|d6|d5|d4|d3|d2|d1|d0| d7＝0，d6＝0
B GPR： |d7|d6|d5|d4|d3|d2|d1|d0| d7＝0，d6＝1
SRAM/ASB：|d7|d6|d5|d4|d3|d2|d1|d0| d7＝1，d6＝0，d5＝0
SDRAM： |d7|d6|d5|d4|d3|d2|d1|d0| d7＝1，d6＝0，d5＝1
如果<a6:a5>＝1，1，<b6:b5>＝1，1或<d7:d6>＝1，1则低位解释为与前后文相关的地址字段(下述)。当在A、B绝对字段中指定了非相关A或B源地址时，只有SRAM/ASB和SDRAM地址空间的下半部分被寻址。实际上，读绝对SRAM/SDRAM装置具有有效地址空间；然而，由于这一限制不适用于目标字段，写SRAM/SDRAM仍使用该全地址空间。
在相对模式中对指定地址的寻址是在前后文空间中用表16中的5位源字段(a4-a0或b4-b0)定义的偏置：
表16
7 6 5 4 3 2 1 0
+…+…+…+…+…+…+…+…+
A GPR： |a4|0|前后文|a3|a2|a1|a0| a4＝0
B GPR： |b7|1|前后文|b3|b2|b1|b0| b4＝0
SRAM/ASB：|ab4|0|ab3|前后文|b2|b1|ab0| ab4＝1，ab3＝0
SDRAM： |ab4|0|ab3|前后文|b2|b1|ab0| ab4＝1，ab3＝1
或用表17中的6位目标字段(d5-d0)定义的偏置：
表17
7 6 5 4 3 2 1 0
+…+…+…+…+…+…+…+…+
A GPR： |d5|d4|前后文|d3|d2|d1|d0| d5＝0，d4＝0
B GPR： |d5|d4|前后文|d3|d2|d1|d0| d5＝0，d4＝1
SRAM/ASB：|d5|d4|d3|前后文|d2|d1|d0| d5＝1，d4＝0，d3＝0
SDRAM： |d5|d4|d3|前后文|d2|d1|d0| d5＝1，d4＝0，d3＝1
如果<d5:d4>＝1，1，则目标地址不寻址到一有效寄存器，因而，没有操作数被写回。
其它实施例是处在所附权利要求书范围内。
Claims (18)
1.一种操作处理器的方法，其特征在于，它包括：
基于寄存器中的一字节等于或不等于指定字节值，所述指定字节是否与该字节值匹配或不匹配，引导处理器从执行第一指令顺序系列转移到不同的指令顺序系列。
2.如权利要求1所述的方法，其特征在于，所述转移是转移到在指定标号处的一条指令。
3.如权利要求1所述的方法，其特征在于，引导处理器转移的步骤包括：
一位_位置字段，指定了包含在寄存器中的长字中的字节。
4.如权利要求1所述的方法，其特征在于，引导处理器转移的步骤包括：
设置一任选项标志，它指定了在执行转移前要执行的跟随在该转移后的指令数目i。
5.如权利要求1所述的方法，其特征在于，引导处理器转移的步骤包括：
设置一任选项标志，它指定了在执行转移前要执行的跟随在该转移后的指令数目i，其中指令数目可以被指定为1，2或3。
6.如权利要求1所述的方法，其特征在于，所述寄存器是前后文相关的转移寄存器或保持所述操作数的通用寄存器。
7.如权利要求1所述的方法，其特征在于，引导处理器转移的步骤包括：
设置任选项标志，它指定了对于“转移采取”条件的指令的推测_转移预提取而不是下一顺序指令。
8.如权利要求1所述的方法，其特征在于，引导处理器转移的步骤包括；
设置一任选项标志，指定了在执行转移操作前要执行的跟随在该转移后的指令数目i；以及
设置第二任选项标志，它指定了对于“转移采取”条件的指令的推测_转移预提取而不是下一顺序指令。
9.如权利要求1所述的方法，其特征在于，引导步骤允许程序员指定使用寄存器的哪一位来确定转移操作。
10.如权利要求1所述的方法，其特征在于，引导步骤允许基于对处理器的数据通路中的一字节所作的计算而发生转移。
11.如权利要求1所述的方法，其特征在于，引导步骤基于匹配所述字节值的一个字节而转移，并且引导步骤预提取用于“转移采取”条件的指令。
12.如权利要求1所述的方法，其特征在于，引导步骤基于不匹配所述字节值的一个字节而转移，并且引导步骤预提取下一顺序指令。
13.如权利要求1所述的方法，其特征在于，引导步骤包括一字节_说明号，该字节_说明号指定了寄存器中要与字节_比较_值比较的字节。
14.一种处理器，其特征在于，包括：
一寄存器堆；
一与寄存器堆耦合的算术逻辑单元，以及存储转移指令的程序控制存储器，所述转移指令使处理器：
提取存储在寄存器中的一字节；
确定寄存器中的该字节是否等于或不等于包含在该指令中的指定的字节值；以及
基于所述指定的字节等于或不等于寄存器中的该字节引导转移操作。
15.如权利要求14所述的处理器，其特征在于，所述引导转移操作是转移到指定标号处的一条指令。
16.如权利要求1所述的处理器，其特征在于，位_位置字段指定了包含在寄存器中的长字中的该字节。
17.一种操作处理器的方法，其特征在于，包括：
提取存储在寄存器中的一字节；
确定寄存器中的该字节是否等于或不等于包含在指令中的指定的字节值；以及
基于所述指定的字节等于或不等于寄存器中的该字节进行由所述指令指定的转移操作。
18.如权利要求17所述的方法，其特征在于，执行所述转移操作是转移到指定标号处的一条指令。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15196199P | 1999-09-01 | 1999-09-01 | |
| US60/151,961 | 1999-09-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1387640A CN1387640A (zh) | 2002-12-25 |
| CN1254739C true CN1254739C (zh) | 2006-05-03 |
Family
ID=22540994
Family Applications (7)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB008148740A Expired - Fee Related CN1271513C (zh) | 1999-09-01 | 2000-08-31 | 转移指令的方法和处理器 |
| CNB008154376A Expired - Fee Related CN1184562C (zh) | 1999-09-01 | 2000-08-31 | 处理器的转移指令 |
| CNB008154309A Expired - Fee Related CN1254739C (zh) | 1999-09-01 | 2000-08-31 | 处理器和操作处理器的方法 |
| CNB008154171A Expired - Fee Related CN100342326C (zh) | 1999-09-01 | 2000-08-31 | 多线程处理器和操作处理器的方法 |
| CNB008144966A Expired - Fee Related CN100474236C (zh) | 1999-09-01 | 2000-08-31 | 多线程并行处理器及其维持线程执行的方法 |
| CNB008151237A Expired - Fee Related CN1296818C (zh) | 1999-09-01 | 2000-08-31 | 用于多线程并行处理器的指令 |
| CNB008154120A Expired - Fee Related CN100351781C (zh) | 1999-09-01 | 2000-09-01 | 多线程并行处理器结构中所用的微引擎的存储器引用指令 |
Family Applications Before (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB008148740A Expired - Fee Related CN1271513C (zh) | 1999-09-01 | 2000-08-31 | 转移指令的方法和处理器 |
| CNB008154376A Expired - Fee Related CN1184562C (zh) | 1999-09-01 | 2000-08-31 | 处理器的转移指令 |
Family Applications After (4)
| Application Number | Title | Priority Date | Filing Date |
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| CNB008144966A Expired - Fee Related CN100474236C (zh) | 1999-09-01 | 2000-08-31 | 多线程并行处理器及其维持线程执行的方法 |
| CNB008151237A Expired - Fee Related CN1296818C (zh) | 1999-09-01 | 2000-08-31 | 用于多线程并行处理器的指令 |
| CNB008154120A Expired - Fee Related CN100351781C (zh) | 1999-09-01 | 2000-09-01 | 多线程并行处理器结构中所用的微引擎的存储器引用指令 |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US7421572B1 (zh) |
| EP (7) | EP1236088B9 (zh) |
| CN (7) | CN1271513C (zh) |
| AT (2) | ATE475930T1 (zh) |
| AU (11) | AU7097900A (zh) |
| CA (7) | CA2386558C (zh) |
| DE (2) | DE60044752D1 (zh) |
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| WO (8) | WO2001018646A1 (zh) |
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