CN112997298B - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN112997298B CN112997298B CN201980068831.3A CN201980068831A CN112997298B CN 112997298 B CN112997298 B CN 112997298B CN 201980068831 A CN201980068831 A CN 201980068831A CN 112997298 B CN112997298 B CN 112997298B
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- layer
- semiconductor device
- metal layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 246
- 229910052751 metal Inorganic materials 0.000 claims abstract description 202
- 239000002184 metal Substances 0.000 claims abstract description 202
- 238000009792 diffusion process Methods 0.000 claims abstract description 33
- 239000007790 solid phase Substances 0.000 claims abstract description 32
- 229920005989 resin Polymers 0.000 claims description 73
- 239000011347 resin Substances 0.000 claims description 73
- 238000005538 encapsulation Methods 0.000 claims description 56
- 230000002093 peripheral effect Effects 0.000 claims description 29
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 24
- 229910002804 graphite Inorganic materials 0.000 claims description 20
- 239000010439 graphite Substances 0.000 claims description 20
- 238000005452 bending Methods 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 10
- 238000007789 sealing Methods 0.000 claims description 10
- 238000010292 electrical insulation Methods 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 478
- 238000001514 detection method Methods 0.000 description 58
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 22
- 239000010949 copper Substances 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 18
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 15
- 239000000203 mixture Substances 0.000 description 15
- 229910052709 silver Inorganic materials 0.000 description 15
- 239000004332 silver Substances 0.000 description 15
- 229910000881 Cu alloy Inorganic materials 0.000 description 11
- 230000017525 heat dissipation Effects 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 239000011810 insulating material Substances 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 239000000919 ceramic Substances 0.000 description 9
- 239000011888 foil Substances 0.000 description 9
- 239000011800 void material Substances 0.000 description 8
- 238000007747 plating Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 229910000838 Al alloy Inorganic materials 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000001771 vacuum deposition Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 229920002577 polybenzoxazole Polymers 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- 239000004918 carbon fiber reinforced polymer Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229920000049 Carbon (fiber) Polymers 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 244000126211 Hericium coralloides Species 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000004917 carbon fiber Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明提供一种半导体装置,其具备支撑部件、导电部件和半导体元件。所述支撑部件具有朝向厚度方向的支撑面。所述导电部件具有:在所述厚度方向上朝向与所述支撑面相同的一侧的主面、以及朝向与所述主面相反的一侧的背面。所述导电部件以所述背面与所述支撑面对置的方式与所述支撑部件接合。所述半导体元件与所述主面接合。所述半导体装置还具备第一金属层和第二金属层。所述第一金属层覆盖所述支撑面的至少一部分。所述第二金属层覆盖所述背面。所述第一金属层和所述第二金属层通过固相扩散彼此接合。
Description
技术领域
本公开涉及具备半导体元件的半导体装置,尤其涉及半导体元件为开关元件的半导体装置。
背景技术
以往广泛公知搭载有MOSFET或IGBT等半导体元件的半导体装置。专利文献1公开了搭载有这种半导体元件的半导体装置的一例。在该半导体装置中,在支撑部件(在专利文献1中是绝缘基板11)上配置有由金属箔构成的导电部件(在专利文献1中是金属图案4a、4b)。半导体元件与该导电部件接合。
在使用专利文献1公开的半导体装置时从半导体元件发热,因此导电部件的温度上升。由金属箔构成的导电部件的厚度比较薄,因此具有与厚度方向正交的方向上的单位长度的热电阻较高的特性。因此,导电部件的温度降低比较缓慢,在位于半导体元件附近的该导电部件中,存在高温状态局部性地持续的问题。
现有技术文献
专利文献
专利文献1:日本特开2009-158787号公报
发明内容
发明所要解决的课题
本公开针对上述情况的课题在于,提供一种能够提高散热性的半导体装置。
用于解决课题的方案
根据本公开提供的半导体装置,具备:支撑部件,其具有朝向厚度方向的支撑面;导电部件,其具有在所述厚度方向上朝向与所述支撑面相同的一侧的主面、和朝向与所述主面相反的一侧的背面,并且以所述背面与所述支撑面对置的方式与所述支撑部件接合;以及半导体元件,其与所述主面接合,还具备覆盖所述支撑面的至少一部分的第一金属层、和覆盖所述背面的第二金属层,所述第一金属层和所述第二金属层通过固相扩散彼此接合。
以下基于附图对本公开提供的半导体装置的具体结构进行详细说明。
附图说明
图1是本公开第一实施方式的半导体装置的立体图。
图2是图1所示的半导体装置的俯视图。
图3是与图2对应的俯视图且透过了封装树脂。
图4是图1所示的半导体装置的仰视图。
图5是沿着图3的V-V线的剖视图。
图6是沿着图3的VI-VI线的剖视图。
图7是图3的局部放大图。
图8是沿着图7的VIII-VIII线的剖视图。
图9A是图8的局部放大图。
图9B是图8的局部放大图。
图9C是与图9B所示结构对应的局部放大图,且示出了沿着厚度方向观察时的第二金属层的中央部。
图9D是与图9B所示结构对应的局部放大图,且示出了沿着厚度方向观察时的第二金属层的周缘部。
图10A是本公开第一实施方式的变形例的半导体装置的局部放大剖视图。
图10B是本公开第一实施方式的变形例的半导体装置的局部放大剖视图。
图10C是与图10B所示结构对应的局部放大图,且示出了沿着厚度方向观察时的第二金属层的中央部。
图10D是与图10B所示结构对应的局部放大图,且示出了沿着厚度方向观察时的第二金属层的周缘部。
图11是本公开第二实施方式的半导体装置的俯视图,且透过了封装树脂。
图12是图11所示半导体装置的仰视图。
图13是沿着图11的XIII-XIII线的剖视图。
图14是沿着图11的XIV-XIV线的剖视图。
图15是图13的局部放大图。
图16是构成图11所示半导体装置的导电部件的基层的石墨的结晶结构的模式图。
图17是图15的局部放大图。
图18是本公开第三实施方式的半导体装置的立体图。
图19是图18所示半导体装置的俯视图。
图20是与图19对应的俯视图,且透过了封装树脂。
图21是针对图20所示半导体装置进一步透过了第二输入端子和多个导通部件的俯视图。
图22是图18所示半导体装置的仰视图。
图23是图18所示半导体装置的右侧视图。
图24是图18所示半导体装置的左侧视图。
图25是图18所示半导体装置的正视图。
图26是沿着图20的XXVI-XXVI线的剖视图。
图27是沿着图20的XXVII-XXVII线的剖视图。
图28是图26的局部放大图。
图29是图27的局部放大图。
图30是本公开第四实施方式的半导体装置的俯视图,且透过了封装树脂。
图31是图30所示半导体装置的仰视图。
图32是沿着图30的XXXII-XXXII线的剖视图。
图33是沿着图30的XXXIII-XXXIII线的剖视图。
图34是图32的局部放大图。
图35是图33的局部放大图。
图36是本公开第五实施方式的半导体装置的俯视图,且透过了封装树脂。
图37是图36所示半导体装置的仰视图。
图38是沿着图36的XXXVIII-XXXVIII线的剖视图。
图39是沿着图36的XXXIX-XXXIX线的剖视图。
图40是本公开第六实施方式的半导体装置的局部放大剖视图。
图41是图40的局部放大图。
图42A是与图41所示结构对应的局部放大图,且示出了沿着厚度方向观察时的第二金属层的中央部的上端。
图42B是与图41所示结构对应的局部放大图,且示出了沿着厚度方向观察时的第二金属层的周缘部的上端。
图43A是与图41所示结构对应的局部放大图,且示出了沿着厚度方向观察时的第二金属层的中央部的下端。
图43B是与图41所示结构对应的局部放大图,且示出了沿着厚度方向观察时的第二金属层的周缘部的下端。
具体实施方式
参照附图对本公开的实施方式进行说明。
〔第一实施方式〕
参照图1~图9D对本公开第一实施方式的半导体装置A10进行说明。半导体装置A10具备:支撑部件10、第一金属层19、导电部件20、第二金属层29、第一端子31、第二端子32、半导体元件40、导通部件50和封装树脂60。此外,半导体装置A10还具备:绝缘层23、栅极层24、检测层25、栅极端子36、检测端子37、栅极引线51、检测引线52、第一引线531和第二引线532。这些图中示出的半导体装置A10是半导体元件40例如为MOSFET的电力变换装置(功率模块)。半导体装置A10可用于电动机的驱动源、各种电器产品的逆变器装置、以及DC/DC转换器等。在此,图3为了便于理解而透过了封装树脂60。在图3中以虚拟线(双点划线)示出了透过的封装树脂60。图9C和图9D均与图9B所示结构对应,并且剖面位置互不相同。
在对半导体装置A10的说明中,将支撑部件10的厚度方向称为“厚度方向z”。将与厚度方向z正交的方向称为“第一方向x”。将与厚度方向z和第一方向x双方正交的方向称为“第二方向y”。如图1和图2所示,半导体装置A10沿着厚度方向z观察呈矩形状。第一方向x与半导体装置A10的长度方向对应。第二方向y与半导体装置A10的短边方向对应。另外,在对半导体装置A10的说明中,为了方便而将第一方向x上的第一端子31所在侧称为“第一方向x的一侧”。将第一方向x上的第二端子32所在侧称为“第一方向x的另一侧”。
如图3、图5和图6所示,支撑部件10对导电部件20进行支撑。在半导体装置A10的示例中,支撑部件10沿着厚度方向z观察呈以第一方向x为长边的矩形状。支撑部件10具有在厚度方向z上彼此朝向相反侧的支撑面10A和底面10B。其中,支撑面10A与导电部件20对置。如图4~图6所示,底面10B从封装树脂60露出。在将半导体装置A10安装于散热器时,底面10B与该散热器对置。在半导体装置A10中,支撑部件10具有第一支撑板11、第二支撑板12和底板13。
如图5和图6所示,第一支撑板11在厚度方向z上位于第二支撑板12和底板13之间。第一支撑板11具有电绝缘性。第一支撑板11是热传导性优异的陶瓷。作为该陶瓷的一例,可举出氮化铝(AlN)。
如图3、图5和图6所示,第二支撑板12与第一支撑板11层叠。第二支撑板12包含支撑面10A。在半导体装置A10中,导电部件20与第二支撑板12接合。第二支撑板12是由铜(Cu)或铜合金构成的金属箔。因此,第二支撑板12具有导电性。在半导体装置A10的示例中,第二支撑板12具有第一区域121、第二区域122和第三区域123这三个区域。这三个区域彼此分离。第一区域121位于第一方向x的一侧。第二区域122相对于第一区域121而言,位于第一方向x的另一侧。第三区域123相对于第一区域121而言,位于第二方向y的一侧。其中,第一区域121和第三区域123沿着厚度方向z观察呈在第一方向x上延伸的帯状。
如图5和图6所示,底板13在与第二支撑板12相反的一侧与第一支撑板11层叠。底板13包含底面10B。底板13与第二支撑板12同样地是由铜或铜合金构成的金属箔。因此,第二支撑板12具有导电性。如图4所示,沿着厚度方向z观察,底板13的面积比第一支撑板11的面积小。相应地,第一支撑板11的周缘位于比底板13的周缘靠外侧。由此,在支撑部件10设有台阶部13A,该台阶部13A沿着厚度方向z观察围绕底板13。台阶部13A被封装树脂60覆盖。
在半导体装置A10中,支撑部件10例如可以采用DBC(Direct Bonded Copper:直接键合铜)基板而容易地形成。DBC基板由陶瓷板、和在厚度方向z的两侧与陶瓷板层叠的一对铜箔构成。该陶瓷板成为第一支撑板11。将一对铜箔分别通过蚀刻而局部地除去,从而形成第二支撑板12和底板13。
如图5和图6所示,第一金属层19将支撑部件10的支撑面10A的至少一部分覆盖。在半导体装置A10中,第一金属层19将第二支撑板12的第一区域121和第二区域122各自的支撑面10A覆盖。此外,第一金属层19不覆盖第二支撑板12的第三区域123的支撑面10A。如图9A所示,第一金属层19具有第一层191和第二层192。第一层191将支撑面10A的至少一部分覆盖。第一层191的组成包含铝(Al)。第二层192在厚度方向z上相对于第一层191而言,位于与支撑部件10相反的一侧并且与第一层191层叠。第二层192的组成含银(Ag)。第一层191的维氏硬度(HV)比第二层192的维氏硬度小。相应地,第一层191的厚度t1比第二层192的厚度t2大。
第一金属层19可通过相对于支撑部件10的支撑面10A依次进行第一层191、第二层192各层的成膜而形成。成膜方法例如可举出溅射法、或者真空蒸镀。在为了形成支撑部件10而采用DBC基板的情况下,在厚度方向z的一侧以将层叠于陶瓷板的一侧的铜箔覆盖的方式依次进行第一层191、第二层192的成膜。之后,第一层191和第二层192都通过将一侧的铜箔利用蚀刻局部地除去而形成第二支撑板12和第一金属层19。
如图9B所示,第一金属层19可以是仅为单层的结构。在该情况下,第一金属层19的组成含银。
如图3、图5和图6所示,导电部件20与支撑部件10的第二支撑板12接合。在半导体装置A10中,导电部件20与第一端子31、第二端子32和导通部件50一起构成了半导体装置A10的外部与半导体元件40的导电路径。导电部件20具有在厚度方向z上彼此朝向相反侧的主面20A和背面20B。主面20A在厚度方向z上朝向与支撑部件10的支撑面10A相同的一侧。背面20B与支撑部件10的支撑面10A对置。在半导体装置A10中,导电部件20是由铜或铜合金构成的金属板。如图8所示,导电部件20的厚度Ta比第二支撑板12的厚度Tb大。此外,也可以在主面20A上施加例如银镀层或者依次层叠有铝层、镍(Ni)层、银层的多种金属镀层。
如图3和图5所示,导电部件20包含第一导电部201和第二导电部202。第一导电部201与第二支撑板12的第一区域121接合。第二导电部202与第二支撑板12的第二区域122接合。因此,第一导电部201和第二导电部202在第一方向x上彼此分离。
如图5和图6所示,第二金属层29将导电部件20(第一导电部201和第二导电部202)各自的背面20B覆盖。如图9A和图9B所示,第二金属层29具有第一层291和第二层292。第一层291将背面20B覆盖。第一层291的组成包含铝。第二层292在厚度方向z上相对于第一层291而言,位于与导电部件20相反的一侧并且与第一层291层叠。第二层292的组成含银。第一层291的维氏硬度比第二层292的维氏硬度小。相应地,第一层291的厚度t1比第二层292的厚度t2大。
第二金属层29可通过相对于导电部件20的背面20B依次进行第一层291、第二层292各层的成膜而形成。成膜方法例如可举出溅射法、或者真空蒸镀。
接下来,对支撑部件10与导电部件20的接合方法进行说明。
首先,使将导电部件20的背面20B覆盖的第二金属层29与将支撑部件10的支撑面10A覆盖的第一金属层19接触。此时,第一金属层19的第二层192与第二金属层29的第二层292彼此接触。由此,支撑面10A与背面20B彼此对置。
接下来,使第一金属层19与第二金属层29通过固相扩散彼此接合。为了使第一金属层19和第二金属层29进行固相扩散,需要在高温高压下进行。作为进行固相扩散的条件,例如温度为350℃且压力为40MPa。由此,使第一金属层19的第二层192、与第二金属层29的第二层292通过固相扩散彼此接合。此外,虽然该固相扩散设定为在大气中进行,但是也可以在真空中进行。如上所述,在导电部件20的背面20B与支撑部件10的支撑面10A对置的状态下,使导电部件20与支撑部件10接合。
如图9A和图9B所示,在第一金属层19的第二层192、与第二金属层29的第二层292之间形成有空隙19A。空隙19A在使第一金属层19与第二金属层29通过固相扩散彼此接合时形成。
如图9C和图9D所示,就第二金属层29的第二层292的每单位体积中的空隙19A的体积而言,在沿着厚度方向z观察时的第二金属层29的中央部、和沿着厚度方向z观察时的第二金属层29的周缘部有所不同。该中央部的第二层292的每单位体积中的空隙19A的体积比该周缘部的第二层292的每单位体积中的空隙19A的体积小。
如图9D所示,沿着厚度方向z观察,在导电部件20的周缘部形成有从背面20B向厚度方向z凹陷的凹部20C。第二金属层29的第一层291与凹部20C相接。此外,如图9C和图9D所示,沿着厚度方向z观察,第一层291的中央部的最大厚度t1-1比第一层291的周缘部的最大厚度t1-2小。
如图3和图6所示,绝缘层23配置于第二支撑板12的第三区域123的支撑面10A。绝缘层23呈在第一方向x上延伸的帯状。作为绝缘层23的材料的一例,可举出陶瓷或玻璃环氧树脂。
如图3和图6所示,栅极层24在绝缘层23上配置。栅极层24呈在第一方向x上延伸的帯状。栅极层24是包含铜或铜合金的金属箔。此外,也可以在栅极层24的表面施加例如银镀层。
如图3和图6所示,检测层25在绝缘层23上配置。检测层25呈在第一方向x上延伸的帯状。检测层25的宽度与栅极层24的宽度大致相等。沿着厚度方向z观察,检测层25在第二方向y上位于栅极层24与第一导电部201之间。检测层25是由铜或铜合金构成的金属箔。此外,也可以在检测层25的表面施加例如银镀层。
如图2、图3和图5所示,第一端子31位于第一方向x的一侧。第一端子31与第一导电部201连接。沿着厚度方向z观察,第一端子31呈在第一方向x上延伸的帯状。第一端子31是由铜或铜合金构成的金属板。第一端子31具有连接部311和端子部312。连接部311被封装树脂60覆盖。连接部311通过焊锡接合或者超音波接合等与第一导电部201的主面20A连接。由此,第一端子31与第一导电部201导通。端子部312与连接部311的第一方向x的一侧相连。端子部312从封装树脂60露出。
如图2、图3和图5所示,第二端子32位于第一方向x的另一侧。第二端子32与第二导电部202连接。沿着厚度方向z观察,第二端子32呈在第一方向x上延伸的帯状。第二端子32是由铜或金属板构成的金属板。第二端子32具有连接部321和端子部322。连接部321被封装树脂60覆盖。连接部321通过焊锡接合或超音波接合与第二导电部202的主面20A连接。由此,第二端子32与第二导电部202导通。端子部322与连接部321的第一方向x的另一侧相连。端子部322从封装树脂60露出。
如图3和图5所示,半导体元件40与第一导电部201(导电部件20)的主面20A接合。半导体元件40是例如采用以碳化硅(SiC)为主的半导体材料构成的MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor:金属氧化物半导体场效应晶体管)。此外,半导体元件40不限于MOSFET,也可以是包含MISFET(Metal-Insulator-Semiconductor Field-Effect Transistor:金属绝缘体半导体场效应晶体管)的场效应晶体管、IGBT(InsulatedGate Bipolar Transistor:绝缘栅双极型晶体管)等双极型晶体管。在对半导体装置A10的说明中,半导体元件40以n沟道型且纵型结构的MOSFET为对象。
如图7和图8所示,半导体元件40具有第一面40A、第二面40B、第一电极41、第二电极42、栅极电极43和绝缘膜44。第一面40A和第二面40B在厚度方向z上彼此朝向相反侧。第一面40A在厚度方向z上朝向与第一导电部201的主面20A相同的一侧。因此,背面20B与主面20A对置。
如图7和图8所示,第一电极41设置于第一面40A。从半导体元件40的内部向第一电极41流通源极电流。
如图8所示,第二电极42设置于第二面40B的整体。在第二电极42中朝向半导体元件40的内部流通漏极电流。第二电极42通过具有导电性的接合层49与第一导电部201的主面20A接合。作为接合层49的一例,可举出以锡(Sn)为主成分的无铅焊锡、或者烧成银。由此,第二电极42与第一导电部201导通。因此,第一端子31经由第一导电部201与第二电极42导通。因此,第一端子31相当于半导体装置A10的漏极端子。
如图7所示,栅极电极43设置于第一面40A。栅极电极43被施加用于驱动半导体元件40的栅极电压。栅极电极43的尺寸比第一电极41的尺寸小。
如图7和图8所示,绝缘膜44设置于第一面40A。绝缘膜44具有电绝缘性。沿着厚度方向z观察,绝缘膜44分别包围第一电极41和栅极电极43。绝缘膜44例如从第一面40A起依次层叠有:二氧化硅(SiO2)层、氮化硅(Si3N4)层、聚苯并噁唑(PBO)层。此外,在绝缘膜44中也可以取代该聚苯并噁唑层而具备聚酰亚胺层。
如图3和图5所示,导通部件50与半导体元件40的第一电极41、第二导电部202的主面20A连接。沿着厚度方向z观察,导通部件50呈在第一方向x上延伸的帯状。导通部件50是由铜或铜合金构成的金属导线。导通部件50的位于第一方向x的一侧的端部通过接合层49与第一电极41连接。导通部件50的位于第一方向x的另一侧的端部通过接合层49与第二导电部202的主面20A连接。由此,第一电极41与第二导电部202导通。因此,第二端子32经由第二导电部202和导通部件50与第一电极41导通。因此,第二端子32相当于半导体装置A10的源极端子。此外,导通部件50也可以是多个引线。作为该多个引线的材料的一例,可举出铝或铝合金。
如图3所示,栅极引线51与半导体元件40的栅极电极43、栅极层24连接。由此,栅极电极43与栅极层24导通。作为栅极引线51的材料的一例,可举出金(Au)、铝或铝合金。
如图3所示,检测引线52与半导体元件40的第一电极41、检测层25连接。由此,第一电极41与检测层25导通。作为检测引线52的材料的一例,可举出铝或铝合金。
如图3所示,栅极端子36和检测端子37在第二方向y上与支撑部件10相邻。栅极端子36和检测端子37沿着第一方向x排列。栅极端子36和检测端子37均由同一导线框构成。
栅极端子36被施加用于驱动半导体元件40的栅极电压。栅极端子36具有连接部361和端子部362。连接部361被封装树脂60覆盖。由此,栅极端子36被封装树脂60支撑。此外,也可以在连接部361的表面施加例如银镀层。端子部362与连接部361相连,并且从封装树脂60露出(参照图6)。沿着第一方向x观察,端子部362呈L字状。
如图3所示,检测端子37在第一方向x上与栅极端子36相邻。在检测端子37上可检测向半导体元件40的第一电极41施加的电压(与源极电流对应的电压)。检测端子37具有连接部371和端子部372。连接部371被封装树脂60覆盖。由此,检测端子37被封装树脂60支撑。此外,也可以在连接部371的表面施加例如银镀层。端子部372与连接部371相连,并且从封装树脂60露出(参照图3和图4)。沿着第一方向x观察,端子部372呈L字状。
如图3所示,第一引线531与栅极端子36的连接部361、栅极层24连接。由此,栅极端子36与栅极层24导通。因此,栅极端子36经由第一引线531、栅极层24和栅极引线51与半导体元件40的栅极电极43导通。作为第一引线531的材料的一例,可举出铝或铝合金。
如图3所示,第二引线532与检测端子37的连接部371、检测层25连接。由此,检测端子37与检测层25导通。因此,检测端子37经由第二引线532、检测层25和检测引线52与半导体元件40的第一电极41导通。作为第二引线532的材料的一例,可举出铝或铝合金。
如图5所示,封装树脂60将支撑部件10、第一端子31和第二端子32各自的一部分、导电部件20、半导体元件40和导通部件50覆盖。封装树脂60将绝缘层23、栅极层24、检测层25、栅极引线51、检测引线52、第一引线531和第二引线532、栅极端子36和检测端子37各自的一部分覆盖。封装树脂60由包含例如黑色的环氧树脂的材料构成。如图2~图6所示,封装树脂60具有顶面61、底面62、一对第一侧面63A和一对第二侧面63B。
如图5和图6所示,顶面61在厚度方向z上朝向与支撑部件10的支撑面10A相同的一侧。底面62在厚度方向z上朝向与顶面61相反的一侧。如图4所示,从底面62露出底板13(支撑部件10)的底面10B。底面62呈围绕底板13的框状。
如图5所示,一对第一侧面63A与顶面61和底面62双方相连,并且朝向第一方向x。从位于第一方向x的一侧的第一侧面63A露出第一端子31的端子部312。从位于第一方向x的另一侧的第一侧面63A露出第二端子32的端子部322。
如图6所示,一对第二侧面63B与顶面61和底面62双方相连,并且朝向第二方向y。一对第二侧面63B的第一方向x的两端与一对第一侧面63A相连。从一对第二侧面63B的任意一方露出栅极端子36的端子部362、和检测端子37的端子部372。
<第一实施方式的变形例>
接下来,参照图10A~图10D对半导体装置A10的变形例即半导体装置A11进行说明。在半导体装置A11中的第一金属层19和第二金属层29的结构与前述半导体装置A10中的第一金属层19和第二金属层29的结构不同。在此,图10C和图10D均与图10B所示的结构对应,并且剖面位置互不相同。
如图10A所示,半导体装置A11的第一金属层19还具有夹在第一层191与第二层192之间的第三层193。第三层193的组成含镍。第三层193的厚度t3比第一层191和第二层192各自的厚度t1、t2小。
如图10B所示,第一金属层19可以与图9B所示半导体装置A10的情况同样地仅由单层构成。此时,第一金属层19的组成含银。
如图10A和图10B所示,半导体装置A11的第二金属层29还具有夹在第一层291与第二层292之间的第三层293。第三层293的组成含镍。第三层293的厚度t3比第一层291和第二层292各自的厚度t1、t2小。
半导体装置A11的第一金属层19可通过相对于支撑部件10的支撑面10A依次进行第一层191、第三层193、第二层192各层的成膜而形成。同样地,半导体装置A11的第二金属层29可通过相对于导电部件20的背面20B依次进行第一层291、第三层293、第二层292各层的成膜而形成。在半导体装置A11中,也是第一金属层19的第二层192、与第二金属层29的第二层292通过固相扩散彼此接合,从而使导电部件20与支撑部件10接合。
如图10C和图10D所示,就第二金属层29的第二层292的每单位体积中的空隙19A的体积而言,在沿着厚度方向z观察时的第二金属层29的中央部、和沿着厚度方向z观察时的第二金属层29的周缘部有所不同。该中央部的第二层292的每单位体积中的空隙19A的体积比该周缘部的第二层292的每单位体积中的空隙19A的体积小。
如图10D所示,沿着厚度方向z观察,在导电部件20的周缘部形成有从背面20B向厚度方向z凹陷的凹部20C。第二金属层29的第一层291与凹部20C相接。此外,如图10C和图10D所示,沿着厚度方向z观察,第一层291的中央部的最大厚度t1-1小于第一层291的周缘部的最大厚度t1-2。
接下来,对半导体装置A10的作用效果进行说明。
半导体装置A10具备第一金属层19和第二金属层29。第一金属层19将支撑部件10的支撑面10A的至少一部分覆盖。第二金属层29将导电部件20的背面20B覆盖。第一金属层19和第二金属层29通过固相扩散彼此接合。由此,能够使导电部件20的厚度与现有的金属箔相比更大。因此,降低了与厚度方向z正交的方向上的导电部件20的每单位长度内的热电阻,缓和了半导体元件40产生的热量在导电部件20局部性地集中的情况,并使该热量容易在大范围内传导。相应地,第一金属层19和第二金属层29通过固相扩散彼此接合,因此能够防止厚度方向z上的半导体装置A10的热传导性的降低。因此,根据半导体装置A10,能够提高其散热性。
如图9A和图9B所示,第二金属层29具有:将导电部件20的背面20B覆盖的第一层291、在厚度方向z上相对于第一层291而言位于与导电部件20相反的一侧的第二层292。第一金属层19的第二层192、与第二层292通过固相扩散彼此接合。第一层291的维氏硬度小于第二层292的维氏硬度。相应地,第二金属层29的第一层291的厚度t1大于第二金属层29的第二层292的厚度t2。由此,在使第一金属层19与第二金属层29通过固相扩散彼此接合时,能够使从支撑部件10和导电部件20向第一金属层19和第二金属层29作用的应力缓和。因此,降低了在通过固相扩散进行了接合的第一金属层19和第二金属层29中蓄积的残留应力,因此能够在使用半导体装置A10时抑制在第一金属层19和第二金属层29上产生龟裂。
在半导体装置A10中,支撑部件10具有:具有电绝缘性的第一支撑板11、包含支撑面10A且与第一支撑板11层叠的第二支撑板12。导电部件20是金属板。导电部件20的厚度大于第二支撑板12的厚度。由此,能够降低与厚度方向z正交的方向上的导电部件20的每单位长度内的热电阻。
支撑部件10具有朝向与支撑面10A相反的一侧的底面10B。半导体装置A10还具备将导电部件20和半导体元件40、支撑部件10的一部分覆盖的封装树脂60。底面10B从封装树脂60露出。由此,能够进一步提高半导体装置A10的散热性。另外,在支撑部件10上设有台阶部13A,该台阶部13A沿着厚度方向z观察,将支撑部件10的底板13包围。台阶部13A被封装树脂60覆盖。由此,在底面10B从封装树脂60露出的状态下,也能够防止支撑部件10从封装树脂60脱落。
〔第二实施方式〕
参照图11~图17对本公开第二实施方式的半导体装置A20进行说明。在这些图中,对于和上述半导体装置A10相同或类似的要素标记相同的符号并省略重复说明。在此,图11为了便于理解而透过了封装树脂60。将透过的封装树脂60用虚拟线表示。
半导体装置A20的支撑部件10和导电部件20的结构与前述半导体装置A10中的这些结构不同。
在半导体装置A20中,支撑部件10是绝缘板。如图11~图14所示,该绝缘板包含支撑面10A和底面10B。因此,在支撑部件10上并未如前述半导体装置A10的支撑部件10那样设置台阶部13A。该绝缘板是热传导性优异的陶瓷。作为该陶瓷,例如可举出氮化铝(AlN)。如图13所示,第一金属层19将沿着厚度方向z观察与导电部件20重叠的支撑部件10的支撑面10A的区域覆盖。
如图13和图14所示,导电部件20具有基层21、第一配线层221和第二配线层222。基层21占据导电部件20的体积的大半。基层21的组成含碳。在半导体装置A20中,基层21由石墨(graphite)构成。此外,基层21的材料还可以采用碳纤维强化树脂(carbon fiberreinforced plastic;CFRP)。如图16所示,石墨的结晶21A连续的方向即该石墨的面内方向在厚度方向z上沿着双方。石墨的结晶21A层叠的方向即该石墨的面外方向沿着与厚度方向z正交的方向。在半导体装置A20的示例中,该石墨的面外方向是第二方向y。因此,基层21的面内方向、即厚度方向z的杨氏模量可以为铜的4倍以上(1,000GPa以上)。此外,基层21的面外方向的杨氏模量为30~40GPa。如图15所示,基层21的厚度Td大于支撑部件10的厚度Tc。
如图13和图14所示,第一配线层221包含主面20A且与基层21层叠。第二配线层222包含背面20B且与基层21层叠。因此,基层21夹在第一配线层221和第二配线层222之间。第一配线层221和第二配线层222是由铜或铜合金构成的金属箔。如图15所示,第一配线层221和第二配线层222各自的厚度Te、Tf小于基层21的厚度Td。在导电部件20中,从背面20B到主面20A依次层叠有第二配线层222、基层21、第一配线层221。
如图17所示,第一金属层19和第二金属层29各自的结构与前述半导体装置A10的这些结构(参照图9A)相同。
接下来,对半导体装置A20的作用效果进行说明。
半导体装置A20具备第一金属层19和第二金属层29。第一金属层19将支撑部件10的支撑面10A的至少一部分覆盖。第二金属层29将导电部件20的背面20B覆盖。第一金属层19和第二金属层29通过固相扩散彼此接合。因此,采用半导体装置A20也能够提高其散热性。
在半导体装置A20中,支撑部件10是绝缘板。导电部件20具有:包含主面20A的第一配线层221、包含背面20B的第二配线层222、位于第一配线层221和第二配线层222之间的基层21。基层21由石墨构成。该石墨的面内方向沿着厚度方向z。基层21的厚度大于支撑部件10的厚度。由此,能够降低厚度方向z、与厚度方向z正交的一方向(在半导体装置A20的示例中为第一方向x)双方的导电部件20的每单位长度内的热电阻。石墨的面内方向的热传导率为铜的热传导率(398W/(m·K))的约4倍。因此,与前述半导体装置A10相比,能够进一步提高半导体装置A20的散热性。
由石墨构成的基层21的密度为铜的密度(8.92g/cm3)的约1/4。因此,能够使半导体装置A20的重量比半导体装置A10小。
〔第三实施方式〕
参照图18~图29对本公开第三实施方式的半导体装置A30进行说明。在这些图中,对于和前述半导体装置A10相同或类似的要素标记相同的符号并省略重复说明。在此,图20为了便于理解而透过了封装树脂60。图21为了便于理解而相对于图20而言进一步透过了第二输入端子34(详情后述)和多个导通部件50。在图20和图21中将透过的这些要素用虚拟线表示。
半导体装置A30具备:支撑部件10、第一金属层19、导电部件20、第二金属层29、第一输入端子33、第二输入端子34、输出端子35、绝缘材39、多个半导体元件40、多个导通部件50、和封装树脂60。此外,半导体装置A30还具备:一对绝缘层23、一对栅极层24、一对检测层25、一对栅极端子36、一对检测端子37、多个虚端子38、多个栅极引线51、多个检测引线52、一对第一引线531和一对第二引线532。在这些结构中,除了第一金属层19、导电部件20和第二金属层29以外的结构与上述半导体装置A10中的结构不同。如图18和图19所示,半导体装置A30沿着厚度方向z观察呈矩形状。
如图20所示,支撑部件10的第二支撑板12仅具有第一区域121和第二区域122。如图26和图27所示,第一金属层19将第一区域121和第二区域122各自的支撑面10A覆盖。第一导电部201与第一区域121接合。第二导电部202与第二区域122接合。
第一金属层19和第二金属层29各自的结构与前述半导体装置A10的这些结构(参照图9A和图9B)相同。此外,在半导体装置A30中,也可以使第一金属层19和第二金属层29各自的结构与前述半导体装置A11的这些结构(参照图10A和图10B)相同。
如图21所示,一对绝缘层23相对于第一导电部201和第二导电部202的主面20A独立配置。一对绝缘层23在第一方向x上彼此分离。一对绝缘层23呈在第二方向y上延伸的帯状。位于第一方向x的一侧的绝缘层23配置于第一导电部201的主面20A。位于第一方向x的另一侧的绝缘层23配置于第二导电部202的主面20A。
如图21所示,一对栅极层24在一对绝缘层23上配置。一对栅极层24呈在第二方向y上延伸的帯状。
如图21所示,一对检测层25在一对绝缘层23上配置。一对检测层25呈在第二方向y上延伸的帯状。在位于第一方向x的一侧的绝缘层23中,检测层25位于比栅极层24靠第一方向x的一侧。在位于第一方向x的另一侧的绝缘层23中,检测层25位于比栅极层24靠第一方向x的另一侧。
如图20和图21所示,第一输入端子33和第二输入端子34位于第一方向x的一侧。第一输入端子33和第二输入端子34被输入作为电力变换对象的直流电力。第一输入端子33是正极(P端子)。第二输入端子34是负极(N端子)。如图27所示,第二输入端子34在厚度方向z上相对于第一输入端子33、第一导电部201和第二导电部202的任一而言分离配置。第一输入端子33和第二输入端子34是由铜或铜合金构成的金属板。
如图21所示,第一输入端子33具有第一连接部331和第一端子部332。在第一输入端子33中,第一连接部331和第一端子部332的交界面是沿着第二方向y和厚度方向z的面,并且相当于包含位于第一方向x的一侧的封装树脂60的第一侧面63A的面。第一连接部331整体被封装树脂60覆盖。第一连接部331的第一方向x的另一侧呈梳齿状。该梳齿状的部分通过焊锡接合或者超音波接合等与第一导电部201的主面20A连接。由此,第一输入端子33与第一导电部201导通。
如图21和图22所示,第一端子部332从封装树脂60向第一方向x的一侧延伸。沿着厚度方向z观察,第一端子部332呈矩形状。第一端子部332的第二方向y的两侧被封装树脂60覆盖。除此以外的第一端子部332的部分从封装树脂60露出。由此,第一输入端子33被第一导电部201和封装树脂60双方支撑。
如图20所示,第二输入端子34具有第二连接部341和第二端子部342。第二输入端子34的第二连接部341和第二端子部342的交界面与前述第一输入端子33的第一连接部331和第一端子部332的交界面相同。
如图20所示,第二连接部341具有连结部341A和多个延伸部341B。连结部341A呈在第二方向y上延伸的帯状。连结部341A的第一方向x的一侧与第二端子部342相连。多个延伸部341B从连结部341A朝向第一方向x的另一侧延伸。多个延伸部341B呈在第一方向x上延伸的帯状。如图29所示,多个延伸部341B的位于第一方向x的另一侧的端部通过接合层49与多个第二元件402(详情后述)的第一电极41连接。由此,第二输入端子34与多个第二元件402的第一电极41导通。
如图19和图20所示,第二端子部342从封装树脂60向第一方向x的一侧延伸。沿着厚度方向z观察,第二端子部342呈矩形状。第二端子部342的第二方向y的两侧被封装树脂60覆盖。除此以外的第二端子部342的部分从封装树脂60露出。如图20和图21所示,沿着厚度方向z观察,第二端子部342与第一输入端子33的第一端子部332重叠。如图27所示,第二端子部342相对于第一端子部332而言,在厚度方向z上向支撑部件10的支撑面10A所朝向的一侧分离。此外,在半导体装置A30的示例中,第二端子部342的形状与第一端子部332的形状相同。
如图27所示,绝缘材39在厚度方向z上位于第一输入端子33和第二输入端子34之间。绝缘材39是具有电绝缘性的平板。作为绝缘材39的一例,可举出绝缘纸。沿着厚度方向z观察,第一输入端子33整体与绝缘材39重叠。在第二输入端子34中,沿着厚度方向z观察,第二连接部341的连结部341A的一部分、第二端子部342的整体与绝缘材39重叠。沿着厚度方向z观察与绝缘材39重叠的这些部分与绝缘材39相接。由此,第一输入端子33和第二输入端子34彼此绝缘。绝缘材39的一部(第一方向x的另一侧、和第二方向y的两侧)被封装树脂60覆盖。
如图21和图27所示,绝缘材39具有介在部391和延伸部392。介在部391夹在第一输入端子33的第一端子部332、和第二输入端子34的第二端子部342之间。延伸部392从介在部391相对于第一端子部332和第二端子部342而言进一步朝向第一方向x的一侧延伸。延伸部392的第二方向y的两侧被封装树脂60覆盖。
如图20所示,输出端子35位于第一方向x的另一侧。通过多个半导体元件40进行了电力变换的交流电力从输出端子35输出。输出端子35是由铜或铜合金构成的金属板。输出端子35具有连接部351和端子部352。连接部351和端子部352的交界面是沿着第二方向y和厚度方向z的面,并且是包含位于第一方向x的另一侧的封装树脂60的第一侧面63A的面。连接部351整体被封装树脂60覆盖。在连接部351的第一方向x的一侧设有梳齿部351A。梳齿部351A通过焊锡接合或超音波接合等与第二导电部202的主面20A连接。由此,输出端子35与第二导电部202导通。如图19和图20所示,端子部352从封装树脂60向第一方向x的另一侧延伸。沿着厚度方向z观察,端子部352呈矩形状。端子部352的第二方向y的两侧被封装树脂60覆盖。除此以外的端子部352的部分从封装树脂60露出。由此,输出端子35被第二导电部202和封装树脂60双方支撑。
多个半导体元件40包含:多个第一元件401、多个第二元件402。多个第一元件401和多个第二元件402均与前述半导体装置A10的半导体元件40相同。因此,省略对多个第一元件401和多个第二元件402各自的结构的说明。
如图20所示,多个第一元件401与第一导电部201的主面20A接合。多个第一元件401沿着第二方向y以预定的间隔排列。多个第一元件401构成了半导体装置A30的上臂电路。在第一导电部201中,多个第一元件401位于比绝缘层23靠第一方向x的另一侧。
如图20所示,多个第二元件402与第二导电部202的主面20A接合。多个第二元件402沿着第二方向y以预定的间隔排列。多个第二元件402构成了半导体装置A30的下臂电路。在第二导电部202中,多个第二元件402位于比绝缘层23靠第一方向x的一侧。
如图20所示,多个第一元件401和多个第二元件402作为其整体而言交错配置于导电部件20。在半导体装置A30的示例中,第一元件401和第二元件402各自的个数是四个。第一元件401和第二元件402各自的个数不限于本结构,能够根据半导体装置A30所要求的性能自由设定。
如图26和图28所示,多个导通部件50与多个第一元件401的第一电极41、第二导电部202的主面20A连接。多个导通部件50的位于第一方向x的一侧的端部通过接合层49与多个第一元件401的第一电极41连接。多个导通部件50的位于第一方向x的另一侧的端部通过接合层49与第二导电部202的主面20A连接。由此,多个第一元件401的第一电极41与第二导电部202导通。
多个栅极引线51包含:多个第一栅极引线511、多个第二栅极引线512。如图20所示,多个第一栅极引线511与多个第一元件401的栅极电极43、位于第一导电部201的主面20A上的一方的栅极层24连接。由此,多个第一元件401的栅极电极43与该栅极层24导通。如图20所示,多个第二栅极引线512与多个第二元件402的栅极电极43、位于第二导电部202的主面20A上的另一方的栅极层24连接。由此,多个第二元件402的栅极电极43与该栅极层24导通。
多个检测引线52包含:多个第一检测引线521、多个第二检测引线522。如图20所示,多个第一检测引线521与多个第一元件401的第一电极41、位于第一导电部201的主面20A上的一方的检测层25连接。由此,多个第一元件401的第一电极41与该检测层25导通。如图20所示,多个第二检测引线522与多个第二元件402的第一电极41、位于第二导电部202的主面20A上的另一方的检测层25连接。由此,多个第二元件402的第一电极41与该检测层25导通。
如图20所示,一对栅极端子36、一对检测端子37和多个虚端子38在第二方向y上与导电部件20相邻。这些端子沿着第一方向x排列。在半导体装置A30中,一对栅极端子36、一对检测端子37和多个虚端子38均由同一导线框构成。
如图20所示,一对栅极端子36的其中一方与第一导电部201相邻且另一方与第二导电部202相邻。一对栅极端子36分别被施加用于驱动多个第一元件401和多个第二元件402的其中一方的栅极电压。
如图20所示,一对检测端子37在第一方向x上与一对栅极端子36相邻。从一对检测端子37分别施加向与多个第一元件401和多个第二元件402的其中一方对应的多个第一电极41施加的电压(与源极电流对应的电压)。
如图20所示,多个虚端子38在第一方向x上相对于一对检测端子37而言位于与一对栅极端子36相反的一侧。在半导体装置A30的示例中,虚端子38的个数为六个。其中,三个虚端子38位于第一方向x的一侧。其余三个虚端子38位于第一方向x的另一侧。此外,虚端子38的个数不限于本结构。此外,在半导体装置A30中,也可以是不具备多个虚端子38的结构。多个虚端子38各自具有连接部381和端子部382。连接部381被封装树脂60覆盖。由此,多个虚端子38被封装树脂60支撑。此外,也可以在连接部381的表面施加例如银镀层。端子部382与连接部381相连,并且从封装树脂60露出(参照图20和图25)。如图23和图24所示,沿着第一方向x观察,端子部382呈L字状。此外,一对栅极端子36的端子部362、和一对检测端子37的端子部372各自的形状与端子部382的形状相同。
如图20所示,一对第一引线531与一对栅极端子36、一对栅极层24分别连接。由此,与第一导电部201相邻的一方的栅极端子36与多个第一元件401的栅极电极43导通。与第二导电部202相邻的另一方的栅极端子36与多个第二元件402的栅极电极43导通。
如图20所示,一对第二引线532与一对检测端子37、一对检测层25分别连接。由此,与第一导电部201相邻的一方的检测端子37与多个第一元件401的第一电极41导通。与第二导电部202相邻的另一方的检测端子37与多个第一元件401的第一电极41导通。
如图26和图27所示,封装树脂60将支撑部件10、第一输入端子33、第二输入端子34和输出端子35各自的一部分、导电部件20、多个半导体元件40和多个导通部件50覆盖。封装树脂60将一对绝缘层23、一对栅极层24、一对检测层25、多个栅极引线51、多个检测引线52、一对第一引线531和一对第二引线532覆盖。此外,封装树脂60将一对栅极端子36、一对检测端子37和多个虚端子38各自的一部分覆盖。如图19~图25所示,封装树脂60具有顶面61、底面62、一对第一侧面63A、一对第二侧面63B、多个第三侧面63C、多个第四侧面63D、多个切口部63E和多个安装孔64。
如图26和图27所示,顶面61在厚度方向z上朝向与支撑部件10的支撑面10A相同的一侧。底面62在厚度方向z上朝向与顶面61相反的一侧。如图22所示,从底面62露出了底板13(支撑部件10)的底面10B。底面62呈围绕底板13的框状。
如图19~图24、和图27所示,一对的第一侧面63A与顶面61和底面62双方相连,并且朝向第一方向x。从位于第一方向x的一侧的第一侧面63A起,第一输入端子33的第一端子部332、和第二输入端子34的第二端子部342朝向第一方向x的一侧延伸。从位于第二方向y的另一侧的第一侧面63A起,输出端子35的端子部352朝向第一方向x的另一侧延伸。这样,第一输入端子33和第二输入端子34各自的一部分在第一方向x的一侧从封装树脂60露出。相应地,输出端子35的一部分在第一方向x的另一侧从封装树脂60露出。
如图19~图25所示,一对第二侧面63B与顶面61和底面62双方相连,并且朝向第二方向y。一对栅极端子36的端子部362、一对检测端子37的端子部372、和多个虚端子38的端子部382从一对第二侧面63B的任意一方露出。
如图19~图24、和图27所示,多个第三侧面63C与顶面61和底面62双方相连,并且朝向第二方向y。多个第三侧面63C包含:位于第一方向x的一侧的一对第三侧面63C、以及位于第一方向x的另一侧的一对第三侧面63C。分别在第一方向x的一侧和另一侧,一对第三侧面63C在第二方向y上对置。另外,分别在第一方向x的一侧和另一侧,一对第三侧面63C与第一侧面63A的第二方向y的两端相连。
如图19~图27所示,多个第四侧面63D与顶面61和底面62双方相连,并且朝向第一方向x。多个第四侧面63D在第一方向x上位于比一对第一侧面63A靠半导体装置A10的外侧。多个第四侧面63D包含:位于第一方向x的一侧的一对第四侧面63D、以及位于第一方向x的另一侧的一对第四侧面63D。分别在第一方向x的一侧和另一侧,一对第四侧面63D的第二方向y的两端与一对第二侧面63B、一对第三侧面63C相连。
如图19和图22所示,多个切口部63E各自位于第一侧面63A和第三侧面63C的交界。沿着厚度方向z观察,多个切口部63E均相对于第一方向x和第二方向y双方倾斜。
如图26所示,多个安装孔64在厚度方向z上从顶面61到底面62贯通封装树脂60。多个安装孔64用于将半导体装置A30安装于散热器时。如图19和图22所示,沿着厚度方向z观察,多个安装孔64的孔缘呈圆形状。多个安装孔64沿着厚度方向z观察位于封装树脂60的四角。
接下来,对半导体装置A30的作用效果进行说明。
半导体装置A30具备第一金属层19和第二金属层29。第一金属层19将支撑部件10的支撑面10A覆盖。第二金属层29将导电部件20的背面20B覆盖。第一金属层19和第二金属层29通过固相扩散彼此接合。因此,采用半导体装置A30也能够提高其散热性。
在半导体装置A30中,多个半导体元件40包含:多个第一元件401、以及多个第二元件402。多个第一元件401与第一导电部201接合。多个第二元件402与第二导电部202接合。第一金属层19和第二金属层29彼此通过固相扩散相互接合,因此能够使第一导电部201和第二导电部202各自的厚度大于第二支撑板12的厚度。因此,接合有多个半导体元件40的导电部件20全部能够提高其散热性。
第一输入端子33和第二输入端子34位于第一方向x的一侧。第一输入端子33和第二输入端子34在厚度方向z上彼此分离。沿着厚度方向z观察,第二输入端子34的至少一部(第二端子部342)与第一输入端子33重叠。由此,在使用半导体装置A30时,能够利用从第二输入端子34产生的磁场来降低第一输入端子33的自感,从而抑制半导体装置A30的电力变换效率的降低。
〔第四实施方式〕
参照图30~图35对本公开第四实施方式的半导体装置A40进行说明。在这些图中,对于和前述半导体装置A10相同或类似的要素标记相同的符号并省略重复说明。在此,图30为了便于理解而透过了封装树脂60。将透过的封装树脂60用虚拟线表示。
半导体装置A40的支撑部件10和导电部件20的结构与前述半导体装置A30中的这些结构不同。
在半导体装置A40中,支撑部件10是绝缘板。如图30~图34所示,该绝缘板包含支撑面10A和底面10B。如图32和图33所示,第一金属层19将沿着厚度方向z观察与导电部件20重叠的支撑部件10的支撑面10A的区域覆盖。除此以外的支撑部件10的结构与前述半导体装置A20的结构相同,因此省略这里的说明。
如图32~图35所示,导电部件20具有基层21、第一配线层221和第二配线层222。基层21占据了导电部件20的体积的大半。基层21的组成含碳。在半导体装置A40中,基层21由石墨构成。第一配线层221包含主面20A且与基层21层叠。第二配线层222包含背面20B且与基层21层叠。因此,基层21夹在第一配线层221和第二配线层222之间。除此以外的导电部件20的结构与前述半导体装置A20的结构相同,因此省略这里的说明。
第一金属层19和第二金属层29各自的结构与前述半导体装置A20的这些结构(参照图17)相同。
接下来,对半导体装置A40的作用效果进行说明。
半导体装置A40具备第一金属层19和第二金属层29。第一金属层19将支撑部件10的支撑面10A的至少一部分覆盖。第二金属层29将导电部件20的背面20B覆盖。第一金属层19和第二金属层29通过固相扩散彼此接合。因此,采用半导体装置A40也能够提高其散热性。
在半导体装置A40中,支撑部件10是绝缘板。导电部件20具有:包含主面20A的第一配线层221、包含背面20B的第二配线层222、以及位于第一配线层221和第二配线层222之间的基层21。基层21由石墨构成。该石墨的面内方向沿着厚度方向z。基层21的厚度大于支撑部件10的厚度。因此,与前述半导体装置A30相比,能够进一步提高半导体装置A40的散热性。此外,由石墨构成的基层21的密度为铜的密度的约1/4。因此,能够使半导体装置A40的重量小于半导体装置A30。
〔第五实施方式〕
参照图36~图39对本公开第五实施方式的半导体装置A50进行说明。在这些图中,对于和前述半导体装置A10相同或类似的要素标记相同的符号并省略重复说明。在此,图36为了便于理解而透过了封装树脂60。将透过的封装树脂60用虚拟线表示。
半导体装置A50的支撑部件10的结构与前述半导体装置A30中的结构不同。
如图36~图39所示,支撑部件10包含在第一方向x上彼此分离的第一支撑部101和第二支撑部102。第一支撑部101和第二支撑部102各自具有第一支撑板11、第二支撑板12和底板13。如图38和图39所示,第一金属层19将第一支撑部101和第二支撑部102各自的支撑面10A覆盖。第一导电部201与第一支撑部101的第二支撑板12接合。第二导电部202与第二支撑部102的第二支撑板12接合。
如图37所示,第一支撑部101和第二支撑部102各自的底面10B从封装树脂60的底面62露出。沿着厚度方向观察,底面62的一部分位于第一支撑部101的底面10B、和第二支撑部102的底面10B之间。
接下来,对半导体装置A50的作用效果进行说明。
半导体装置A50具备第一金属层19和第二金属层29。第一金属层19将支撑部件10的支撑面10A覆盖。第二金属层29将导电部件20的背面20B覆盖。第一金属层19和第二金属层29通过固相扩散彼此接合。因此,采用半导体装置A50也能够提高其散热性。
在半导体装置A50中,支撑部件10包含第一支撑部101和第二支撑部102。第一支撑部101和第二支撑部102彼此分离。第一导电部201与第一支撑部101接合。第二导电部202与第二支撑部102接合。在半导体装置A50的制造中形成封装树脂60时,会因封装树脂60的收缩而在导体装置A50中产生厚度方向z的翘曲。通过采用这种结构,从而能够抑制该翘曲。
〔第六实施方式〕
参照图40~图43B对本公开第五实施方式的半导体装置A60进行说明。在这些图中,对于和前述半导体装置A10相同或类似的要素标记相同的符号并省略重复说明。在此,图40与图8对应。
半导体装置A60的导电部件20和第二金属层29的结构与前述半导体装置A10中的结构不同。
如图40所示,导电部件20(第一导电部201和第二导电部202)具有主体层20D和接合层20E。主体层20D包含主面20A。主体层20D是由铜或铜合金构成的金属板。接合层20E包含背面20B且与主体层20D层叠。接合层20E的组成含银。接合层20E的厚度小于主体层20D的厚度。接合层20E通过相对于接合层20E进行成膜而形成。成膜方法例如可举出溅射法、或者真空蒸镀。
如图41所示,第二金属层29具有第一层291、一对第二层292、和一对第三层293。第一层291的组成含铝。第一层291例如是铝箔。第一层291的厚度t1大于半导体装置A10的第一层291的厚度t1。一对第二层292在厚度方向z上位于第一层291的两侧。一对第二层292的组成含银。第一层291的维氏硬度比一对第二层292各自的维氏硬度小。相应地,第一层291的厚度比一对第二层292各自的厚度大。一对第三层293夹在第一层291、和一对第二层292各自之间。一对第三层293的组成含镍。一对第三层293各自的厚度t3比第一层291的厚度t1、和一对第二层292各自的厚度t2小。第二金属层29可通过相对于第一层291的两面依次进行一对第三层293、一对第二层292的成膜而形成。成膜方法例如可举出溅射法、或者真空蒸镀。
如图41所示,第一金属层19与图9B所示半导体装置A10的情况同样地仅由单层构成。此时,第一金属层19的组成含银。
如图41所示,在半导体装置A60中,导电部件20的背面20B、和一对第二层292的其中一方的该第二层292通过固相扩散彼此接合。由此,在导电部件20的接合层20E、和一方的该第二层292之间形成了空隙29A。相应地,第一金属层19、和一对第二层292的其中另一方的该第二层292通过固相扩散彼此接合。由此,在第一金属层19、和另一方的该第二层292之间形成了空隙19A。
如图42A和图42B所示,就一对第二层292的其中一方的该第二层292的每单位体积中的空隙29A的体积而言,在沿着厚度方向z观察时的一方的该第二层292的中央部、和沿着厚度方向z观察时的一方的该第二层292的周缘部有所不同。该中央部的一方的该第二层292的每单位体积中的空隙29A的体积小于该周缘部的一方的该第二层292的每单位体积中的空隙29A的体积。
如图43A和图43B所示,就一对第二层292的其中另一方的该第二层292的每单位体积中的空隙19A的体积而言,在沿着厚度方向z观察时的另一方的该第二层292的中央部、和沿着厚度方向z观察时的另一方的该第二层292的周缘部有所不同。该中央部的另一方的该第二层292的每单位体积中的空隙19A的体积小于该周缘部的另一方的该第二层292的每单位体积中的空隙19A的体积。
如图43B所示,沿着厚度方向z观察,在与第二金属层29的周缘部相接的第一金属层19形成有沿着厚度方向z弯曲的第一弯曲部19B。在半导体装置A60中,第一弯曲部19B在厚度方向z上朝向第二金属层29所在侧弯曲。此外,沿着厚度方向z观察,在第二金属层29的一对第二层292中的、与第一金属层19相接的该第二层292的周缘部形成有沿着厚度方向z弯曲的第二弯曲部29B。在厚度方向z上,第二弯曲部29B弯曲的朝向与第一弯曲部19B弯曲的朝向相同。在半导体装置A60中,第二弯曲部29B在厚度方向z上朝向第二金属层29的第一层291所在侧弯曲。
如图42B所示,沿着厚度方向z观察,在第二金属层29的一对第二层292中的、与导电部件20的接合层20E相接的该第二层292的周缘部也形成有第二弯曲部29B。在半导体装置A60中,该第二弯曲部29B在厚度方向z上朝向导电部件20所在侧弯曲。
接下来,对半导体装置A60的作用效果进行说明。
半导体装置A60具备第一金属层19和第二金属层29。第一金属层19将支撑部件10的支撑面10A覆盖。第二金属层29将导电部件20的背面20B覆盖。第一金属层19和第二金属层29通过固相扩散彼此接合。因此,采用半导体装置A60也能够提高其散热性。
本公开不限于前述实施方式。本公开各部的具体结构可以进行多种设计变更。
本公开的多种实施方式可以规定为以下的附记。
附记1.一种半导体装置,其具备:
支撑部件,其具有朝向厚度方向的支撑面;
导电部件,其具有在所述厚度方向上朝向与所述支撑面相同的一侧的主面、和朝向与所述主面相反的一侧的背面,并且以所述背面与所述支撑面对置的方式与所述支撑部件接合;以及
半导体元件,其与所述主面接合,
还具备覆盖所述支撑面的至少一部分的第一金属层、和覆盖所述背面的第二金属层,
所述第一金属层和所述第二金属层通过固相扩散彼此接合。
附记2.根据附记1所述的半导体装置,其中,
所述第二金属层具有:第一层;其覆盖所述背面;以及第二层,其在所述厚度方向上相对于所述第一层位于与所述导电部件相反的一侧,
所述第一金属层和所述第二层通过固相扩散彼此接合。
附记3.根据附记2所述的半导体装置,其中,
所述第一层的厚度比所述第二层的厚度大,
所述第一层的维氏硬度比所述第二层的维氏硬度小。
附记4.根据附记3所述的半导体装置,其中,
沿着所述厚度方向观察,在所述导电部件的周缘部形成有从所述背面向所述厚度方向凹陷的凹部,
所述凹部与所述第一层相接。
附记5.根据附记4所述的半导体装置,其中,
沿着所述厚度方向观察,所述第一层的中央部的最大厚度比所述第一层的周缘部的最大厚度小。
附记6.根据附记2至5的任一所述的半导体装置,其特征在于,
所述第一金属层具有第三层,该第三层夹在所述第一层和所述第二层之间,
所述第三层的厚度比所述第一层和所述第二层各自的厚度小。
附记7.根据附记1所述的半导体装置,其中,
所述第二金属层具有:第一层;以及一对第二层,其在所述厚度方向上位于所述第一金属层的两侧,
所述背面与所述一对第二层中的一方的相应第二层通过固相扩散彼此接合,
所述第一金属层与所述一对第二层中的另一方的相应第二层通过固相扩散彼此接合。
附记8.根据附记7所述的半导体装置,其中,
所述第一层的厚度比所述一对第二层各自的厚度大,
所述第一层的维氏硬度比所述一对第二层各自的维氏硬度小。
附记9.根据附记8所述的半导体装置,其中,
沿着所述厚度方向观察,在与所述第二金属层的周缘部相接的第一金属层形成有向所述厚度方向弯曲的第一弯曲部。
附记10.根据附记9所述的半导体装置,其中,
沿着所述厚度方向观察,在所述一对第二层的至少任一个的周缘部形成有向所述厚度方向弯曲的第二弯曲部,
在所述厚度方向上,所述第二弯曲部弯曲的朝向与所述第一弯曲部弯曲的朝向相同。
附记11.根据附记7至10的任一所述的半导体装置,其中,
所述第一金属层具有一对第三层,该一对第三层夹在所述第一层和所述一对第二层各自之间,
所述一对第三层各自的厚度比所述第一层和所述一对第二层各自的厚度小。
附记12.根据附记2至11的任一所述的半导体装置,其中,
所述支撑部件包含具有电绝缘性的第一支撑板和所述支撑面,并且具有与所述第一支撑板层叠的金属制的第二支撑板,
所述导电部件是金属板,
所述导电部件的厚度比所述第二支撑板的厚度大。
附记13.根据附记2或3所述的半导体装置,其中,
所述支撑部件是绝缘板,
所述导电部件具有:包含所述主面的第一配线层;包含所述背面的第二配线层;以及位于所述第一配线层和所述第二配线层之间并且组成含碳的基层,
所述基层的厚度比所述支撑部件的厚度大。
附记14.根据附记13所述的半导体装置,其中,
所述基层由石墨构成,
所述石墨的面内方向沿着所述厚度方向。
附记15.根据附记12至14任一所述的半导体装置,其中,
所述支撑部件具有朝向与所述支撑面相反的一侧的底面,
还具备封装树脂,该封装树脂覆盖所述导电部件及所述半导体元件和所述支撑部件的一部分,
所述底面从所述封装树脂露出。
Claims (16)
1.一种半导体装置,其特征在于,具备:
支撑部件,其具有朝向厚度方向的支撑面;
导电部件,其具有在所述厚度方向上朝向与所述支撑面相同的一侧的主面、和朝向与所述主面相反的一侧的背面,并且以所述背面与所述支撑面对置的方式与所述支撑部件接合;以及
半导体元件,其与所述主面接合,
还具备覆盖所述支撑面的至少一部分的第一金属层、和覆盖所述背面的第二金属层,
所述第一金属层和所述第二金属层彼此通过固相扩散接合,
所述支撑部件包含具有电绝缘性的第一支撑板和所述支撑面,并且具有与所述第一支撑板层叠的金属制的第二支撑板,
所述导电部件是金属板。
2.根据权利要求1所述的半导体装置,其特征在于,
所述第二金属层具有:第一层;其覆盖所述背面;以及第二层,其在所述厚度方向上相对于所述第一层位于与所述导电部件相反的一侧,
所述第一金属层和所述第二层通过固相扩散彼此接合。
3.根据权利要求2所述的半导体装置,其特征在于,
所述第一层的厚度比所述第二层的厚度大,
所述第一层的维氏硬度比所述第二层的维氏硬度小。
4.根据权利要求3所述的半导体装置,其特征在于,
沿着所述厚度方向观察,在所述导电部件的周缘部形成有从所述背面向所述厚度方向凹陷的凹部,
所述凹部与所述第一层相接。
5.根据权利要求4所述的半导体装置,其特征在于,
沿着所述厚度方向观察,所述第一层的中央部的最大厚度比所述第一层的周缘部的最大厚度小。
6.根据权利要求2至5中任一项所述的半导体装置,其特征在于,
所述第一金属层具有第三层,该第三层夹在所述第一层和所述第二层之间,
所述第三层的厚度比所述第一层和所述第二层各自的厚度小。
7.根据权利要求1所述的半导体装置,其特征在于,
所述第二金属层具有:第一层;以及一对第二层,其在所述厚度方向上位于所述第一金属层的两侧,
所述背面与所述一对第二层中的一方的相应第二层通过固相扩散彼此接合,
所述第一金属层与所述一对第二层中的另一方的相应第二层通过固相扩散彼此接合。
8.根据权利要求7所述的半导体装置,其特征在于,
所述第一层的厚度比所述一对第二层各自的厚度大,
所述第一层的维氏硬度比所述一对第二层各自的维氏硬度小。
9.根据权利要求8所述的半导体装置,其特征在于,
沿着所述厚度方向观察,在与所述第二金属层的周缘部相接的第一金属层形成有向所述厚度方向弯曲的第一弯曲部。
10.根据权利要求9所述的半导体装置,其特征在于,
沿着所述厚度方向观察,在所述一对第二层的至少任一个的周缘部形成有向所述厚度方向弯曲的第二弯曲部,
在所述厚度方向上,所述第二弯曲部弯曲的朝向与所述第一弯曲部弯曲的朝向相同。
11.根据权利要求7至10中任一项所述的半导体装置,其特征在于,
所述第一金属层具有一对第三层,该一对第三层夹在所述第一层和所述一对第二层各自之间,
所述一对第三层各自的厚度比所述第一层和所述一对第二层各自的厚度小。
12.根据权利要求1所述的半导体装置,其特征在于,
所述导电部件的厚度比所述第二支撑板的厚度大,
所述半导体元件是采用以碳化硅为主的半导体材料构成的MOSFET。
13.根据权利要求1所述的半导体装置,其特征在于,
所述支撑部件具有朝向与所述支撑面相反的一侧的底面,
还具备封装树脂,该封装树脂覆盖所述导电部件及所述半导体元件和所述支撑部件的一部分,
所述底面从所述封装树脂露出。
14.一种半导体装置,其特征在于,具备:
支撑部件,其具有朝向厚度方向的支撑面;
导电部件,其具有在所述厚度方向上朝向与所述支撑面相同的一侧的主面、和朝向与所述主面相反的一侧的背面,并且以所述背面与所述支撑面对置的方式与所述支撑部件接合;以及
半导体元件,其与所述主面接合,
还具备覆盖所述支撑面的至少一部分的第一金属层、和覆盖所述背面的第二金属层,
所述第一金属层和所述第二金属层彼此通过固相扩散接合,
所述支撑部件是绝缘板,
所述导电部件具有:包含所述主面的第一配线层;包含所述背面的第二配线层;以及位于所述第一配线层和所述第二配线层之间并且组成含碳的基层,
所述基层的厚度比所述支撑部件的厚度大。
15.根据权利要求14所述的半导体装置,其特征在于,
所述基层由石墨构成,
所述石墨的面内方向沿着所述厚度方向。
16.根据权利要求14所述的半导体装置,其特征在于,
所述第二金属层具有覆盖所述背面的第一层、和相对于所述第一层位于与所述导电部件相反的一侧的第二层,
所述第一金属层和所述第二层彼此通过固相扩散接合。
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JP2014022579A (ja) * | 2012-07-19 | 2014-02-03 | Rohm Co Ltd | パワーモジュール半導体装置 |
CN105189109A (zh) * | 2013-03-14 | 2015-12-23 | 三菱综合材料株式会社 | 接合体、功率模块用基板及自带散热器的功率模块用基板 |
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