CN112926719A

CN112926719A - Dynamic encryption chip and underground marker

Info

Publication number: CN112926719A
Application number: CN202110344943.6A
Authority: CN
Inventors: 李成龙; 李丽杰
Original assignee: Shenzhen Sotrowin Technology Co ltd
Current assignee: Shenzhen Sotrowin Technology Co ltd
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2021-06-08

Abstract

The application relates to a dynamic encryption chip and an underground marker. The dynamic encryption chip comprises: the dynamic encryption chip comprises a rectification module used for generating a power supply required by the dynamic encryption chip, a frequency division module used for generating a clock required by the dynamic encryption chip, a control module used for controlling the working flow of the dynamic encryption chip in a general mode, a storage module used for storing chip data and an encryption module used for generating a random number and encrypting the chip data. In the application, the random number is added to the inside of the dynamic encryption chip to encrypt the chip data of the encryption module. After the dynamic encryption chip obtains the power supply and the frequency, the chip data is encrypted by combining the random number generated by the encryption module. After the dynamic encryption processing of the dynamic encryption chip, the retransmitted chip data has higher security and is not easy to be recorded.

Description

Dynamic encryption chip and underground marker

Technical Field

The application relates to the field of electronic communication, in particular to a dynamic encryption chip and an underground marker.

Background

The conventional rf transmission chip is generally a wireless sensing chip. After the wireless sensing chip obtains the power supply and the frequency, the original data stored in the chip can be directly transmitted to the receiver, so that the transmitted data has no safety and is easy to record.

Disclosure of Invention

Therefore, it is necessary to provide a dynamic encryption chip and an underground marker for solving the problems that the conventional wireless sensing chip directly transmits the original data stored in the chip to the receiver after obtaining the power and the frequency, so that the transmitted data has no security and is easy to be recorded.

A dynamic cryptographic chip, comprising:

the rectifier module is used for generating a power supply required by the dynamic encryption chip;

the frequency eliminating module is connected with the rectifying module in parallel and is used for generating a clock required by the dynamic encryption chip;

the control module is respectively electrically connected with the rectifying module and the frequency eliminating module and is used for controlling the working flow of the dynamic encryption chip in a general mode;

the storage module is electrically connected with the control module and is used for storing chip data;

and the encryption module is respectively electrically connected with the control module and the storage module, and the encryption module is used for encrypting the chip data by adopting an advanced encryption standard.

In one embodiment, the encryption module comprises:

a random number generator for generating random numbers of different word lengths;

the input end of the encryption processor is respectively and electrically connected with the random number generator and the storage module and is used for encrypting the random number and the chip data by adopting an advanced encryption standard;

and the encryption result buffer is electrically connected with the output end of the encryption processor and used for buffering the encrypted chip data.

In one embodiment, the data stored in the memory module is 128 bits;

a random number of 8-bit word length is generated in the random number generator.

In one embodiment, the dynamic encryption chip further includes:

and the coding module is electrically connected with the output end of the encryption result buffer and used for converting the encrypted chip data into the encrypted data in the radio frequency output format.

In one embodiment, the dynamic encryption chip further includes:

and the transmitting module is electrically connected with the encoding module and is used for transmitting the encrypted data in the radio frequency output format.

In one embodiment, the data structure stored in the storage module includes:

a 13-bit start code;

an 88-bit data code;

22 bits of horizontal even parity check codes, wherein every 4 bits of the data codes form a row, and each even row comprises one bit of the horizontal even parity check codes;

4 bits column odd parity check code, every 20 bits of said data code make up a row, each odd column includes a bit of said column odd parity check code;

a 1-bit end code.

In one embodiment, the waveform output by the dynamic encryption chip is an asymmetric waveform, and a symbol representing '0' and a symbol representing '1' in the asymmetric waveform are asymmetric.

In one embodiment, the dynamic encryption chip outputs a waveform in which a symbol representing "0" has one transition among 2 levels with equal periods and a symbol representing "1" has three transitions among 4 levels with equal periods.

In one embodiment, the first jump is a high-to-low jump, and the first jump of the three jumps is a low-to-high jump.

The application also provides an underground marker, which comprises the dynamic encryption chip.

The application provides a dynamic encryption chip and an underground marker. The dynamic encryption chip comprises: the dynamic encryption chip comprises a rectification module used for generating a power supply required by the dynamic encryption chip, a frequency division module used for generating a clock required by the dynamic encryption chip, a control module used for controlling the working flow of the dynamic encryption chip in a general mode, a storage module used for storing chip data and an encryption module used for generating a random number and encrypting the chip data. The frequency eliminating module is connected with the rectifying module in parallel. The control module is respectively electrically connected with the rectifying module and the frequency dividing module. The storage module is electrically connected with the control module. The encryption module is electrically connected with the control module and the storage module respectively. In the application, the random number is added to the inside of the dynamic encryption chip to encrypt the chip data of the encryption module. After the dynamic encryption chip obtains the power supply and the frequency, the chip data is encrypted by combining the random number generated by the encryption module. After the dynamic encryption processing of the dynamic encryption chip, the retransmitted chip data has higher security and is not easy to be recorded.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic block diagram of the dynamic encryption chip according to an embodiment of the present application.

Fig. 2 is a circuit diagram of the rectifier module according to an embodiment of the present application.

Fig. 3 is a schematic diagram illustrating an operating principle of the frequency dividing module according to an embodiment of the present application.

Fig. 4 is a schematic internal structural diagram of the control module according to an embodiment of the present application.

Fig. 5 is a schematic structural diagram of the encryption module according to an embodiment of the present application.

Fig. 6 is a schematic diagram of a data structure output by the dynamic encryption chip according to an embodiment of the present application.

Fig. 7 is a schematic structural diagram of the dynamic encryption chip according to an embodiment of the present application.

Description of the reference numerals

First pin 101 and second pin 102 of dynamic encryption chip 100

Rectifier module 10 voltage limiting circuit 11 rectifier circuit 12

Frequency eliminating module 20

Control module 30 storage controller 31 encryption controller 32 encoding controller 33

Memory module 40

Encryption module 50 random number generator 51 encryption processor 52

Encoding module 60

Transmitting module 70

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below by way of embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be considered as limiting the present application.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

The dynamic encryption chip and the underground marker are provided aiming at the problems that the traditional wireless induction chip can directly transmit original data stored in the chip to a receiver after obtaining a power supply and frequency, so that the transmitted data has no safety and is easy to be recorded by a user.

Referring to fig. 1, fig. 1 is a block diagram illustrating a dynamic cryptographic chip 100 according to an embodiment of the present disclosure. The dynamic encryption chip 100 includes: the device comprises a rectification module 10, a frequency division module 20, a control module 30, a storage module 40 and an encryption module 50.

The rectifier module 10 is used for generating a power supply required by the dynamic encryption chip 100. Specifically, referring to fig. 2, fig. 2 is a circuit diagram of the rectifier module according to an embodiment of the present disclosure. The rectification module 10 is a full-wave rectification circuit. The rectifying module 10 includes a voltage limiting circuit 11 and a rectifying circuit 12. The voltage limiting circuit 11 is responsible for limiting the induced voltage within the normal operating range (2V-5V) of the dynamic encryption chip 100, so as to prevent the dynamic encryption chip 100 from being burnt out due to an excessive external induced voltage. The rectifying circuit 12 is responsible for converting the induced ac voltage into a dc voltage that can enable the dynamic encryption chip 100 to operate.

The frequency dividing module 20 is connected in parallel with the rectifying module 10, and is configured to generate a clock required by the dynamic encryption chip 100. Specifically, please refer to fig. 3, fig. 3 is a schematic diagram illustrating an operating principle of the frequency dividing module 20 according to an embodiment of the present application. The frequency dividing module 20 is used for dividing the original frequency into different working frequencies. The frequency dividing module 20 may include a clock conversion circuit and a frequency dividing circuit (not shown). The internal operation clock of the dynamic encryption chip 100 is a square wave. Therefore, the clock conversion circuit is arranged to convert the sine wave obtained by induction into a square wave. In addition, since the working timings of the dynamic encryption chip 100 are different, the frequency dividing circuit is responsible for generating the working clocks and various frequency divisions required by the circuit modules of the dynamic encryption chip 100.

The control module 30 is electrically connected to the rectifying module 10 and the frequency dividing module 20, and is configured to control the work flow of the dynamic encryption chip 100. Referring to fig. 4, fig. 4 is a schematic diagram illustrating an internal structure of the control module 30 according to an embodiment of the present disclosure. The control module 30 includes a storage controller 31, an encryption controller 32, and an encoding controller 33. The control module 30 is responsible for controlling the working flow of the dynamic encryption chip 100. Specifically, the memory controller 31 is configured to control data reading and/or data reading of the memory module 40. The encryption controller 32 is used for controlling whether the encryption module 50 is started or not. The encoding controller 33 is configured to implement operation and development of encoding work on the encrypted chip data.

The memory module 40 is electrically connected to the control module 30 and is used for storing chip data. The Memory module 40 may be a Read-Only Memory (ROM) and may operate in a non-destructive manner, and Only Read information that cannot be written into a chip is Read.

The encryption module 50 is electrically connected to the control module 30 and the storage module 40, respectively, and is configured to generate a random number and encrypt the chip data. The specific structure of the encryption module 50 is not limited as long as the random number can be generated and the chip data can be encrypted.

In this embodiment, the encryption module 50 for generating a random number and encrypting the random number and the chip data is added in the dynamic encryption chip 100. After obtaining the power and the frequency, the dynamic encryption chip 100 encrypts the chip data by combining the random number generated by the encryption module 50. After the encryption processing of the dynamic encryption chip 100, the retransmitted chip data has higher security and is not easy to be recorded.

Referring to fig. 5, fig. 5 is a schematic structural diagram of the encryption module 50. In one embodiment, the encryption module 50 includes: a random number generator 51 and an encryption processor 52.

The random number generator 51 is used to generate random numbers of different word lengths. The encryption processor 52 is configured to encrypt the random number and the chip data. The input end of the encryption processor 52 is electrically connected to the random number generator 51 and the storage module 40, respectively.

In this embodiment, a specific structure of the encryption module 50 is provided. The encryption module 50 is mainly responsible for the encryption work of the dynamic encryption chip 100, and the encryption module 50 encrypts the chip data by combining a random number. In the encryption module 50, different encryption round numbers are adopted according to the random numbers with different word lengths and the chip data with different word lengths, and finally random encryption processing on the chip data is realized. The encrypted dynamic ID (english IDentity) is obtained after the processing by the encryption module 50. Specifically, the dynamic ID means a dynamic identification code.

The encryption principle of the encryption module 50 is similar to a dynamic encryption method. Before each chip data (128bit) is transmitted, it is recombined in the random number processor 52 with the random number generated by the random number generator 51. The cryptographically processed dynamic ID is formed after recombination in the random number processor 52.

In one embodiment, the chip data stored in the memory module 40 is 128 bits. A random number of 8-bit word length is generated in the random number generator 51.

In this embodiment, the chip data may be 128bits and the random number may be 8 bits. In other embodiments of the present application, the random number may have other word sizes. The random numbers have different lengths, and when dynamic encryption processing is carried out, the encryption rounds have different numbers, and the encryption grades of the chip data generated by encryption are different.

In one embodiment, the storage module 40 includes: and a fusing unit. The fusing unit has a fused state and a non-fused state. The programming of the memory module 40 adopts a Laser Fuse (Laser Fuse) mode. The memory module 40 may have 8 fuses. The fuse may be in a laser blown state or in a state where it is not blown by a laser. The laser fusing directly generates high heat energy on the conducting wire in a physical mode, the conducting wire is actually fused, and a polycrystalline silicon Fuse (Poly Fuse) is avoided. Therefore, the situation that the flash memory is not easy to blow or is similar to break or break is not generated, so that the situation of data repetition is caused, and the problem of the storage life of the flash memory data is avoided. In the present application, the memory module 40 adopts a non-recoverable programming mode, and can ensure the durability of the chip data storage.

In one embodiment, the dynamic encryption chip 100 further includes an encoding module 60.

The encoding module 60 is electrically connected to the output end of the encryption module 50, and is configured to convert the encrypted chip data into encrypted data in a radio frequency output format. The encoding module 60 may be a carrier encoding module. The encoding module 60 is configured to convert the encrypted data into a format suitable for rf output, so as to prepare for rf output in the next step.

In one embodiment, the dynamic encryption chip 100 further includes a transmitting module 70.

The transmitting module 70 is electrically connected to the encoding module 60, and is configured to transmit the encrypted data in the radio frequency output format. The transmit module 70 may include a high frequency oscillator and a power amplifier. Specifically, the transmitting module 70 may include a transmitting circuit composed of an inductor, a capacitor, a resistor, a transistor amplifier, and the like. In one embodiment, the transmitting module 70 may be equivalent to a triode, and stores and loads the encoded and encrypted chip data to a radio frequency, and transmits the encrypted chip data to the outside of the dynamic encryption chip 100.

In one embodiment, the data structure stored in the storage module 40 includes: 13 bits of start code, 88bits of data code, 22 bits of horizontal even parity check code, 4 bits of column odd parity check code and 1 bit of end code. Every 4 bits of the data codes form a row, and each even row comprises one bit of the transverse even parity check code. Every 20 bits of the data codes form a row, and each odd row comprises a bit of the column odd parity check code.

Referring to table 1, in the present embodiment, the storage module 40 may be a computer Read Only Memory (ROM) and is mainly responsible for storing the original chip data (the chip data before encryption). The data stored in the memory module 40 has 128BITS (128 BITS). The parity check code comprises a 13-bit start code, an 88-bit data code, a 22-bit horizontal even parity check code, a 4-bit column odd parity check code and a 1-bit end code. In which a 13-bit start code, i.e., 13 "1" s in table 1, is used as the start code. 88bit data codes, i.e., 88BITS of D00-DL3 in Table 1. The 22-bit horizontal even parity check codes are P0-P21 horizontal even parity check codes in Table 1. The 4-bit column parity check codes are PC0-PC3 column parity check codes in Table 1. The 1-bit end code, i.e., "0" in Table 1, is used as an end suffix.

Table 1: data structure schematic table of storage module

The DATA of ROM _ DATA in table 1 is raw chip DATA without encryption.

Referring to fig. 6, fig. 6 is a schematic diagram of a data structure output by the dynamic encryption chip 100. In one embodiment, a continuous output paradigm of the dynamic cryptographic chip 100 is provided.

In a specific embodiment, the dynamic encryption chip 100 is formed as an SCW5113 chip. Referring to fig. 6, the special encoding structure in the dynamic encryption chip 100 is: data "0" is a 50% period trigger waveform (negative edge trigger waveform). Data "1" is a trigger waveform of 25% of the period.

In one embodiment, the waveform output by the dynamic encryption chip 100 is an asymmetric waveform, and the symbol representing "0" and the symbol representing "1" in the asymmetric waveform are asymmetric.

In one embodiment, the dynamic encryption chip 100 outputs a waveform in which a symbol representing "0" has one transition among 2 levels of equal period and a symbol representing "1" has three transitions among 4 levels of equal period. The first jump becomes a jump from high level to low level, and the first jump among the three jumps becomes a jump from low level to high level.

In another embodiment, in the waveform output by the dynamic encryption chip 100,

has one hop among 2 levels of equal period, and the symbol representing "1" has three hops among 4 levels of equal period. The first jump becomes a jump from low level to high level, and the first jump among the three jumps becomes a jump from high level to low level.

Referring to fig. 7, fig. 7 is a schematic structural diagram of the dynamic encryption chip 100 according to the present application. The dynamic encryption chip 100 comprises the rectification module 10 for generating a power supply required by the dynamic encryption chip 100, the frequency division module 20 for generating a clock required by the dynamic encryption chip 100, the control module 30 for controlling the working process of the dynamic encryption chip 100, the storage module 40 for storing chip data, the encryption module 50 for generating random numbers and encrypting the chip data, the coding module 60 for converting the encrypted chip data into the encrypted data in the radio frequency output format, and the transmitting module 70 for transmitting the encrypted data in the radio frequency output format.

The working steps of the dynamic encryption chip 100 are as follows:

the dynamic encryption chip 100 uses an external LC parallel resonant circuit to trigger the first pin 101 and the second pin 102. The rectifying module 10 and the frequency dividing module 20 start to generate power and clock required for the whole dynamic encryption chip 100 to work. It needs to be further explained that: when an external radio frequency magnetic field is close to the LC parallel resonant circuit, an induced voltage is generated at the first pin 101 and the second pin 102 at the two ends of the LC parallel resonant circuit, and the induced voltage is converted into a working voltage and a working frequency of the dynamic encryption chip 100 by the circuit of the dynamic encryption chip 100, and a return signal is loaded on the induced voltage.

The control module 30 issues a control command instructing the storage module 40 to sequentially output the chip data to the encryption module 50. The encryption module 50 breaks up the chip data, and then performs recombination encryption processing by combining the generated random number. That is, the encryption module 50 encrypts the chip data in combination with a random number. The encrypted chip data is subjected to carrier encoding by the encoding module 60, and finally the encrypted chip data is transmitted by the transmitting module 70.

In this embodiment, before transmitting the original chip data in the dynamic cryptographic chip 100, the original chip data passes through the cryptographic module 50, and the data is scattered and recombined, and then is transmitted to the transmitting module 70 of the dynamic cryptographic chip 100. After the dynamic encryption chip 100 is recorded or stolen, because the encryption module 50 has performed encryption processing, the dynamic encryption chip 100 is not easy to be decoded, thereby greatly improving the security of the dynamic encryption chip 100.

The application also provides an underground marker, which comprises the dynamic encryption chip 100. The application provides integrated in the underground marker and adopted the advanced encryption standard right chip data encrypt dynamic encryption chip 100 makes underground marker data do not have the security, be difficult to moreover by the side record, promoted greatly underground marker's safety in utilization.

The present application also includes an underground marker reading device (not shown). The underground marker reading device may be a handheld device. The underground marker reading apparatus includes: the device comprises a receiving module, a decoding module, a reading control module, an output module and a display module. The receiving module, the decoding module and the reading control module are electrically connected in sequence. The output module and the display module are respectively and electrically connected to the reading control module. The receiving module is configured to read the chip data encrypted in the dynamic encryption chip 100 in the underground identifier. The decoding module is configured to restore the encrypted chip data to the original chip data of the dynamic encryption chip 100. The output module is configured to output the original chip data to other devices that need to identify the dynamic encryption chip 100. The display module is used for displaying the original chip data in a display screen of the underground identifier reading device. The reading control module is used for controlling the working processes of the receiving module, the decoding module, the output module and the display module.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present patent. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A dynamic cryptographic chip, comprising:

the rectifier module (10) is used for generating a power supply required by the dynamic encryption chip (100);

the frequency dividing module (20) is connected with the rectifying module (10) in parallel and is used for generating a clock required by the dynamic encryption chip (100);

the control module (30) is respectively electrically connected with the rectifying module (10) and the frequency dividing module (20) and is used for totally controlling the working process of the dynamic encryption chip (100);

the storage module (40) is electrically connected with the control module (30) and is used for storing chip data;

the encryption module (50) is respectively electrically connected with the control module (30) and the storage module (40), and the encryption module (50) generates random numbers for encryption to encrypt the chip data.

2. The dynamic cryptographic chip of claim 1, wherein the cryptographic module (50) comprises:

a random number generator (51) for generating random numbers;

and the input end of the encryption processor (52) is respectively electrically connected with the random number generator (51) and the storage module (40) and is used for encrypting the random number and the chip data so as to generate the encrypted chip data.

3. The dynamic encryption chip of claim 2, wherein the data stored in the storage module (40) is 128 bits;

a random number of 8-bit word length is generated in the random number generator (51).

4. The dynamic encryption chip of claim 3, further comprising:

and the coding module (60) is electrically connected with the output end of the encryption processor (52) and is used for converting the encrypted chip data into encrypted data in a radio frequency output format.

5. The dynamic encryption chip of claim 4, further comprising:

and the transmitting module (70) is electrically connected with the encoding module (60) and is used for transmitting the encrypted data in the radio frequency output format.

6. The dynamic encryption chip of claim 5, wherein the data structure stored in the storage module (40) comprises:

a 13-bit start code;

an 88-bit data code;

a 1-bit end code.

7. The dynamic encryption chip of claim 6, wherein the waveform outputted by the dynamic encryption chip (100) is an asymmetric waveform, and a symbol representing "0" and a symbol representing "1" in the asymmetric waveform are asymmetric.

8. The dynamic encryption chip of claim 7, wherein the dynamic encryption chip (100) outputs a waveform in which a symbol representing "0" has one transition among 2 levels with equal periods and a symbol representing "1" has three transitions among 4 levels with equal periods.

9. The dynamic encryption chip of claim 8, wherein the one transition is a transition from high to low, and wherein a first transition of the three transitions is a transition from low to high.

10. An underground marker, characterized in that it comprises a dynamic cryptographic chip (100) according to any one of claims 1 to 9.