CN113037481A - Encryption chip and underground marker - Google Patents
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- CN113037481A CN113037481A CN202110345215.7A CN202110345215A CN113037481A CN 113037481 A CN113037481 A CN 113037481A CN 202110345215 A CN202110345215 A CN 202110345215A CN 113037481 A CN113037481 A CN 113037481A
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- 230000008569 process Effects 0.000 claims description 3
- 238000012545 processing Methods 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 14
- 238000006243 chemical reaction Methods 0.000 description 2
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- 238000013459 approach Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
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Abstract
The application relates to an encryption chip and an underground marker. The encryption chip comprises: the device comprises a rectification module used for generating a power supply required by an encryption chip, a frequency division module used for generating a clock required by the encryption chip, a control module used for master control of the work flow of the encryption chip, a storage module used for storing chip data and an encryption module used for encrypting the chip data by adopting an advanced encryption standard. And the encryption module encrypts the chip data by adopting an advanced encryption standard. In this application encrypt the inside of chip and increased and adopted the advanced encryption standard to encrypt the encryption module. After the encryption chip obtains the power supply and the frequency, the encryption chip adopts the advanced encryption standard to encrypt the chip data. After the encryption processing of the encryption chip, the retransmitted chip data has higher security and is not easy to be recorded.
Description
Technical Field
The application relates to the field of electronic communication, in particular to an encryption chip and an underground marker.
Background
The conventional rf transmission chip is generally a wireless sensing chip. After the wireless sensing chip obtains the power supply and the frequency, the original data stored in the chip can be directly transmitted to the receiver, so that the transmitted data has no safety and is easy to record.
Disclosure of Invention
Therefore, it is necessary to provide an encryption chip and an underground marker for solving the problems that the conventional wireless sensing chip directly transmits the original data stored in the chip to the receiver after obtaining the power and the frequency, so that the transmitted data has no security and is easy to be recorded.
A cryptographic chip, comprising:
the rectifier module is used for generating a power supply required by the encryption chip;
the frequency eliminating module is connected with the rectifying module in parallel and is used for generating a clock required by the encryption chip;
the control module is respectively electrically connected with the rectifying module and the frequency eliminating module and is used for totally controlling the working flow of the encryption chip;
the storage module is electrically connected with the control module and is used for storing chip data;
and the encryption module is respectively electrically connected with the control module and the storage module and is used for encrypting the chip data by adopting an advanced encryption standard.
In one embodiment, the encryption module comprises:
a key generator for generating keys of different word lengths;
the input end of the encryption processor is respectively and electrically connected with the secret key generator and the storage module, and the encryption processor is used for encrypting the secret key and the chip data by adopting an advanced encryption standard;
and the encryption result buffer is electrically connected with the output end of the encryption processor and used for buffering the encrypted chip data.
In one embodiment, the data stored in the memory module is 128 bits;
the key generator generates a key of 128bits, 192 bits or 256 bits.
In one embodiment, the encryption chip further includes:
and the coding module is electrically connected with the output end of the encryption result buffer and used for converting the encrypted chip data into the encrypted data in the radio frequency output format.
In one embodiment, the encryption chip further includes:
and the transmitting module is electrically connected with the encoding module and is used for transmitting the encrypted data in the radio frequency output format.
In one embodiment, the data structure stored in the storage module includes:
a 23-bit start code;
an 80-bit data code;
20 bits of horizontal even parity check codes, wherein every 4 bits of the data codes form a row, and each even row comprises one bit of the horizontal even parity check codes;
4 bits column odd parity check code, every 20 bits of said data code make up a row, each odd column includes a bit of said column odd parity check code;
a 1-bit end code.
In one embodiment, the waveform output by the encryption chip is an asymmetric waveform, and a symbol representing '0' and a symbol representing '1' in the asymmetric waveform are asymmetric.
In one embodiment, in the waveform output by the encryption chip, a symbol representing "0" is modulated to be low level in one period, and a symbol representing "1" is modulated to have three transitions in one period.
In one embodiment, the first transition of the three transitions is a transition from high to low.
The application also provides an underground marker, which comprises the encryption chip.
The application provides an encryption chip and underground marker. The encryption chip comprises: the device comprises a rectification module used for generating a power supply required by an encryption chip, a frequency division module used for generating a clock required by the encryption chip, a control module used for master control of the work flow of the encryption chip, a storage module used for storing chip data and an encryption module used for encrypting the chip data by adopting an advanced encryption standard. The frequency eliminating module is connected with the rectifying module in parallel. The control module is respectively electrically connected with the rectifying module and the frequency dividing module. The storage module is electrically connected with the control module. The encryption module is electrically connected with the control module and the storage module respectively. In this application encrypt the inside of chip and increased and adopted the advanced encryption standard to encrypt the encryption module. After the encryption chip obtains the power supply and the frequency, the encryption chip adopts the advanced encryption standard to encrypt the chip data. After the encryption processing of the encryption chip, the retransmitted chip data has higher security and is not easy to be recorded.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic block diagram of the cryptographic chip according to an embodiment of the present application.
Fig. 2 is a circuit diagram of the rectifier module according to an embodiment of the present application.
Fig. 3 is a schematic diagram illustrating an operating principle of the frequency dividing module according to an embodiment of the present application.
Fig. 4 is a schematic internal structural diagram of the control module according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of the encryption module according to an embodiment of the present application.
Fig. 6 is a schematic diagram of a data structure output by the cryptographic chip according to an embodiment of the present application.
Fig. 7 is a schematic structural diagram of the encryption chip according to an embodiment of the present application.
Description of the reference numerals
Rectifier module 10 voltage limiting circuit 11 rectifier circuit 12
Encoding module 60
Transmitting module 70
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below by way of embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be considered as limiting the present application.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
The encryption chip and the underground marker are provided aiming at the problems that the traditional wireless induction chip can directly transmit original data stored in the chip to a receiver after obtaining a power supply and frequency, so that the transmitted data has no safety and is easy to be recorded by a user.
Referring to fig. 1, fig. 1 is a block diagram illustrating an encryption chip 100 according to an embodiment of the present disclosure. The cryptographic chip 100 includes: the device comprises a rectification module 10, a frequency division module 20, a control module 30, a storage module 40 and an encryption module 50.
The rectifying module 10 is used for generating a power supply required by the encryption chip 100. Specifically, referring to fig. 2, fig. 2 is a circuit diagram of the rectifier module according to an embodiment of the present disclosure. The rectification module 10 is a full-wave rectification circuit. The rectifying module 10 includes a voltage limiting circuit 11 and a rectifying circuit 12. The voltage limiting circuit 11 is responsible for limiting the induced voltage within the normal operating range (2V-5V) of the encryption chip 100, so as to prevent the encryption chip 100 from being burnt due to an excessive external induced voltage. The rectifying circuit 12 is responsible for converting the induced ac voltage into a dc voltage that allows the encryption chip 100 to operate.
The frequency dividing module 20 is connected in parallel with the rectifying module 10, and is configured to generate a clock required by the cryptographic chip 100. Specifically, please refer to fig. 3, fig. 3 is a schematic diagram illustrating an operating principle of the frequency dividing module 20 according to an embodiment of the present application. The frequency dividing module 20 is used for dividing the original frequency into different working frequencies. The frequency dividing module 20 may include a clock conversion circuit and a frequency dividing circuit (not shown). Since the internal operation clock of the encryption chip 100 is a square wave. Therefore, the clock conversion circuit is arranged to convert the sine wave obtained by induction into a square wave. In addition, since the operation timings of the encryption chip 100 are different, the frequency dividing circuit is responsible for generating the operation clocks and various frequency divisions required by the circuit modules of the encryption chip 100.
The control module 30 is electrically connected to the rectifying module 10 and the frequency dividing module 20, and is configured to control the work flow of the encryption chip 100. Referring to fig. 4, fig. 4 is a schematic diagram illustrating an internal structure of the control module 30 according to an embodiment of the present disclosure. The control module 30 includes a storage controller 31, an encryption controller 32, and an encoding controller 33. The control module 30 is responsible for overall controlling the working flow of the encryption chip 100. Specifically, the memory controller 31 is configured to control data reading and/or data reading of the memory module 40. The encryption controller 32 is used for controlling whether the encryption module 50 is started or not. The encoding controller 33 is configured to implement operation and development of encoding work on the encrypted chip data.
The memory module 40 is electrically connected to the control module 30 and is used for storing chip data. The Memory module 40 may be a Read-Only Memory (ROM) and may operate in a non-destructive manner, and Only Read information that cannot be written into a chip is Read.
The encryption module 50 is electrically connected to the control module 30 and the storage module 40, respectively, and is configured to encrypt the chip data using advanced encryption standards. The specific structure of the encryption module 50 is not limited as long as the function of encrypting the chip data can be realized by adopting the advanced encryption standard.
In this embodiment, the encryption module 50 for encrypting according to the advanced encryption standard is added in the encryption chip 100. After the encryption chip 100 obtains the power and the frequency, it encrypts the chip data by using the advanced encryption standard. After the encryption processing of the encryption chip, the retransmitted chip data has higher security and is not easy to be recorded.
Referring to fig. 5, fig. 5 is a schematic structural diagram of the encryption module 50. In one embodiment, the encryption module 50 includes: a key generator 51, an encryption processor 52 and an encryption result buffer 53.
The key generator 51 is used for generating keys of different word lengths. The encryption processor 52 is configured to perform encryption processing on the key and the chip data by using an advanced encryption standard. The input end of the encryption processor 52 is electrically connected to the key generator 51 and the storage module 40, respectively. The encryption result buffer 53 is used for buffering the encrypted chip data. The encryption result buffer 53 is electrically connected to an output of the encryption processor 52.
In this embodiment, a specific structure of the encryption module 50 is provided. The encryption module 50 is mainly responsible for the encryption work of the encryption chip 100, and the encryption module 50 encrypts the chip data by adopting the advanced encryption standard. Specifically, in this embodiment, the Encryption module 50 encrypts the chip data by using Advanced Encryption Standard (AES). In the encryption module 50, different encryption rounds are adopted according to keys with different word lengths and the chip data with different word lengths, and finally advanced encryption processing on the chip data is realized.
In one embodiment, the chip data stored in the memory module 40 is 128 bits. The key generator 51 generates a key of 128bits, 192 bits or 256 bits.
In this embodiment, the 128bits of chip data and the 128bits of key may be subjected to AES encryption processing. The chip data, which may be 128bits, is AES encrypted with a 192-bit key. The 128bits of chip data and 256 bits of key can be used for AES encryption processing. The length of the secret key is different, when AES encryption processing is carried out, the number of encryption rounds is different, and the encryption grades of the chip data generated by encryption are different.
In one embodiment, the cryptographic chip 100 further comprises an encoding module 60.
The encoding module 60 is electrically connected to the output end of the encryption result buffer 53, and is configured to convert the encrypted chip data into encrypted data in a radio frequency output format. The encoding module 60 may be a carrier encoding module. The encoding module 60 is configured to convert the encrypted data into a format suitable for rf output, so as to prepare for rf output in the next step.
In one embodiment, the cryptographic chip 100 further comprises a transmitting module 70.
The transmitting module 70 is electrically connected to the encoding module 60, and is configured to transmit the encrypted data in the radio frequency output format. The transmit module 70 may include a high frequency oscillator and a power amplifier. Specifically, the transmitting module 70 may include a transmitting circuit composed of an inductor, a capacitor, a resistor, a transistor amplifier, and the like. In one embodiment, the transmitting module 70 may be equivalent to a triode, and stores and loads the encoded and encrypted chip data to a radio frequency, and transmits the encrypted chip data to the outside of the encryption chip 100.
In one embodiment, the data structure stored in the storage module 40 includes: 23 bits of start code, 80bits of data code, 20 bits of horizontal even parity check code, 4 bits of column odd parity check code and 1 bit of end code. Every 4 bits of the data codes form a row, and each even row comprises one bit of the transverse even parity check code. Every 20 bits of the data codes form a row, and each odd row comprises a bit of the column odd parity check code.
Referring to table 1, in the present embodiment, the storage module 40 may be a computer Read Only Memory (ROM) and is mainly responsible for storing the original chip data (the chip data before encryption). The data stored in the memory module 40 has 128BITS (128 BITS). The code includes 23 bits of start code, 80bits of data code, 20 bits of horizontal even parity check code, 4 bits of column odd parity check code and 1 bit of end code. Among them, 23 bits of start code, namely 23 "1" in table 1, is used as the start code. And the 80-bit data codes are data BITS of 80BITS in total, namely D00-DJ3 in Table 1. The 20-bit horizontal even parity check codes are P0-P19 horizontal even parity check codes in Table 1. The 4-bit column parity check codes are PC0-PC3 column parity check codes in Table 1. The 1-bit end code, i.e., "0" in Table 1, is used as an end suffix.
Table 1: data structure schematic table of storage module
The DATA of ROM _ DATA in table 1 is raw chip DATA without encryption.
Referring to fig. 6, fig. 6 is a schematic diagram of a data structure output by the encryption chip 100. In one embodiment, a continuous output paradigm of the cryptographic chip 100 is provided.
In a specific embodiment, the formed encryption chip 100 is a CSG5208 chip. Referring to fig. 6, the special encoding structure in the encryption chip 100 is: data "0" is a trigger waveform of 25% of the period. Data "1" is a trigger waveform of 100% of the period.
In one embodiment, the waveform output by the encryption chip 100 is an asymmetric waveform, and the symbol representing "0" and the symbol representing "1" in the asymmetric waveform are asymmetric.
In one embodiment, in the waveform output from the encryption chip 100, a symbol representing "0" is modulated to a low level in one period, and a symbol representing "1" is modulated to have three transitions in one period. The first of the three transitions becomes a transition from high to low.
In another embodiment, the waveform output from the encryption chip 100 has a symbol representing "0" modulated to a high level in one period and a symbol representing "1" modulated to have three transitions in one period. The first of the three transitions becomes a transition from low to high.
Referring to fig. 7, fig. 7 is a schematic diagram of a specific structure of the encryption chip 100 provided in the present application. The encryption chip 100 comprises the rectification module 10 for generating a power supply required by the encryption chip, the frequency-dividing module 20 for generating a clock required by the encryption chip 100, the control module 30 for overall controlling the work flow of the encryption chip 100, the storage module 40 for storing chip data, the encryption module 50 for encrypting the chip data by adopting an advanced encryption standard, the coding module 60 for converting the encrypted chip data into encrypted data in a radio frequency output format, and the transmitting module 70 for transmitting the encrypted data in the radio frequency output format.
The working steps of the encryption chip 100 are as follows:
the encryption chip 100 uses an external LC parallel resonant circuit to trigger the first pin 101 and the second pin 102. The rectifying module 10 and the frequency dividing module 20 start to generate power and clock required for the whole encryption chip 100 to work. It needs to be further explained that: when an external radio frequency magnetic field approaches to the LC parallel resonant circuit, an induced voltage is generated at the first pin 101 and the second pin 102 at the two ends of the LC parallel resonant circuit, and the induced voltage is converted into a working voltage and a working frequency of the encryption chip 100 by the circuit of the encryption chip 100 itself, and a return signal is loaded on the induced voltage.
The control module 30 issues a control command instructing the storage module 40 to sequentially output the chip data to the encryption module 50. The encryption module 50 breaks up the chip data, and then performs a re-combination encryption process by combining with the generated secret key. That is, the encryption module 50 encrypts the chip data using the advanced encryption standard. The encrypted chip data is subjected to carrier encoding by the encoding module 60, and finally the encrypted chip data is transmitted by the transmitting module 70.
In this embodiment, before transmitting the original chip data in the cryptographic chip 100, the original chip data passes through the cryptographic module 50, and the data is scattered and recombined, and then is transmitted to the transmitting module 70 of the cryptographic chip 100. When the encryption chip 100 is recorded or stolen, the encryption module 50 performs encryption processing, so that the encryption chip 100 is not easy to be decoded, and the security of the encryption chip 100 is greatly improved.
The application also provides an underground marker, which comprises the encryption chip 100. The application provides integrated in the underground marker and adopted the advanced encryption standard right chip data encrypt encryption chip 100 makes underground marker data do not have the security, be difficult to moreover by the side record, promoted greatly underground marker's safety in utilization.
The present application also includes an underground marker reading device (not shown). The underground marker reading device may be a handheld device. The underground marker reading apparatus includes: the device comprises a receiving module, a decoding module, a reading control module, an output module and a display module. The receiving module, the decoding module and the reading control module are electrically connected in sequence. The output module and the display module are respectively and electrically connected to the reading control module. The receiving module is used for reading the chip data encrypted in the encryption chip 100 in the underground identifier. The decoding module is configured to restore the encrypted chip data to the original chip data of the encrypted chip 100. The output module is configured to output the original chip data to other devices that need to identify the cryptographic chip 100. The display module is used for displaying the original chip data in a display screen of the underground identifier reading device. The reading control module is used for controlling the working processes of the receiving module, the decoding module, the output module and the display module.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present patent. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A cryptographic chip, comprising:
the rectifier module (10) is used for generating a power supply required by the encryption chip (100);
the frequency dividing module (20) is connected with the rectifying module (10) in parallel and is used for generating a clock required by the encryption chip (100);
the control module (30) is respectively electrically connected with the rectifying module (10) and the frequency dividing module (20) and is used for totally controlling the working process of the encryption chip (100);
the storage module (40) is electrically connected with the control module (30) and is used for storing chip data;
and the encryption module (50) is respectively electrically connected with the control module (30) and the storage module (40) and is used for encrypting the chip data by adopting an advanced encryption standard.
2. The cryptographic chip according to claim 1, characterized in that said cryptographic module (50) comprises:
a key generator (51) for generating keys of different word lengths;
the input end of the encryption processor (52) is respectively electrically connected with the secret key generator (51) and the storage module (40) and is used for encrypting the secret key and the chip data by adopting an advanced encryption standard;
and the encryption result buffer (53) is electrically connected with the output end of the encryption processor (52) and is used for buffering the encrypted chip data.
3. The cryptographic chip according to claim 2, wherein the data stored in the storage module (40) is 128 bits;
the key generator (51) generates a key of 128-bit, 192-bit or 256-bit word length.
4. The cryptographic chip of claim 3, further comprising:
and the coding module (60) is electrically connected with the output end of the encryption result buffer (53) and is used for converting the encrypted chip data into the encrypted data in the radio frequency output format.
5. The cryptographic chip of claim 4, further comprising:
and the transmitting module (70) is electrically connected with the encoding module (60) and is used for transmitting the encrypted data in the radio frequency output format.
6. The cryptographic chip according to claim 5, wherein the data structure stored in the storage module (40) comprises:
a 23-bit start code;
an 80-bit data code;
20 bits of horizontal even parity check codes, wherein every 4 bits of the data codes form a row, and each even row comprises one bit of the horizontal even parity check codes;
4 bits column odd parity check code, every 20 bits of said data code make up a row, each odd column includes a bit of said column odd parity check code;
a 1-bit end code.
7. The cryptographic chip of claim 6, wherein the waveform output by the cryptographic chip (100) is an asymmetric waveform in which a symbol representing "0" and a symbol representing "1" are asymmetric.
8. The encryption chip of claim 7, wherein the waveform outputted from the encryption chip (100) is modulated to have a low level for a symbol representing "0" and three transitions for a symbol representing "1" in one period.
9. The cryptographic chip of claim 8, wherein the first of the three transitions is a transition from high to low.
10. An underground marker, characterized in that it comprises a cryptographic chip (100) according to any one of claims 1 to 9.
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| CN202110345215.7A CN113037481A (en) | 2021-03-31 | 2021-03-31 | Encryption chip and underground marker |
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| CN202110345215.7A CN113037481A (en) | 2021-03-31 | 2021-03-31 | Encryption chip and underground marker |
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| CN106384139A (en) * | 2016-11-02 | 2017-02-08 | 安徽工程大学 | RFID reader-writer based on hardware security encryption |
| CN108199732A (en) * | 2018-02-08 | 2018-06-22 | 北京智芯微电子科技有限公司 | Radio frequency transmission chip |
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