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CN111129155A - Preparation method of low-gate-drain capacitance silicon carbide DI-MOSFET - Google Patents

Preparation method of low-gate-drain capacitance silicon carbide DI-MOSFET Download PDF

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CN111129155A
CN111129155A CN201911352640.8A CN201911352640A CN111129155A CN 111129155 A CN111129155 A CN 111129155A CN 201911352640 A CN201911352640 A CN 201911352640A CN 111129155 A CN111129155 A CN 111129155A
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刘敏
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Chongqing Weitesen Electronic Technology Co ltd
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Abstract

The invention provides a preparation method of a low-gate-drain capacitance SiC DI-MOSFET (direct-current drive-metal oxide semiconductor field effect transistor) for solving the problems of low device working frequency and large dynamic loss caused by large gate-drain capacitance, which comprises the following specific steps of: selecting a semiconductor substrate with a silicon carbide (SiC) epitaxial layer; carrying out region ion implantation on the silicon wafer through a photoetching mask, and activating and implanting impurities through high-temperature annealing; carrying out local Si ion implantation on the epitaxial layer without implanted doping through a photoetching mask; thermally growing an oxide layer at 600-2000 ℃; depositing polysilicon and etching off the unnecessary part to form a grid; depositing a dielectric layer to coat and etch the grid to form a source level contact hole; and depositing source metal covering the source region and the dielectric layer above the dielectric layer, depositing drain metal below the substrate, and annealing to prepare ohmic contact. Due to the adoption of the technical scheme, the thickness of the gate oxide layer is increased, the gate leakage capacitance is reduced, the switching speed of the device is increased, the working frequency is increased, and the switching loss of the device is reduced.

Description

Preparation method of low-gate-drain capacitance silicon carbide DI-MOSFET
Technical Field
The invention relates to the field of semiconductors, in particular to a preparation method of a silicon carbide DI-MOSFET (DI-metal oxide semiconductor field effect transistor) with low gate-drain capacitance.
Background
Semiconductor technology has been a decisive force for driving the development of the power electronics industry. The application of power Silicon devices (Si) is well established, but with the increasing industrial demand, Silicon devices have become unsuitable for some high-voltage, high-temperature, high-efficiency and high-power-density applications due to the limitation of their physical properties. Silicon carbide (SiC) materials have been receiving attention and research due to their excellent physical properties, and the silicon carbide technology has been rapidly developed. The silicon carbide is one of wide bandgap semiconductor materials, is also an important component of third generation semiconductor materials, and has the advantages of high critical breakdown electric field intensity, high saturated electron mobility, high thermal conductivity, corrosion resistance, high hardness and the like. Among many silicon carbide semiconductor devices, a silicon carbide DI-mosfet (double Implanted Metal Oxide semiconductor field Effect transistor) is a switching device having the most advantageous characteristics, and has the advantages of easy driving, high switching speed, low power consumption, and the like. The device is mainly characterized in that an n-type doped region and a p-type doped region surrounding the n-type doped region are formed firstly through two times of ion implantation, then a gate oxide layer is formed on the surface of SiC through thermal oxidation, polycrystalline silicon is deposited on the gate oxide layer to form an MOS structure, then a dielectric layer is deposited to isolate a grid, and finally source metal and drain metal are deposited and annealed to prepare a source electrode and a drain electrode.
However, in the switching power supply, the internal structure, the switching process and the loss of the MOS transistors are complicated, and a large number of MOS transistors are burnt out and failed due to short-time overpower, because a parasitic capacitor needs to be charged and discharged when the large MOS transistors are switched, which causes driving loss, switching loss and reduction of the switching speed.
Disclosure of Invention
The invention provides a preparation method of a low gate-drain capacitance SiC DI-MOSFET, which reduces the gate-drain capacitance of a device by thickening the thickness of an oxide layer between a grid and an uninjected doped epitaxial layer, thereby improving the working frequency of the device and reducing the dynamic loss of the device.
In order to realize the purpose of the invention, the invention provides the following technical scheme:
a preparation method of a low gate-drain capacitance SiCDI-MOSFET comprises the following specific steps:
step S1: selecting an epitaxial wafer with a SiC epitaxial layer grown on the upper surface of the SiC substrate;
step S2: carrying out P-type doping on a local area of the upper surface of the SiC epitaxial layer to form a P-type doped area, forming an n-type ion injection area on the upper surface of the P-type doped area through ion injection to form an n-type doped area, carrying out high-temperature annealing activation to inject impurities, enabling the upper surface of the P-type doped area to coincide with the upper surface of the n-type doped area, enabling the P-type doped area and the n-type doped area to jointly form a source area, and enabling the P-type doped area to surround the n-type doped area;
step S3: performing local Si ion implantation on the region of the upper surface of the SiC epitaxial layer, which is not implanted with the doping, through a photoetching mask to amorphize the SiC;
step S4: performing thermal oxidation treatment to oxidize the non-crystallized ion implantation area and the exposed parts of the p-type doped area, the n-type doped area and the upper surface of the SiC epitaxial layer so as to form an oxidation dielectric layer;
step S5: depositing a grid electrode conductive material on the surface of the oxidized dielectric layer and etching off small parts on two sides, so that the formed grid electrode conductive material can cover part of the p-type doped region and the n-type doped region in the vertical direction;
step S6: depositing or growing a dielectric layer to completely coat the gate conductive material, and etching the dielectric layer to form a source contact hole
Step S7: and depositing source metal covering the source region and the dielectric layer above the SiC epitaxial layer, depositing drain metal below the SiC substrate, and annealing to prepare ohmic contact.
The principle of the invention is as follows: the internal parasitic capacitance of the MOS tube mainly comprises a gate source capacitance (Cgs) and a gate drain capacitance (Cgd), which are formed by an insulating layer of a MOS structure; and the drain-source capacitance (Cds) is formed by a PN junction. The gate-drain capacitance (Cgd) capacitance, known in the industry as the miller capacitance, is not constant but varies rapidly with changes in the voltage between the gate and drain. The miller effect caused by the miller capacitance is that in the process of turning on the MOS transistor, the GS voltage has a stable value after rising to a certain voltage value, and after that, the GS voltage starts rising again until being completely turned on. Because the voltage of the D electrode is greater than the voltage of the G electrode before the MOS is turned on, the power stored in the parasitic capacitance Cgd of the MOS needs to be injected into the G electrode to neutralize the charge therein when the parasitic capacitance Cgd of the MOS is turned on, and the voltage of the G electrode is greater than the voltage of the D electrode after the MOS is completely turned on. The Miller effect can make MOS transistor be goodThe switching state can be quickly entered, and the MOS switching loss is seriously increased. The calculation formula in the semiconductor can be known as follows: oxide layer voltage drop Vox = - Qs/Cox，Cox=εox/tox，εox =εr×εo（Cox is the capacitance per unit area of the oxide layer, epsilonoDielectric constant in vacuum,. epsilonrDenotes the dielectric constant, ε, of other materialsoxIs the dielectric constant of the gate oxide layer, toxOxide layer thickness ). Cgd is therefore proportional to Cox, which is inversely proportional to tox.
By adopting the technical scheme of the invention, Si ion implantation is carried out on the part of the SiC epitaxial layer which is not implanted with the doping under the grid electrode, the SiC is amorphized by the ion implantation, the oxidation speed is improved, and the preparation of a local thick oxidation layer is realized, so that the capacitance value between the grid electrode and the drain electrode is reduced, the working frequency of the device is improved, and the dynamic loss of the device is reduced.
Drawings
FIG. 1 is a schematic structural diagram of step 1.
FIG. 2 is a schematic structural diagram of step 2.
FIG. 3 is a schematic structural diagram of step 3.
FIG. 4 is a schematic structural diagram of step 4.
FIG. 5 is a schematic diagram of a structure of step 5.
FIG. 6 is a schematic diagram of a structure of step 6.
Fig. 7 is a schematic diagram of one structure of the entire device.
1. A source-level metal; 2. a dielectric layer; 3. a gate electrode; an n-type doped region; a p-type doped region; SiC epitaxial layer: a SiC substrate; 8. a drain metal; a Si ion implantation zone.
Detailed Description
The present invention is illustrated below by way of specific examples, but the present invention is not limited thereto, and the experimental methods described in the following examples are all conventional methods unless otherwise specified;
example 1
Step S1: selecting a 4H-SiC epitaxial wafer, wherein the 4H-SiC epitaxial wafer consists of an N + SiC substrate 7 and an N-type epitaxial layer 6, and the epitaxial layer 6 is prepared by Physical Vapor Deposition (PVD) and has the thickness of 10 mu m;
step S2: p-type doping is carried out on two sides of the upper surface of the SiC epitaxial layer 6 to form a p-type doped region 5, an n-type ion implantation region is formed on the upper surface of the p-type doped region 5 through ion implantation to form an n-type doped region 4, annealing activation is carried out at the high temperature of 1700 ℃, implanted impurities are activated, the upper surface of the p-type doped region 5 is overlapped with the upper surface of the n-type doped region 4, the p-type doped region 5 and the n-type doped region 4 jointly form a source region, the p-type doped region 5 surrounds the n-type doped region 4, and the doping concentration of the p-type region is 1x1013cm-3The doping concentration of the n-type region is 1 × 1016cm-3；
Step S3: implanting Si ions 9 into the undoped region of the upper surface of the epitaxial layer 6 through a photomask to amorphize SiC, wherein the Si ions are implanted to a depth of 60nm and have a concentration of 1 × 1020cm-3；
Step S4: performing thermal oxidation treatment at 1200 deg.C to oxidize the exposed parts of the amorphized ion implantation region 9, the p-type doped region 5, the N-type doped region 4 and the SiC epitaxial layer 6 to form an oxide dielectric layer 2, wherein the oxide gas is dry oxygen, wet oxygen, NO, N2O、NO2And oxygen or a mixed gas of nitrogen-containing gases, preferably NO and N2O、NO2；
Step S5: depositing a grid electrode conducting material 3 on the surface of the oxidized dielectric layer 2 and etching off small parts on two sides, so that the grid electrode conducting material 3 can cover part of the p-type doped region 5 and the n-type doped region 4 in the vertical direction;
step S6: etching to form a source contact hole, generating a dielectric layer 2, and completely coating the gate conductive material 3, wherein the dielectric layer 2 is formed by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD) or thermal oxidation of a layer of polycrystalline silicon or amorphous silicon or monocrystalline silicon;
step S7: and depositing source metal 1 covering a source region and the dielectric layer 2 above the SiC epitaxial layer 6, depositing drain metal 8 below the SiC substrate 7, and annealing at the high temperature of 1000 ℃ to prepare ohmic contact.
Example 2
Step S1: selecting a 4H-SiC epitaxial wafer, wherein the 4H-SiC epitaxial wafer consists of an N + SiC substrate 7 and an N-type epitaxial layer 6, and the epitaxial layer 6 is prepared by Physical Vapor Deposition (PVD) and has the thickness of 20 mu m;
step S2: p-type doping is carried out on two sides of the upper surface of the SiC epitaxial layer 6 to form a p-type doped region 5, an n-type ion implantation region is formed on the upper surface of the p-type doped region 5 through ion implantation to form an n-type doped region 4, annealing activation is carried out at the high temperature of 1700 ℃, implanted impurities are activated, the upper surface of the p-type doped region 5 is overlapped with the upper surface of the n-type doped region 4, the p-type doped region 5 and the n-type doped region 4 jointly form a source region, the p-type doped region 5 surrounds the n-type doped region 4, and the doping concentration of the p-type region is 1x1015cm-3The doping concentration of the n-type region is 1 × 1017cm-3；
Step S3: implanting Si ions 9 into the undoped region of the upper surface of the epitaxial SiC layer 6 through a photomask to amorphize SiC, wherein the Si ions are implanted to a depth of 300nm and have a concentration of 1 × 1021cm-3；
Step S4: performing thermal oxidation treatment at 950 ℃ to oxidize the non-crystallized ion implantation region 9 and the exposed parts of the p-type doped region 5, the N-type doped region 4 and the upper surface of the SiC epitaxial layer 6 so as to form an oxidation dielectric layer 2, wherein the oxidation gas is dry oxygen, wet oxygen, NO, N2O、NO2And oxygen or a mixed gas of nitrogen-containing gases, preferably NO and N2O、NO2；
Step S5: depositing a grid electrode conducting material 3 on the surface of the oxidized dielectric layer 2 and etching off small parts on two sides, so that the grid electrode conducting material 3 can cover part of the p-type doped region 5 and the n-type doped region 4 in the vertical direction;
step S6: etching to form a source contact hole, generating a dielectric layer 2, and completely coating the gate conductive material 3, wherein the dielectric layer 2 is formed by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD) or thermal oxidation of a layer of polycrystalline silicon or amorphous silicon or monocrystalline silicon;
step S7: and depositing source metal 1 covering a source region and the dielectric layer 2 above the SiC epitaxial layer 6, depositing drain metal 8 below the SiC substrate 7, and annealing at the high temperature of 1000 ℃ to prepare ohmic contact.
Si ion implantation is carried out on the part of the SiC epitaxial layer which is not implanted with the doping materials below the grid electrode, the SiC is amorphized by the ion implantation, the oxidation speed of the SiC can be improved, and the preparation of a local thick oxidation layer is realized, so that the capacitance value between the grid electrode and the drain electrode is reduced, the working frequency of the device is improved, and the dynamic loss of the device is reduced.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. A preparation method of a low-grid-drain capacitance SiC DI-MOSFET comprises the following specific steps:
step S1: selecting an epitaxial wafer with a SiC epitaxial layer (6) grown on the upper surface of the SiC substrate (7) in a homogeneous manner;
step S2: carrying out p-type doping on a local area of the upper surface of the SiC epitaxial layer (6) to form a p-type doped area (5), forming an n-type ion implantation area on the upper surface of the p-type doped area (5) through ion implantation to form an n-type doped area (4), and carrying out high-temperature annealing activation to implant impurities, wherein the upper surface of the p-type doped area (5) is superposed with the upper surface of the n-type doped area (4), the p-type doped area (5) and the n-type doped area (4) jointly form a source area, and the p-type doped area (5) surrounds the n-type doped area (4);
step S3: injecting local Si ions (9) into the region which is not injected and doped on the upper surface of the SiC epitaxial layer (6) through a photoetching mask to amorphize SiC;
step S4: carrying out thermal oxidation treatment to oxidize the non-crystallized ion implantation region (9), the p-type doped region (5), the n-type doped region (4) and the exposed part of the upper surface of the SiC epitaxial layer (6) so as to form an oxidation dielectric layer (2);
step S5: depositing a grid electrode conducting material (3) on the surface of the oxidized dielectric layer (2) and etching off small parts on two sides, so that the grid electrode conducting material (3) can cover a part of the p-type doped region (5) and the n-type doped region (4) in the vertical direction;
step S6: depositing or growing a dielectric layer (2) to completely cover the grid conductive material (3), and etching the dielectric layer 2 to form a source contact hole;
step S7: and depositing source metal (1) covering the source region and the dielectric layer (2) above the SiC epitaxial layer (6), depositing drain metal (8) below the SiC substrate (7), and annealing to prepare ohmic contact.
2. The method of claim 1, wherein the method comprises the steps of: the temperature for activating the implanted impurity by the high temperature annealing in the step S2 is 1200-2000 ℃.
3. The method of claim 1, wherein the method comprises the steps of: the grid conductive material (3) is metal, polysilicon or alloy of metal and Si, or is a laminated structure of 2 or more than 2 of metal, polysilicon and Si.
4. The method of claim 1, wherein the method comprises the steps of: the doping concentration of the n-type doping region (4) is 1x1016cm-3-1x1020cm-3(ii) a The doping concentration of the p-type doping region (5) is 1x1013cm-3-1x1019cm-3。
5. The method of claim 1, wherein the method comprises the steps of: the SiC epitaxial wafer consists of an N + SiC substrate and an N-type epitaxial layer, the crystal forms of the SiC epitaxial layer (6) and the SiC substrate (7) are 4H or 6H, and the thickness of the SiC epitaxial layer (6) is 0-500 um.
6. The method of claim 1, wherein the method comprises the steps of: in the step S3, the implantation depth of the local Si ion implantation region (9) is 30nm-1000nm, and the concentration is 1x1018cm-3-1x1022cm-3。
7. The method of claim 1, wherein the method comprises the steps of: in the step S4, the dielectric layer (2) is SiO2Oxide layer to form SiO2The temperature of the thermal oxidation treatment of the oxide layer is 600-2000 ℃, and the oxidizing gas is dry oxygen, wet oxygen, NO, N2O、NO2And oxygen or a mixed gas containing nitrogen.
8. The method of claim 1, wherein the method comprises the steps of: in the step S6, the dielectric layer (2) is SiO2The oxide layer is formed by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or thermal oxidation of a layer of polysilicon, amorphous silicon, or single crystal silicon.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112750912A (en) * 2021-02-18 2021-05-04 厦门芯一代集成电路有限公司 High-voltage silicon carbide MOS device and preparation method thereof
CN113506829A (en) * 2021-07-05 2021-10-15 西安卫光科技有限公司 Step gate dielectric layer structure and manufacturing method thereof
CN114335152A (en) * 2022-03-02 2022-04-12 江苏游隼微电子有限公司 Silicon carbide power semiconductor device and preparation method thereof
CN116230753A (en) * 2023-04-21 2023-06-06 南京第三代半导体技术创新中心有限公司 Gate thickening dielectric layer for silicon carbide field effect transistor and manufacturing method thereof

Citations (14)

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