CN105161540A - VDMOS device structure with low miller capacitance and manufacturing method of VDMOS device structure - Google Patents
VDMOS device structure with low miller capacitance and manufacturing method of VDMOS device structure Download PDFInfo
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- CN105161540A CN105161540A CN201510585417.3A CN201510585417A CN105161540A CN 105161540 A CN105161540 A CN 105161540A CN 201510585417 A CN201510585417 A CN 201510585417A CN 105161540 A CN105161540 A CN 105161540A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 53
- 229920005591 polysilicon Polymers 0.000 claims abstract description 53
- 230000003647 oxidation Effects 0.000 claims abstract description 10
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 35
- 229910052760 oxygen Inorganic materials 0.000 claims description 35
- 239000001301 oxygen Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 30
- 238000000407 epitaxy Methods 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- MEYZYGMYMLNUHJ-UHFFFAOYSA-N tunicamycin Natural products CC(C)CCCCCCCCCC=CC(=O)NC1C(O)C(O)C(CC(O)C2OC(C(O)C2O)N3C=CC(=O)NC3=O)OC1OC4OC(CO)C(O)C(O)C4NC(=O)C MEYZYGMYMLNUHJ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention provides a VDMOS device structure with low miller capacitance and a manufacturing method of the VDMOS device structure. A polysilicon gate of the device structure is divided into two parts, namely a control gate and a shielding gate, wherein the polysilicon gate on a channel is called the control gate to control the channel to open and close; and polysilicon on a thick field oxide layer is connected or not connected with a source electrode, and is called the shielding gate. According to the manufacturing method of the novel VDMOS device, the conventional manufacturing method of the VDMOS needs to be combined with a local oxidation (LOCOS) technology; and the control gate and the shielding gate are simultaneously formed by a once gate technology, so that the cost of manufacturing the device is reduced. Through introduction of a thick oxide region 10, the miller capacitance of the device can be significantly reduced, so that the switching characteristic of the VDMOS device is improved.
Description
Technical field
The invention belongs to semiconductor device and manufacture technics field, relate to a kind of VDMOS device structure with low miller capacitance and preparation method thereof.
Background technology
Vertical double diffusion isolated-gate field effect transistor (IGFET) (VDMOS) is the most important part in power device field.Because VDMOS has the advantages such as easy driving, switching speed is fast, accessible site, technique are simple, it is widely used in the middle of power supply, pressure drop converter and electric machine controller constant power equipment.Current VDMOS device mostly adopts polysilicon self aligned process manufacture, first growing deposit one deck polysilicon on the silicon single crystal flake having gate oxidation films, then diffusion window is etched on the polysilicon, impurity is diffused in silicon single crystal body by this window, form source electrode and drain diffusion regions, form the polygate electrodes of conduction simultaneously.When designing VDMOS, mainly pay close attention to the conducting resistance of device, puncture voltage and electric capacity.For the VDMOS of conventional structure, conducting resistance and puncture voltage depend primarily on drift region length and the doping content of device, and electric capacity depends primarily on the thickness of gate oxide and the area of polygate electrodes.Gate electrode covers on cellular region can bring larger electric capacity.In the various electric capacity of VDMOS device, the most directly act on it is crucial that the reduction of the miller capacitance Cgd between grid leak, Cgd has the raising of devices switch speed and the reduction of power consumption.
Chinese patent CN102569386A proposes a kind of VDMOS device with shield grid, has less miller capacitance than conventional structure.Compared with conventional structure, the structure in patent CN10256938A just processes in grid part, is divided into control gate and shield grid two parts.Its manufacture craft is similar with conventional structure VDMOS, but will use twice grid technique when making polysilicon gate: first make control gate, then make shield grid.Twice grid technique just means the uncertainty that more cost and process deviation bring, and this patent for once grid technique, thus more save cost, be also more conducive to the performance improving device.
Summary of the invention
The problem to be solved in the present invention is to provide a kind of VDMOS device structure and the manufacture method with low miller capacitance.The polysilicon gate with the VDMOS device of low miller capacitance provided by the invention divides control gate and shield grid two parts, the polysilicon gate be wherein positioned on raceway groove is called control gate, control raceway groove to open and turn off, and the polysilicon be positioned at above the oxygen layer of thick field is connected with source electrode or is not connected, be called shield grid.The manufacture method of described novel VDMOS device needs the manufacture method of conventional VDMOS to combine with selective oxidation (LOCOS) technique.The introducing of described thick oxidation area 10 significantly can reduce the miller capacitance of device, thus improves the switching characteristic of VDMOS device.
For solving the problems of the technologies described above, the technical scheme that this patent adopts is:
Have a VDMOS device for low miller capacitance, its structure cell as shown in Figure 1, comprises N+ type substrate 8, is positioned at the N-type epitaxy layer 7 in N+ substrate 8 front, is positioned at the metal leakage pole 9 at N+ type substrate 8 back side; Both sides, N-type epitaxy layer 7 top have two the P-tagmas 5 be parallel to each other, and have separate N+ source region 6 and P+ body contact zone 4 in each P-tagma 5 respectively; N-type epitaxy layer 7 surface between two P-tagmas 5 has thick field oxygen layer 10, region surface between thick field oxygen layer 10 and two N+ source regions 6 has one deck gate oxide 12 respectively, gate oxide 12 surface has polysilicon control grid electrode 2, and oxygen layer 10 surface, thick field has polysilicon shield gate electrode 3; Metal source 1 is connected with P+ body contact zone 4 with N+ source region 6, and polysilicon shield gate electrode 3 is connected with metal source 1 or is not connected, and realizes isolating between metal source 1 and polysilicon control grid electrode 2 by spacer medium 11.
The thickness of described thick field oxygen layer 10 is micron dimension.
Compared with conventional VDMOS device, this patent has made thick field oxygen layer 10 between two P type tagmas 5, and polysilicon gate is divided into control gate 2 and shield grid 3, and control gate 2 is positioned at above raceway groove, have part to ride in thick field oxygen layer 10, shield grid 3 is positioned at above thick field oxygen layer 10.When drain terminal 9 adds malleation, N-type epitaxy layer 7 surface forms depletion region, and the depletion region of conventional VDMOS device is along N-type epitaxy layer 7 surface distributed between territory, p type island region 5 and territory, p type island region 5.Obviously, after introducing thick field oxygen layer 10, the depletion region distributed along territory, p type island region 5 is constant, but the depletion region on N-type epitaxy layer 7 surface between territory, p type island region 5 will along thick field oxygen layer 10 and the distribution of N-type epitaxy layer 7 interface.After shield grid 3 connects source electrode, shielding action can also be played to the electric charge on N-type epitaxy layer 7 surface.Therefore, overall Cgd will reduce.
Present invention also offers a kind of manufacture method with the VDMOS device of low miller capacitance, comprise the following steps:
1) in N+ type substrate 8 surface deposition N-type epitaxy layer 7;
2) location oxidation of silicon process is utilized to make thick field oxygen layer 10 on N-type epitaxy layer 7 surface;
3) at N-type epitaxy layer 7 surface and thick field oxygen layer 10 superficial growth gate oxide 12;
4) the gate oxide 12 surface deposition polysilicon on oxygen layer 10 surface, thick field forms polysilicon shield gate electrode 3, and the gate oxide 12 surface deposition polysilicon in oxygen layer 10 both sides, thick field forms polysilicon control grid electrode 2; Wherein, polysilicon shield gate electrode 3 does not contact with polysilicon control grid electrode 2 and is formed simultaneously;
5) gate oxide 12 outside photoetching polysilicon control grid electrode 2, exposes P-tagma 5 and injects window, then adopts ion implantation and push away trap technique to form two P-tagmas 5; In each P-tagma 5, adopt ion implantation more respectively and push away trap technique and form N+ source region 6 and P+ body contact zone 4;
6) with other subsequent process steps that traditional handicraft is identical.
The manufacture method with the VDMOS device of low miller capacitance provided by the invention, its core is before doing gate oxidation 12 layers, first make a thick field oxygen layer 10, because first described structure has made thick field oxygen layer 10, therefore in the process of the making control gate 2 carried out subsequently and shield grid 3, only need grid technology just can formation control grid 2 and shield grid 3, and as in patent CN102569386A, twice gate fabrication process need not be needed.So just greatly save the cost of making devices, also contribute to the performance of boost device.
Accompanying drawing explanation
Fig. 1 is a kind of structural representation with the VDMOS device of low miller capacitance provided by the invention.
In Fig. 1,1 is metal source, and 2 is polysilicon control grid electrodes, and 3 is polysilicon shield gate electrodes, and 4 is P+ body contact zones, 5 is P-tagmas, and 6 is N+ source regions, and 7 is N-type epitaxy layer, and 8 is N+ substrates, 9 is metal leakage pole, and 10 is thick field oxygen layer, and 11 is spacer mediums, and 12 is gate oxides.
What Fig. 2-a-Fig. 2-f provided is a kind of step of preparation process with the VDMOS device of low miller capacitance provided by the invention.
Fig. 2-a represents the formation of epitaxial loayer 7.
Fig. 2-b represents the formation of thick field oxygen layer 10.
Fig. 2-c represents the formation of gate oxide 12.
Fig. 2-d represents the formation of polysilicon control grid electrode 2 and polysilicon shield gate electrode 3.
Fig. 2-e represents the formation in P-tagma 5 and N+ source region 6.
Fig. 2-f represents the step that residue is identical with traditional handicraft.
Embodiment
The VDMOS device with low miller capacitance provided by the invention, its structure cell as shown in Figure 1, comprises N+ type substrate 8, is positioned at the N-type epitaxy layer 7 in N+ substrate 8 front, is positioned at the metal leakage pole 9 at N+ type substrate 8 back side; Both sides, N-type epitaxy layer 7 top have two the P-tagmas 5 be parallel to each other, and have separate N+ source region 6 and P+ body contact zone 4 in each P-tagma 5 respectively; N-type epitaxy layer 7 surface between two P-tagmas 5 has thick field oxygen layer 10, region surface between thick field oxygen layer 10 and two N+ source regions 6 has one deck gate oxide 12 respectively, gate oxide 12 surface has polysilicon control grid electrode 2, and oxygen layer 10 surface, thick field has polysilicon shield gate electrode 3; Metal source 1 is connected with P+ body contact zone 4 with N+ source region 6, and polysilicon shield gate electrode 3 is connected with metal source 1 or is not connected, and realizes isolating between metal source 1 and polysilicon control grid electrode 2 by spacer medium 11.After gate oxide 12 completes, control gate 2 and shield grid 3 are completed by a grid technique.Shield grid 2 is connected with source electrode 1, and is isolated by spacer medium 11 and control gate 2.Shield grid 3 also can be set to unsettled.Thick field oxygen layer 10 makes prior to gate oxide 12, adopts selective oxidation (LOCOS) technique during making.
The specific embodiment of the present invention and processing step are described below:
1. adopt N type semiconductor material as substrate 8, at Grown one deck N type semiconductor material as epitaxial loayer 7 (see Fig. 2-a).Substrate is that N-type is highly doped, and epitaxial loayer is N-type light dope.Epitaxial loayer is the main withstand voltage region of device, and its doping content and thickness determine the epitaxial electric resistance in the withstand voltage of device and conducting resistance.
2. make thick field oxygen layer 10 (see Fig. 2-b) by selective oxidation (LOCOS) technique.First at epitaxial loayer surface deposition one deck Si
3n
4; Then carry out photoetching and etching, remove middle Si
3n
4, retain the Si at two ends
3n
4as the mask be oxidized after a while; Finally be oxidized, not by Si
3n
4the part that mask blocks can be oxidized, this completes the making of thick field oxygen layer 10.Because oxidizing process not only longitudinally carrying out, also can laterally can be carried out, therefore Si
3n
4the silicon at occlusion area edge also can be oxidized, thus form " beak ".
3. grow gate oxide 12 (see Fig. 2-c).Dry wet dry oxidizing process is adopted to grow the compact oxidation layer that a layer thickness is the 1000 Izod right sides.
4. depositing polysilicon on gate oxide 12, then photoetching and etching are carried out to described polysilicon, form polysilicon control grid electrode 2 and polysilicon shield gate electrode 3, polysilicon control grid electrode 2 is positioned on raceway groove, and polysilicon shield gate electrode 3 is positioned at (see Fig. 2-d) in thick field oxygen layer 10.Polysilicon control grid electrode 2 has part to ride in thick field oxygen layer 10, can avoid like this, when carrying out self-registered technology after a while, between polysilicon control grid electrode 2 and thick field oxygen layer 10, forming unnecessary P-tagma.The deposit of polysilicon adopts CVD (Chemical Vapor Deposition) method usually, and the etching of polysilicon adopts dry etch process usually.Now oxide layer will etch, but will retain the thickness being not less than 700 dusts after etching.
5. the P-tagma 5 of making devices and N+ source region 6.First do mask plate with polysilicon gate, carry out P type tagma ion implantation, after carrying out thermal diffusion, form P type tagma 5 (see Fig. 2-e).Then still utilize polysilicon gate as mask plate, carry out source region ion implantation, after carrying out thermal diffusion, form N+ source region 6.The doping type in source region and drift region just as, but concentration is far above drift region.
6. step is after this identical with traditional handicraft: deposit tunic; By photoetching, do and carve formation contact hole, with metal filling perforation, with dry quarter or cmp removing unnecessary metal; Depositing metal film, carries out photoetching to metal, dry quarter finally forms figure; To thinning back side of silicon wafer, form metal film (see Fig. 2-f) overleaf.
Claims (3)
1. one kind has the VDMOS device of low miller capacitance, its structure cell comprises N+ type substrate (8), be positioned at the N-type epitaxy layer (7) in N+ substrate (8) front, be positioned at the metal leakage pole (9) at N+ type substrate (8) back side; N-type epitaxy layer (7) both sides, top have two the P-tagmas (5) be parallel to each other, and have separate N+ source region (6) and P+ body contact zone (4) respectively in each P-tagma (5); N-type epitaxy layer (7) surface between two P-tagmas (5) has thick field oxygen layer (10), region surface between thick field oxygen layer (10) and two N+ source regions (6) has one deck gate oxide (12) respectively, gate oxide (12) surface has polysilicon control grid electrode (2), and oxygen layer (10) surface, thick field has polysilicon shield gate electrode (3); Metal source (1) is connected with P+ body contact zone (4) with N+ source region (6), polysilicon shield gate electrode (3) is connected with metal source (1) or is not connected, and realizes isolating between metal source (1) and polysilicon control grid electrode (2) by spacer medium (11).
2. the VDMOS device with low miller capacitance according to claim 1, is characterized in that, the thickness of described thick field oxygen layer (10) is micron dimension.
3. have a preparation method for the VDMOS device of low miller capacitance, it is characterized in that, preparation process comprises the following steps:
1) in N+ type substrate (8) surface deposition N-type epitaxy layer (7);
2) location oxidation of silicon process is utilized to make thick field oxygen layer (10) on N-type epitaxy layer (7) surface;
3) in N-type epitaxy layer (7) surface and thick field oxygen layer (10) superficial growth gate oxide (12);
4) form polysilicon shield gate electrode (3) at gate oxide (12) the surface deposition polysilicon on surface, thick field oxygen layer (10), gate oxide (12) the surface deposition polysilicon in oxygen layer (10) both sides, thick field forms polysilicon control grid electrode (2); Wherein, polysilicon shield gate electrode (3) does not contact with polysilicon control grid electrode (2) and is formed simultaneously;
5) gate oxide (12) in photoetching polysilicon control grid electrode (2) outside, exposes P-tagma (5) and injects window, then adopts ion implantation and push away trap technique to form two P-tagmas (5); In each P-tagma (5), adopt ion implantation more respectively and push away trap technique and form N+ source region (6) and P+ body contact zone (4);
6) with other subsequent process steps that traditional handicraft is identical.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946357A (en) * | 2017-12-27 | 2018-04-20 | 江苏中科君芯科技有限公司 | IGBT device with low Miller capacitance |
| CN108257872A (en) * | 2018-01-12 | 2018-07-06 | 北京品捷电子科技有限公司 | The preparation method of SiC bases DI-MOSFET a kind of and SiC bases DI-MOSFET |
| CN108565289A (en) * | 2018-06-26 | 2018-09-21 | 南京方旭智芯微电子科技有限公司 | The manufacturing method of superjunction field-effect tube and superjunction field-effect tube |
| CN111129155A (en) * | 2019-12-25 | 2020-05-08 | 重庆伟特森电子科技有限公司 | Preparation method of low-gate-drain capacitance silicon carbide DI-MOSFET |
| CN111584365A (en) * | 2020-04-29 | 2020-08-25 | 北京时代民芯科技有限公司 | Manufacturing method of low-miller capacitance groove grid VDMOS device |
| WO2021042582A1 (en) * | 2019-09-03 | 2021-03-11 | 苏州东微半导体有限公司 | Semiconductor power device |
| CN112802906A (en) * | 2021-04-15 | 2021-05-14 | 成都蓉矽半导体有限公司 | Separated gate planar MOSFET device with floating gate |
| CN114361239A (en) * | 2021-12-31 | 2022-04-15 | 电子科技大学 | VDMOS device with low miller capacitance |
| CN114551586A (en) * | 2022-04-27 | 2022-05-27 | 成都蓉矽半导体有限公司 | Silicon carbide split gate MOSFET cell integrated with grid-controlled diode and preparation method |
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| CN102005480A (en) * | 2010-10-28 | 2011-04-06 | 电子科技大学 | High-voltage low-on-resistance LDMOS device and manufacturing method thereof |
| CN102569386A (en) * | 2010-12-17 | 2012-07-11 | 上海华虹Nec电子有限公司 | VDMOS (vertical double-diffused metal oxide semiconductor) device with shield grid and preparation method of VDMOS device |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946357A (en) * | 2017-12-27 | 2018-04-20 | 江苏中科君芯科技有限公司 | IGBT device with low Miller capacitance |
| CN108257872A (en) * | 2018-01-12 | 2018-07-06 | 北京品捷电子科技有限公司 | The preparation method of SiC bases DI-MOSFET a kind of and SiC bases DI-MOSFET |
| WO2019137093A1 (en) * | 2018-01-12 | 2019-07-18 | 重庆伟特森电子科技有限公司 | Sic-based di-mosfet preparation method and sic-based di-mosfet |
| CN108565289A (en) * | 2018-06-26 | 2018-09-21 | 南京方旭智芯微电子科技有限公司 | The manufacturing method of superjunction field-effect tube and superjunction field-effect tube |
| WO2021042582A1 (en) * | 2019-09-03 | 2021-03-11 | 苏州东微半导体有限公司 | Semiconductor power device |
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| CN111584365B (en) * | 2020-04-29 | 2024-01-30 | 北京时代民芯科技有限公司 | Manufacturing method of low miller capacitance trench gate VDMOS device |
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| CN114361239A (en) * | 2021-12-31 | 2022-04-15 | 电子科技大学 | VDMOS device with low miller capacitance |
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