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CN108538911B - Optimized L-type tunneling field effect transistor and preparation method thereof - Google Patents

Optimized L-type tunneling field effect transistor and preparation method thereof Download PDF

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Publication number
CN108538911B
CN108538911B CN201810398738.6A CN201810398738A CN108538911B CN 108538911 B CN108538911 B CN 108538911B CN 201810398738 A CN201810398738 A CN 201810398738A CN 108538911 B CN108538911 B CN 108538911B
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silicon
gate
etching
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CN108538911A (en
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李聪
闫志蕊
庄奕琪
赵小龙
郭嘉敏
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Chongqing Institute Of Integrated Circuit Innovation Xi'an University Of Electronic Science And Technology
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]

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Abstract

The invention discloses an optimized L-type tunneling field effect transistor and a preparation method thereof, mainly solving the problems of low on-state current and serious bipolar effect of the existing device, and comprising the following steps: the SOI device comprises an SOI substrate (1), an isolation groove (2), a source region (3), a channel region (4), a drain region (6), a gate region (5) and a conducting layer (7); the isolation grooves (2) are positioned at two sides of the SOI substrate (1); the source region (3), the channel region (4) and the drain region (6) are positioned on the upper surface of the SOI substrate; the gate region (5) is positioned on the upper side of the channel region (4); the source region (3) is made of germanium semiconductor materials, the gate region (5) is made of a heterogeneous gate dielectric structure, a high-K gate dielectric material is adopted on one side close to the source region, and a low-K gate dielectric material is adopted on one side close to the drain region; and a space S is arranged between the right boundary of the drain region (6) and the gate region (5). The invention can effectively inhibit the bipolar effect, improves the driving current and can be used for manufacturing large-scale integrated circuits.

Description

Optimized L-type tunneling field effect transistor and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to an optimized L-shaped tunneling field effect transistor and a preparation method thereof, which can be used for manufacturing large-scale integrated circuits.
Background
With the advancement of semiconductor integration technology, the development of integrated circuit technology following "Moore's law" has entered the nanometer scale. However, challenges from short channel effects, parasitic effects, and quantum tunneling have made scaling conventional CMOS transistors more and more difficult to meet with the continuing development of integrated circuits.
The tunneling field effect transistor TFET works based on a band-to-band tunneling quantum tunneling effect mechanism, and the subthreshold swing can break through the limitation of the subthreshold limit value of 60mV/decade of the traditional MOSFET at room temperature. Therefore, the TFET device has fast switching characteristics and low leakage current, can effectively reduce the power consumption of the device, and is considered as an important way for continuing the Moore law.
However, the current TFET device has the problems of relatively small on-state current, suboptimal subthreshold swing, bipolar effect and the like, so that the wide application of the TFET device in the aspect of circuits is severely limited. In order to improve the performance of the TFET device, scientists propose an L-type TFET device, and the structure improves the on-state current of the TFET device to a certain extent. However, compared with the MOSFET device, the silicon-based TFET device still faces the problems of small driving current and serious bipolar effect, so that the application of the silicon-based TFET device is limited. Therefore, increasing the driving current and effectively suppressing the bipolar effect are problems to be solved in the silicon-based TFET.
Disclosure of Invention
The invention aims to provide an optimized L-type tunneling field effect transistor and a preparation method thereof aiming at the defects of the traditional silicon-based TFET device, so as to improve the driving current, reduce the leakage current and effectively inhibit the bipolar effect.
In order to achieve the above object, the present invention provides an optimized L-type tunneling field effect transistor, including: the SOI substrate, an isolation groove, a source region, a channel region, a drain region, a gate region and a conducting layer; the isolation grooves are positioned at two sides of the SOI substrate; the source region, the channel region and the drain region are positioned on the upper surface of the SOI substrate; the gate region is located on the upper side of the channel region, and is characterized in that:
the source region is made of germanium semiconductor material;
the gate region adopts a heterogeneous gate dielectric structure, and adopts a high-K gate dielectric material at one side close to the source region and a low-K gate dielectric material at one side close to the drain region;
and an interval S is arranged at the right boundary of the drain region and the gate region.
In order to achieve the above object, the method for manufacturing an optimized L-type tunneling field effect transistor of the present invention comprises the following steps:
1) sequentially preparing an SOI substrate comprising bottom silicon, a buried oxide layer and top silicon;
2) etching two sides of the top layer silicon to form a shallow trench isolation region, and performing oxide deposition to form an isolation groove;
3) etching the surface of the top layer silicon to form a source region groove, epitaxially depositing a germanium material to fill the source region groove at the temperature of 300-600 ℃, and introducing boron doping gas into the germanium to carry out in-situ doping on the source region to form a P-type source region;
4) etching the surface of the top layer silicon to form an L-shaped groove structure, and epitaxially depositing an intrinsic silicon semiconductor layer to form an L-shaped channel layer;
5) growing a heterogeneous gate dielectric layer on the surface of the intrinsic silicon semiconductor layer, and depositing polycrystalline silicon to form a gate region;
6) forming a drain region pattern by adopting a photoetching process at the position of a quarter of gate length or a half of gate length or three quarters of gate length between the top silicon surface and the right boundary of the gate region, implanting arsenic ions with the dose of 3e 14-9 e15 into the drain region by utilizing an ion implantation process, wherein the implantation energy is 30-50 keV, annealing and activating impurities to form the doped region with the doping concentration of 1018cm-3～1020cm-3The N-type drain region of (1);
7) and photoetching lead windows in a source region, a drain region and a grid region, depositing metal, photoetching a lead, forming a source electrode, a drain electrode and a gate electrode, and finally finishing the preparation of the optimized L-shaped tunneling field effect transistor.
The invention has the following advantages:
firstly, the source region of the invention adopts germanium material, and the germanium material has smaller effective mass and narrower forbidden bandwidth, thereby shortening the tunneling distance of carriers, effectively improving the driving current of the device and reducing the swing amplitude of sub-threshold;
secondly, the grid region adopts a heterogeneous grid medium structure, and the right boundary of the drain region and the grid region is provided with the interval S, so that a carrier reverse tunneling potential barrier is increased, the tunneling probability of the carrier is reduced when the device is in a reverse working state, and the bipolar effect is effectively inhibited;
thirdly, the manufacturing process of the invention is simple and easy to implement, is compatible with the existing semiconductor manufacturing process and can be realized at low cost.
Drawings
FIG. 1 is a schematic diagram of the device structure of an optimized L-type tunneling field effect transistor according to the present invention;
FIG. 2 is a schematic flow chart of an optimized L-type tunneling field effect transistor device according to the present invention;
FIG. 3 is a simulation characteristic curve chart of CAD software in embodiment 1 of the present invention;
FIG. 4 is a simulation characteristic curve chart of CAD software in embodiment 2 of the present invention;
fig. 5 is a simulation characteristic curve diagram of the cad software according to embodiment 3 of the present invention.
Detailed Description
The embodiments and effects of the present invention will be described in detail below with reference to the accompanying drawings:
referring to fig. 1, the optimized L-type tunneling field effect transistor of the present invention includes an SOI substrate 1, an isolation trench 2, a source region 3, a channel region 4, a drain region 6, a gate region 5, and a conductive layer 7, wherein the substrate 1 of the SOI structure is composed of an initial silicon wafer 11, an intermediate oxide buried layer 12, and a Si epitaxial layer 13, the gate region 5 is composed of a high-K gate dielectric layer 51, a low-K gate dielectric layer 52, and a polysilicon gate 53, and the conductive layer 7 is composed of a source electrode 71, a gate electrode 72, and a drain electrode 73; the isolation grooves 2 are positioned at two sides of the Si epitaxial layer 13; the source region 3, the channel region 4 and the drain region 6 are positioned on the upper surface of the Si epitaxial layer 13; the gate region 5 is covered on the channel region 4; the source electrode 71, the gate electrode 72, and the drain electrode 73 of the conductive layer 7 are led out from the surfaces of the source region 3, the gate region 5, and the drain region 6, respectively. Specifically, the source region 3 is made of a germanium material with a narrow band gap; the gate region 5 adopts a heterogeneous gate dielectric structure, one side close to the source region adopts a high-K gate dielectric material, and one side close to the drain region adopts a low-K gate dielectric material; the right boundary of the drain region 6 and the gate region 5 is provided with an interval S set to a quarter gate length, a half gate length, or a three-quarter gate length.
Referring to fig. 2, the present invention provides the following three embodiments.
Embodiment 1, a tunneling field effect transistor with a drain region separated from the right boundary of a gate region by a quarter of the gate length is manufactured.
Step 1, an SOI substrate is manufactured as shown in fig. 2 (a).
1a) Generating an oxide buried layer on the initial silicon wafer at the bottom layer by dry oxygen oxidation;
1b) and growing a top silicon epitaxial layer on the buried oxide layer through an epitaxial growth process to form the SOI substrate.
And 2, etching two sides of the top layer silicon to form an isolation groove, as shown in (b) of fig. 2.
2a) Growing SiO on the top silicon surface of SOI substrate2Forming a first SiO2Layer, growing the first Si on the surface of the layer3N4A layer forming a first protective layer;
2b) forming a shallow trench isolation pattern on the first protection layer by using a photoetching machine and utilizing a photoetching process;
2c) etching the shallow trench isolation pattern by using a dry etching process to form a shallow trench isolation region, wherein the etching depth is the thickness of the top silicon;
2d) depositing a silicon dioxide material to fill the shallow trench isolation region by using chemical vapor deposition equipment through a chemical vapor deposition process at the temperature of 600 ℃;
2e) and mechanically polishing the surface of the top silicon by using a polishing machine, and removing redundant silicon dioxide on the surface of the top silicon to flatten the surface of the top silicon to form an isolation groove.
Step 3, forming the doping concentration of 10 on the surface of the top layer silicon18cm-3As shown in fig. 2 (c).
3a) Growing SiO on the surface of the top layer silicon2Forming a second SiO2Layer, and growing a second Si layer on the surface of the layer3N4A layer forming a second protective layer;
3b) forming a source region pattern on the second protective layer at a set position by using a photoetching machine and a photoetching process;
3c) etching the source region pattern by using a dry etching process to form a source region groove;
3d) depositing germanium material in the groove of the source region by using a selective epitaxial growth process to completely fill the groove, introducing boron doping gas to carry out in-situ doping on the source region at the dose of 3e14, and annealing to realize in-situ activation of doping elements to form a doping concentration of 1018cm-3The highly doped P-type source region.
And 4, forming an L-shaped intrinsic silicon channel region on the surface of the top layer silicon, as shown in (d) of FIG. 2.
4a) Growing SiO2 on the surface of the top silicon layer to form a third SiO2 layer, and growing a third Si3N4 layer on the surface of the top silicon layer to form a third protective layer;
4b) photoetching and forming a groove area pattern on the third protective layer by using a photoetching machine and a photoetching process;
4c) etching the groove region pattern by using a dry etching process to form a groove;
4d) and epitaxially depositing intrinsic silicon material in the groove to form an L-shaped intrinsic silicon channel layer.
And 5, preparing an L-shaped gate region of the heterogeneous gate dielectric structure, as shown in (e) of fig. 2.
5a) Epitaxially depositing a high-K dielectric gate oxide layer on the surface of the L-shaped intrinsic silicon channel layer;
5b) etching the transverse high-K dielectric gate oxide layer on the surface of the channel layer by using a selective etching process;
5c) depositing a low-K dielectric gate oxide layer on the surface of the channel layer by using chemical vapor deposition equipment at the temperature of 600 ℃ through a chemical vapor deposition process to form a heterogeneous gate dielectric layer;
5d) epitaxially depositing a heavily doped crystalline silicon gate material on the surface of the heterogeneous gate dielectric layer;
5e) and mechanically polishing the surface of the top layer silicon by using a polishing machine to flatten the surface and remove the polycrystalline silicon and the gate oxide layer on the surface of the top layer silicon, forming a gate graph on the polycrystalline silicon surface of the gate trench by using a photoetching machine and utilizing a photoetching process, and selectively etching off the polycrystalline silicon material and the gate oxide layer material on the surface of the gate trench to form the L-shaped gate region.
Step 6, forming a doping concentration of 10 on the surface of the top silicon layer18cm-3As shown in fig. 2 (f).
6a) Growing SiO2 on the top layer silicon and the surface of the groove to form a fourth SiO2 layer, and growing fourth Si on the surface of the layer3N4A layer forming a fourth protective layer;
6b) forming a drain region pattern on the fourth protective layer and at a distance of a quarter of the gate length from the right boundary of the gate region by using a photoetching machine and utilizing a photoetching process;
6c) etching the drain region pattern by using a dry etching process to form a shallow groove capable of exposing the drain region;
6d) using an ion implanter to implant arsenic ions with a dose of 3e14 at the groove position by an ion implantation process, wherein the implantation energy is 30keV, and the doping concentration is 1018cm-3The N-type drain region of (1);
6e) and (3) rapidly annealing at high temperature at the temperature of 1000 ℃ to activate impurities.
Step 7, a conductive layer is fabricated, as in (g) of fig. 2.
7a) Depositing a silicon nitride insulating layer on the surface of the top silicon layer by using chemical vapor deposition equipment and a chemical vapor deposition process at the temperature of 600 ℃;
7b) mechanically polishing the surface of the silicon nitride insulating layer by using a polishing machine to make the silicon nitride insulating layer smooth and flat;
7c) sputtering metal on the surfaces of the insulating layer and the lead hole, alloying to form metal silicide, and etching off the metal on the surface of the metal silicide;
7d) and sputtering metal on the surfaces of the insulating layer and the lead hole again until the lead hole is filled, mechanically polishing the surface of the metal to be flat, and photoetching to form a source electrode, a gate electrode and a drain electrode to finish the manufacture of the optimized L-shaped tunneling field effect transistor.
Embodiment 2, a tunneling field effect transistor with a drain region spaced from the right boundary of a gate region by one-half gate length is fabricated.
Step one, an SOI substrate is manufactured, as shown in fig. 2 (a).
The specific implementation of this step is the same as in step 1 of example 1.
And step two, etching to form isolation grooves on two sides of the top layer silicon, as shown in (b) of fig. 2.
The specific implementation of this step is the same as step 2 of example 1.
Step three, forming the doping concentration of 10 on the surface of the top layer silicon19cm-3As shown in fig. 2 (c).
3.1) growing SiO on the surface of the top silicon2Forming a second SiO2Layer, and growing a second Si layer on the surface of the layer3N4A layer forming a second protective layer;
3.2) forming a source region pattern on the set position on the second protective layer by using a photoetching machine and utilizing a photoetching process;
3.3) etching the source region pattern by using a dry etching process to form a source region groove;
3.4) depositing germanium material in the groove of the source region by using a selective epitaxial growth process to completely fill the groove, simultaneously introducing boron doping gas to carry out in-situ doping on the source region with the dosage of 4e15, and then annealing to realize in-situ activation of doping elements to form the doping concentration of 1019cm-3The highly doped P-type source region.
And step four, forming an L-shaped intrinsic silicon channel region on the surface of the top layer silicon, as shown in (d) of FIG. 2.
The specific implementation of this step is the same as in step 4 of example 1.
And step five, preparing an L-shaped gate region of the heterogeneous gate dielectric structure, as shown in (e) of fig. 2.
The specific implementation of this step is the same as step 5 of example 1.
Step six, forming the doping concentration of 10 on the surface of the top layer silicon19cm-3As shown in fig. 2 (f).
6.1) growing SiO2 on the top layer silicon and the surface of the groove to form a fourth SiO2 layer, and growing a fourth Si on the surface of the layer3N4A layer forming a fourth protective layer;
6.2) forming a drain region pattern on the fourth protective layer and the right boundary of the gate region at a spacing of half the gate length by using a photoetching machine and utilizing a photoetching process;
6.3) etching at the pattern of the drain region by using a dry etching process to form a shallow groove capable of exposing the drain region;
6.4) using an ion implanter, implanting arsenic ions with the dose of 6e15 at the groove position by using an ion implantation process, wherein the implantation energy is 40keV, and the doping concentration is 1019cm-3The N-type drain region of (1);
6.5) annealing at 1000 deg.C and high temperature to activate impurities.
Step seven, manufacturing a conductive layer, as shown in (g) of fig. 2.
The specific implementation of this step is the same as step 7 of example 1, and the fabrication of the optimized L-type tunneling field effect transistor is completed.
Embodiment 3, a tunneling field effect transistor with a drain region three-quarters of the gate length spaced from the right boundary of the gate region is fabricated.
In the first step, an SOI substrate is manufactured as shown in fig. 2 (a).
The specific implementation of this step is the same as in step 1 of example 1.
And secondly, etching to form isolation grooves on two sides of the top layer silicon, as shown in (b) of FIG. 2.
The specific implementation of this step is the same as step 2 of example 1.
Thirdly, forming a doping concentration of 10 on the surface of the top silicon layer20cm-3As shown in fig. 2 (c).
Firstly, growing SiO on the top silicon surface2Forming a second SiO2Layer, and growing a second Si layer on the surface of the layer3N4A layer forming a second protective layer;
then, forming a source region pattern on the second protective layer at a set position by using a photoetching machine and a photoetching process;
then, etching the source region pattern by using a dry etching process to form a source region groove;
then, depositing germanium material in the groove of the source region by using a selective epitaxial growth process to completely fill the groove, simultaneously introducing boron doping gas to carry out in-situ doping on the source region, wherein the dosage is 5e15, annealing to realize in-situ activation of doping elements, and forming the doping concentration of 1020cm-3The highly doped P-type source region.
And a fourth step of forming an L-type intrinsic silicon channel region on the top silicon surface, as shown in fig. 2 (d).
The specific implementation of this step is the same as in step 4 of example 1.
And fifthly, preparing an L-shaped gate region of the heterogeneous gate dielectric structure, as shown in (e) of fig. 2.
The specific implementation of this step is the same as step 5 of example 1.
Sixthly, forming the doping concentration of 10 on the surface of the top silicon layer20cm-3As shown in fig. 2 (f).
First, SiO2 is grown on the top layer silicon and the surface of the groove to form a fourth SiO2 layer, and fourth Si is grown on the surface of the layer3N4A layer forming a fourth protective layer;
then, forming a drain region pattern on the fourth protective layer and the right boundary of the gate region at an interval of one-half gate length by using a photoetching machine and utilizing a photoetching process;
then, etching the drain region pattern by using a dry etching process to form a shallow groove capable of exposing the drain region;
then, arsenic ions with a dose of 9e15 were implanted into the recess by an ion implantation process using an ion implanter with an implantation energy of 50keV to form a doping concentration of 1020cm-3The N-type drain region of (1);
then, annealing is carried out at a high temperature under the temperature condition of 1000 ℃ to activate impurities.
Seventh, a conductive layer is formed, as shown in fig. 2 (g).
The specific implementation of this step is the same as step 7 of example 1, and the fabrication of the optimized L-type tunneling field effect transistor is completed.
The features and effects of the present invention can be further illustrated by the following simulation experiments,
the experimental contents are as follows:
experiment 1, I-V characteristic simulation was performed on the tunneling transistor and the conventional silicon-based L-type TFET of example 1 by computer aided design software, and the result is shown in fig. 3;
experiment 2, I-V characteristic simulation was performed on the tunneling transistor and the conventional silicon-based L-type TFET of example 2 by computer aided design software, and the result is shown in fig. 4;
experiment 3, I-V characteristic simulation was performed on the tunneling transistor and the conventional silicon-based L-type TFET of example 3 by computer aided design software, and the result is shown in fig. 5;
as can be seen from the comparison results of fig. 3 to fig. 5, compared with the conventional silicon-based L-type TFET device, the optimized L-type tunneling field effect transistor provided by the present invention has the advantages that the source region adopts the germanium semiconductor material with smaller effective mass and narrow forbidden bandwidth, the tunneling distance is shortened, the carrier tunneling rate is increased, and the carrier tunneling rate is further increased, so that the effective performance is improvedIncrease the drive current to 10-4A/mum; meanwhile, the invention can also be seen in that the bipolar effect is effectively inhibited while the on-state current is improved, and the reverse leakage current is always stabilized at 10-14A/mum is the order of magnitude, because the device of the invention is provided with the space S at the right boundary of the drain region and the gate region, and the performance change caused by the width of the reverse tunneling barrier is increased.
The foregoing description is only three specific examples of the present invention and is not intended to limit the invention, so that it will be apparent to those skilled in the art that various changes and modifications in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims (6)

1. A preparation method of an optimized L-shaped tunneling field effect transistor comprises an SOI substrate (1), an isolation groove (2), a source region (3), a channel region (4), a drain region (6), a gate region (5) and a conducting layer (7); the isolation grooves (2) are positioned at two sides of the SOI substrate (1); the source region (3), the channel region (4) and the drain region (6) are positioned on the upper surface of the SOI substrate; the gate region (5) is positioned on the upper side of the channel region (4); the preparation method is characterized by comprising the following preparation steps:
1) sequentially preparing an SOI substrate comprising bottom silicon, a buried oxide layer and top silicon;
2) etching two sides of the top layer silicon to form a shallow trench isolation region, and performing oxide deposition to form an isolation groove;
3) etching the surface of the top layer silicon to form a source region groove, epitaxially depositing a germanium material to fill the source region groove at the temperature of 300-600 ℃, and introducing boron doping gas into the germanium to carry out in-situ doping on the source region to form a P-type source region;
4) etching the surface of the top layer silicon to form an L-shaped groove structure, and epitaxially depositing an intrinsic silicon semiconductor layer to form an L-shaped channel layer;
5) growing a heterogeneous gate dielectric layer on the surface of the intrinsic silicon semiconductor layer, and depositing polycrystalline silicon to form a gate region;
6) on the top silicon surface and the gateForming a drain region pattern by adopting a photoetching process at the position of a quarter of gate length or a half of gate length or three quarters of gate length on the right boundary of the region, implanting arsenic ions with the dose of 3e 14-9 e15 into the drain region by utilizing an ion implantation process, wherein the implantation energy is 30-50 keV, annealing and activating impurities to form the doped concentration of 1018～1020cm-3The N-type drain region of (1);
7) and photoetching lead windows in a source region, a drain region and a grid region, depositing metal, photoetching a lead, forming a source electrode, a drain electrode and a gate electrode, and finally finishing the preparation of the optimized L-shaped tunneling field effect transistor.
2. The method of claim 1, wherein the step 2) of etching both sides of the top silicon to form shallow trench isolation regions is performed as follows:
2a) growing SiO on the top silicon surface of SOI substrate2To form a first SiO2Layer, growing the first Si on the surface of the layer3N4A layer forming a first protective layer;
2b) forming a shallow trench isolation region pattern on the first protection layer by utilizing a photoetching process;
2c) and etching the pattern of the shallow trench isolation region by using a dry etching process to form the shallow trench isolation region, wherein the etching depth is the thickness of the top silicon.
3. The method of claim 1, wherein the etching on the surface of the top silicon in step 3) to form the source region groove is performed as follows:
3a) growing SiO on the surface of the top layer silicon2To form a second SiO2Layer, and growing a second Si layer on the surface of the layer3N4A layer forming a second protective layer;
3b) forming a source region pattern on the second protective layer by using a photoetching process;
3c) and etching the source region pattern by using a dry etching process to form a source region groove.
4. The method of claim 1, wherein step 3) is in germaniumIntroducing boron doping gas to carry out in-situ doping on the source region, wherein the dosage is 3e 14-5 e15, and the doping concentration is 1018cm-3～1020cm-3。
5. The preparation method of claim 1, wherein the etching is performed on the surface of the top silicon layer in the step 4) to form an L-shaped groove structure, and the method comprises the following steps:
4a) growing SiO on the surface of the top layer silicon2Forming third SiO2Layer, growing third Si on the surface of the layer3N4A layer forming a third protective layer;
4b) photoetching the third protective layer to form an L-shaped groove region pattern;
4c) and etching the groove region pattern by using a dry etching process to form an L-shaped groove structure.
6. The preparation method of claim 1, wherein in the step 5), a heterogeneous gate dielectric layer is grown on the surface of the intrinsic silicon semiconductor layer, and a high-K gate dielectric is deposited on the surface of the L-type intrinsic silicon channel layer by using a chemical vapor deposition process; etching the transverse high-K gate dielectric on the surface of the channel layer by using a selective etching process; and then depositing a low-K gate dielectric on the surface of the channel layer by utilizing a chemical vapor deposition process to form a heterogeneous gate dielectric layer.
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