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CN117879590A - LVDS output driving circuit with pre-emphasis - Google Patents

LVDS output driving circuit with pre-emphasis Download PDF

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Publication number
CN117879590A
CN117879590A CN202311743052.3A CN202311743052A CN117879590A CN 117879590 A CN117879590 A CN 117879590A CN 202311743052 A CN202311743052 A CN 202311743052A CN 117879590 A CN117879590 A CN 117879590A
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CN
China
Prior art keywords
transistor
lvds
drain
capacitor
circuit
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CN202311743052.3A
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Chinese (zh)
Inventor
申梦园
邵刚
吕俊盛
刘颖
李嘉
孙丹
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Xian Xiangteng Microelectronics Technology Co Ltd
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Xian Xiangteng Microelectronics Technology Co Ltd
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Priority to CN202311743052.3A priority Critical patent/CN117879590A/en
Publication of CN117879590A publication Critical patent/CN117879590A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention belongs to the field of integrated circuits, and relates to an LVDS output drive circuit with pre-emphasis, which comprises a differential signal input end, a signal output end, an LVDS output stage circuit, an LVDS pre-emphasis circuit and a common mode feedback circuit; the differential signal input end is connected to the signal output end through the LVDS output stage circuit and the LVDS pre-emphasis circuit respectively; the signal output end is respectively connected to the LVDS output stage circuit and the LVDS pre-emphasis circuit in a feedback mode through the common mode feedback circuit. The invention provides an LVDS output driving circuit with pre-emphasis, which can reduce power supply fluctuation and realize the pre-emphasis function at a higher transmission rate.

Description

LVDS output driving circuit with pre-emphasis
Technical Field
The invention belongs to the field of integrated circuits, and relates to an LVDS output driving circuit, in particular to an LVDS output driving circuit with pre-emphasis.
Background
At present, the physical layer of the conventional bus communication protocol is high-speed serial transmission, the data rate is from Mbps to Gbps, and the transmission rate is very high. For such high-speed applications, especially in long-distance transmission, the channel attenuation due to the PCB, the connector directly affects the channel quality, which causes inter-symbol interference and thus increases signal jitter, and furthermore causes eye closure, resulting in communication failure. In order to increase the transmission distance and ensure the communication quality, a pre-emphasis technique can be adopted at the transmitting end. Pre-emphasis techniques are mainly used to boost the high frequency components of the rising and falling edges of a signal to cancel the high frequency signal attenuation caused by the channel. The most used pre-emphasis technology at present uses an inverter chain and a logic unit to enable an input signal to generate a transient pulse signal during data switching, and the signal can control a current tube of an LVDS output stage to generate a transient large current during data switching, so that rising and falling edges are quickened, and high-frequency signal attenuation caused in a signal transmission process is compensated. However, the structure uses the inverter link, so that the power supply ripple of the chip is larger, and meanwhile, the delay time difference generated by the inverter under different process angles is larger, so that the pre-emphasis requirement in high-speed transmission is difficult to meet.
Disclosure of Invention
In order to solve the above technical problems in the background art, the present invention provides an LVDS output driving circuit with pre-emphasis, which can reduce power supply fluctuation and realize a pre-emphasis function at a higher transmission rate.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
an LVDS output driving circuit with pre-emphasis, which is characterized in that: the LVDS output driving circuit with pre-emphasis comprises a differential signal input end, a signal output end, an LVDS output stage circuit, an LVDS pre-emphasis circuit and a common mode feedback circuit; the differential signal input end is connected to the signal output end through the LVDS output stage circuit and the LVDS pre-emphasis circuit respectively; and the signal output end is respectively connected with the LVDS output stage circuit and the LVDS pre-emphasis circuit in a feedback way through the common mode feedback circuit.
The LVDS pre-emphasis circuit includes a power supply VCC, a transistor PM6, a transistor PM7, a capacitor C1, a transistor PM4, a transistor PM5, a transistor NM3, a transistor NM4, a capacitor C2, a current tube I2, and a current tube I3; the power supply VCC is respectively connected with the transistor PM6 and the transistor PM7; the transistor PM6 is connected to the transistor PM7; the transistor PM6 is connected to the transistor NM3 through the transistor PM4; the transistor PM7 is connected to the transistor NM4 through the transistor PM 5; the transistor PM4 is connected with the transistor PM5 through a capacitor C1; the transistor NM3 is grounded through a current tube I2; the transistor NM4 is grounded through a current tube I3; the transistor NM3 is connected with the transistor NM4 through a capacitor C2; the common mode feedback circuit is respectively connected with a transistor PM6 and a transistor PM7; the differential signal input ends are respectively connected with a transistor PM4, a transistor PM5, a transistor NM3 and a transistor NM4; the signal output terminals are respectively connected to the transistor PM4, the transistor PM5, the transistor NM3 and the transistor NM4.
The LVDS pre-emphasis circuit further comprises a capacitor C3 and a capacitor C4; the power supply VCC is connected to the transistor PM4 through the capacitor C3; the power supply VCC is connected to the transistor PM5 via the capacitor C4.
The LVDS pre-emphasis circuit further comprises a capacitor C5 and a capacitor C6; the transistor NM3 is grounded through a capacitor C5; the transistor NM4 is grounded via a capacitor C6.
The power supply VCC is connected to the source of the transistor PM6 and the source of the transistor PM7, respectively; the gate of the transistor PM6 is connected with the gate of the transistor PM7; the drain of the transistor PM6 is connected with the source of the transistor PM4; the gate of the transistor PM4 is connected to the gate of the transistor NM 3; the drain of the transistor PM4 is connected to the drain of the transistor NM 3; the drain of the transistor PM7 is connected with the source of the transistor PM 5; the gate of the transistor PM5 is connected to the gate of the transistor NM4; the drain of the transistor PM5 is connected to the drain of the transistor NM4; the source of the transistor PM4 is connected with the source of the transistor PM5 through a capacitor C1; the source electrode of the transistor NM3 is grounded through a current tube I2; the source electrode of the transistor NM4 is grounded through a current tube I3; the source electrode of the transistor NM3 is connected with the source electrode of the transistor NM4 through a capacitor C2; the common mode feedback circuit is respectively connected with the grid electrode of the transistor PM6 and the grid electrode of the transistor PM7; the differential signal input end is respectively connected with the grid electrode of the transistor PM4, the grid electrode of the transistor PM5, the grid electrode of the transistor NM3 and the grid electrode of the transistor NM4; the signal output end is respectively connected with the drain electrode of the transistor PM4, the drain electrode of the transistor PM5, the drain electrode of the transistor NM3 and the drain electrode of the transistor NM4; the power supply VCC is connected to the source electrode of the transistor PM4 through a capacitor C3; the power supply VCC is connected to the source electrode of the transistor PM5 through a capacitor C4; the source electrode of the transistor NM3 is grounded through a capacitor C5; the source of the transistor NM4 is grounded through a capacitor C6.
The differential signal input terminal includes a differential signal forward input terminal Vip and a differential signal reverse input terminal Vin; the signal output end comprises a forward signal output end Vop and a reverse signal output end Von; the differential signal positive input end Vip is respectively connected to the grid electrode of the transistor PM4 and the grid electrode of the transistor NM 3; the differential signal reverse input end Vin is respectively connected to the grid electrode of the transistor PM5 and the grid electrode of the transistor NM4; the positive signal output end Vop is respectively connected with the drain electrode of the transistor PM4 and the drain electrode of the transistor NM 3; the reverse signal output terminal Von is connected to the drain of the transistor PM5 and the drain of the transistor NM4, respectively.
The LVDS output stage circuit includes a power source VCC, a transistor PM3, a transistor PM1, a transistor PM2, a transistor NM1, a transistor NM2, and a current tube I1; the power supply VCC is respectively connected to the transistor PM1 and the transistor PM2 through the transistor PM3; the transistor PM1 is grounded through a transistor NM1 and a current tube I1; the transistor PM2 is grounded through a transistor NM2 and a current tube I1; the common mode feedback circuit is connected with a transistor PM3; the differential signal positive input end Vip is respectively connected to the transistor PM1 and the transistor NM1; the differential signal reverse input end Vin is respectively connected to the transistor PM2 and the transistor NM2; the forward signal output end Vop is respectively connected to the transistor PM2 and the transistor NM2; the reverse signal output terminal Von is connected to the transistor PM1 and the transistor NM1, respectively.
The power supply VCC is connected to the source electrode of the transistor PM3; the common mode feedback circuit is connected to the grid electrode of the transistor PM3; the drain electrode of the transistor PM3 is connected to the source electrode of the transistor PM1 and the source electrode of the transistor PM2 respectively; the gate of the transistor PM1 is connected to the gate of the transistor NM1; the drain of the transistor PM1 is connected with the drain of the transistor NM1; the source electrode of the transistor NM1 is grounded through a current tube I1; the gate of the transistor PM2 is connected to the gate of the transistor NM2; the drain of the transistor PM2 is connected to the drain of the transistor NM2; the source electrode of the transistor NM2 is grounded through a current tube I1; the differential signal positive input end Vip is respectively connected to the grid electrode of the transistor PM1 and the grid electrode of the transistor NM1; the differential signal reverse input end Vin is respectively connected to the grid electrode of the transistor PM2 and the grid electrode of the transistor NM2; the positive signal output end Vop is respectively connected to the drain electrode of the transistor PM2 and the drain electrode of the transistor NM2; the reverse signal output terminal Von is connected to the drain of the transistor PM1 and the drain of the transistor NM1, respectively.
The common mode feedback circuit comprises a resistor R1, a resistor R2 and a reference level V REF An input terminal and a comparator; the forward signal output end Vop is connected to the forward input end of the comparator through a resistor R1; the reverse signal output end Von is connected to the positive input end of the comparator through a resistor R2; the reference level V REF The input end is connected with the negative input end of the comparator; the output end of the comparator is respectively connected with the source electrode of the transistor PM3, the grid electrode of the transistor PM6 and the grid electrode of the transistor PM 7.
The invention has the advantages that:
the invention provides an LVDS output driving circuit with pre-emphasis, which comprises a differential signal input end, a signal output end, an LVDS output stage circuit, an LVDS pre-emphasis circuit and a common mode feedback circuit, wherein the differential signal input end is connected with the signal output end; the differential signal input end is connected to the signal output end through the LVDS output stage circuit and the LVDS pre-emphasis circuit respectively; the signal output end is respectively connected to the LVDS output stage circuit and the LVDS pre-emphasis circuit in a feedback mode through the common mode feedback circuit. The pre-emphasis circuit in the invention can utilize the capacitance characteristic to respectively disconnect and connect the pre-emphasis tail current after the data conversion is completed and at the moment of the data conversion, and provide large current at the moment of the data conversion so as to complete the pre-emphasis function. Compared with the pre-emphasis circuit structure realized by the traditional inverter chain, the power supply fluctuation is reduced, and the pre-emphasis function can be realized at a higher transmission rate.
Drawings
FIG. 1 is a schematic diagram of the overall structure of an LVDS output driver circuit with pre-emphasis provided by the present invention;
fig. 2 is a circuit configuration diagram of an LVDS output driving circuit employed in the present invention;
fig. 3 is a circuit configuration diagram of an LVDS pre-emphasis circuit employed in the present invention.
Detailed Description
Referring to fig. 1, the invention provides an LVDS output driving circuit with pre-emphasis, which comprises a differential signal input end, a signal output end, an LVDS output stage circuit, an LVDS pre-emphasis circuit and a common mode feedback circuit; the differential signal input end is connected to the signal output end through the LVDS output stage circuit and the LVDS pre-emphasis circuit respectively; the signal output end is respectively connected to the LVDS output stage circuit and the LVDS pre-emphasis circuit in a feedback mode through the common mode feedback circuit. The LVDS output stage circuit is used for completing an LVDS output function, the LVDS pre-emphasis circuit is used for completing the LVDS pre-emphasis function by utilizing the capacitance characteristic, and the common mode feedback circuit is used for guaranteeing the output common mode requirement.
Referring to fig. 3, the LVDS pre-emphasis circuit used in the present invention includes a power source VCC, a transistor PM6, a transistor PM7, a capacitor C1, a transistor PM4, a transistor PM5, a transistor NM3, a transistor NM4, a capacitor C2, a current tube I2, and a current tube I3; the power supply VCC is connected to the transistor PM6 and the transistor PM7, respectively; the transistor PM6 is connected to the transistor PM7; the transistor PM6 is connected to the transistor NM3 through the transistor PM4; the transistor PM7 is connected to the transistor NM4 through the transistor PM 5; transistor PM4 is connected to transistor PM5 through capacitor C1; the transistor NM3 is grounded through a current tube I2; the transistor NM4 is grounded through a current tube I3; the transistor NM3 is connected to the transistor NM4 through a capacitor C2; the common mode feedback circuit is respectively connected with the transistor PM6 and the transistor PM7; the differential signal input ends are respectively connected with a transistor PM4, a transistor PM5, a transistor NM3 and a transistor NM4; the signal output terminals are respectively connected to the transistor PM4, the transistor PM5, the transistor NM3 and the transistor NM4.
Referring to fig. 3, the LVDS pre-emphasis circuit used in the present invention uses the capacitive characteristic to perform the pre-emphasis function. By utilizing the capacitance characteristic, the data conversion can be completedThe pre-emphasis tail current is respectively disconnected and connected at the moment of the later data conversion. At the moment of data conversion, the switch capacitor is conducted, the pre-emphasis tail current is started, the output amplitude is improved, and the pre-emphasis function is completed; after the data conversion is completed, the signal keeps a DC state, the switch capacitor is turned off, the pre-emphasis tail current is turned off, and the LVDS output amplitude is maintained. The method comprises the following steps: when the input differential signal Vip is changed from low level to high level and the differential signal Vin is changed from high level to low level, the voltage across the capacitor C1 and the capacitor C2 changes to make the capacitor instantly turned on, and the input level changes to make the on-resistance of the transistor PM5 and the transistor NM3 smaller than that of the transistor PM4 and the transistor NM4, and the current flows from V CC After the current through the transistor PM6, the capacitor C1 and the transistor PM7 is added, the current flows through the transistor PM5 and flows to the external load R through the forward signal output terminal Vop L Then the signal returns to the reverse signal output end Von to pass through the transistor NM3, and the signal is respectively overlapped to LVDS output from the current tube I2, the capacitor C2 and the current tube I3 to the ground, so that the rising and falling edges of the output can be quickened; with the data switching, the capacitance is reduced until the data switching is completed, the capacitance is turned off after the steady state is entered, at this time, the differential signal Vip is at a high level, the differential signal Vin is at a low level, and the transistors NM3, NM4, PM4 and PM5 in the circuit are all in a saturation region, and the current will not be superimposed on the LVDS output terminal from Vcc to PM6, PM4, NM3 and through the current tube I1 to ground, or from Vcc to PM7, PM5, NM4 and I2 to ground, respectively. Otherwise, the same is true.
In addition, in order to obtain higher-order pre-emphasis, the LVDS pre-emphasis circuit adopted by the invention further comprises a capacitor C3, a capacitor C4, a capacitor C5 and a capacitor C6; the power supply VCC is connected to the transistor PM4 through the capacitor C3; the power supply VCC is connected to the transistor PM5 through the capacitor C4. The transistor NM3 is grounded through a capacitor C5; the transistor NM4 is grounded through a capacitor C6. The working principle is as follows: when the input differential signal Vip is shifted from low to high, the differential signal Vin is shifted from high to low, since the source voltage of the transistor PM5 is vin+vth (PM 5), as the differential signal Vin level is changed from high to low, the source voltage V2 of the transistor PM5 is also changed from high to low,in order to maintain the original high level of V2, the capacitor C4 instantly draws current from the power supply; meanwhile, as the source voltage of the transistor NM3 is Vip-Vth (NM 3), as the level of the differential signal Vip is changed from low to high, the source voltage V3 of the transistor NM3 is also changed from low to high, and the capacitor C5 can instantaneously release the current to the ground to pull down in order to maintain the original low level of V3; current self V CC The current generated by the capacitor C4 is added with the current flowing through the transistor PM6 and the capacitor C1 and then flows through the transistor PM5, and flows to the external load R through the forward signal output end Vop L Then, the signal returns to the reverse signal output end Von to pass through the transistor NM3, and is respectively overlapped to the LVDS output from the capacitor C5, the current tube I2, the capacitor C2 and the current tube I3 to the ground, so that the rising and falling edges of the output can be further quickened; with the data switching, the opening degree of the capacitor is reduced until the data switching is completed, and after the data switching enters a steady state, the capacitor is disconnected, so that the original working state of the circuit is maintained. Otherwise, the same is true.
Illustratively, the power source VCC is connected to the source of the transistor PM6 and the source of the transistor PM7, respectively; the gate of the transistor PM6 is connected to the gate of the transistor PM7; the drain of the transistor PM6 is connected to the source of the transistor PM4; the gate of the transistor PM4 is connected to the gate of the transistor NM 3; the drain of the transistor PM4 is connected to the drain of the transistor NM 3; the drain of the transistor PM7 is connected to the source of the transistor PM 5; the gate of the transistor PM5 is connected to the gate of the transistor NM4; the drain of the transistor PM5 is connected to the drain of the transistor NM4; the source of the transistor PM4 is connected to the source of the transistor PM5 through a capacitor C1; the source of the transistor NM3 is grounded through a current tube I2; the source of the transistor NM4 is grounded through a current tube I3; the source of the transistor NM3 is connected to the source of the transistor NM4 through a capacitor C2; the common mode feedback circuit is respectively connected with the grid electrode of the transistor PM6 and the grid electrode of the transistor PM7; the differential signal input ends are respectively connected with the grid electrode of the transistor PM4, the grid electrode of the transistor PM5, the grid electrode of the transistor NM3 and the grid electrode of the transistor NM4; the signal output end is respectively connected with the drain electrode of the transistor PM4, the drain electrode of the transistor PM5, the drain electrode of the transistor NM3 and the drain electrode of the transistor NM4; the power supply VCC is connected to the source electrode of the transistor PM4 through a capacitor C3; the power supply VCC is connected to the source electrode of the transistor PM5 through a capacitor C4; the source of the transistor NM3 is grounded through a capacitor C5; the source of the transistor NM4 is grounded through a capacitor C6.
The differential signal input terminal comprises a differential signal forward input terminal Vip and a differential signal reverse input terminal Vin; the signal output end comprises a forward signal output end Vop and a reverse signal output end Von; the differential signal positive input end Vip is respectively connected to the grid electrode of the transistor PM4 and the grid electrode of the transistor NM 3; the differential signal inverting input Vin is respectively connected to the gate of the transistor PM5 and the gate of the transistor NM4; the forward signal output terminal Vop is respectively connected to the drain electrode of the transistor PM4 and the drain electrode of the transistor NM 3; the inverted signal output terminal Von is connected to the drain of the transistor PM5 and the drain of the transistor NM4, respectively.
Referring to fig. 2, the LVDS output stage circuit used in the present invention is a classical LVDS driving circuit, which includes a power source VCC, a transistor PM3, a transistor PM1, a transistor PM2, a transistor NM1, a transistor NM2, and a current tube I1; the power supply VCC is respectively connected to the transistor PM1 and the transistor PM2 through the transistor PM3; the transistor PM1 is grounded through the transistor NM1 and the current tube I1; transistor PM2 is grounded through transistor NM2 and current tube I1; the common mode feedback circuit is connected with the transistor PM3; the differential signal positive input end Vip is respectively connected to the transistor PM1 and the transistor NM1; the differential signal inverting input terminal Vin is respectively connected to the transistor PM2 and the transistor NM2; the forward signal output terminal Vop is respectively connected to the transistor PM2 and the transistor NM2; the inverted signal output terminal Von is connected to the transistor PM1 and the transistor NM1, respectively.
Illustratively, the power supply VCC is coupled to the source of transistor PM3; the common mode feedback circuit is connected to the grid electrode of the transistor PM3; the drain electrode of the transistor PM3 is connected to the source electrode of the transistor PM1 and the source electrode of the transistor PM2 respectively; the gate of the transistor PM1 is connected to the gate of the transistor NM1; the drain of the transistor PM1 is connected to the drain of the transistor NM1; the source of the transistor NM1 is grounded through a current tube I1; the gate of the transistor PM2 is connected to the gate of the transistor NM2; the drain of the transistor PM2 is connected to the drain of the transistor NM2; the source of the transistor NM2 is grounded through a current tube I1; the differential signal positive input end Vip is respectively connected to the grid electrode of the transistor PM1 and the grid electrode of the transistor NM1; differential signal inverting input VinThe gate of the transistor PM2 and the gate of the transistor NM2 are connected respectively; the forward signal output terminal Vop is respectively connected to the drain electrode of the transistor PM2 and the drain electrode of the transistor NM2; the inverted signal output terminal Von is connected to the drain of the transistor PM1 and the drain of the transistor NM1, respectively. Referring to FIG. 2, when the input differential signal Vip is high and the differential signal Vin is low, the transistor NM1 and the transistor PM2 are turned on, and the current flows from V CC Through the transistor PM3 and the transistor PM2, the output voltage flows to the external load R through the forward signal output terminal Vop L Then, the output of the forward signal output terminal Vop is high and the output of the reverse signal output terminal Von is low after the reverse signal output terminal Von returns to the reverse signal output terminal Von through the transistor NM1 and the current pipes I1 to GND. Otherwise, the same is true. The output amplitude is ensured by adjusting the size of the current tube I1, and the LVDS protocol is satisfied.
Referring to FIG. 1, the common mode feedback circuit used in the present invention comprises a resistor R1, a resistor R2, and a reference level V REF An input terminal and a comparator; the forward signal output end Vop is connected to the forward input end of the comparator through a resistor R1; the reverse signal output end Von is connected to the positive input end of the comparator through a resistor R2; reference level V REF The input end is connected with the negative input end of the comparator; the output of the comparator is connected to the source of the transistor PM3, the gate of the transistor PM6 and the gate of the transistor PM7, respectively. V generated by taking common mode of output common mode signal through resistor R1 and resistor R2 and band gap reference REF And comparing the voltages to generate a voltage signal to adjust the size of the PMOS current source, so that the common mode signal is regulated and output, and the common mode signal can be stabilized at about 1.2V to meet the LVDS protocol.

Claims (9)

1. An LVDS output driving circuit with pre-emphasis, which is characterized in that: the LVDS output driving circuit with pre-emphasis comprises a differential signal input end, a signal output end, an LVDS output stage circuit, an LVDS pre-emphasis circuit and a common mode feedback circuit; the differential signal input end is connected to the signal output end through the LVDS output stage circuit and the LVDS pre-emphasis circuit respectively; and the signal output end is respectively connected with the LVDS output stage circuit and the LVDS pre-emphasis circuit in a feedback way through the common mode feedback circuit.
2. The LVDS output driver circuit with pre-emphasis of claim 1, wherein: the LVDS pre-emphasis circuit comprises a power supply VCC, a transistor PM6, a transistor PM7, a capacitor C1, a transistor PM4, a transistor PM5, a transistor NM3, a transistor NM4, a capacitor C2, a current tube I2 and a current tube I3; the power supply VCC is respectively connected with the transistor PM6 and the transistor PM7; the transistor PM6 is connected to the transistor PM7; the transistor PM6 is connected to the transistor NM3 through the transistor PM4; the transistor PM7 is connected to the transistor NM4 through the transistor PM 5; the transistor PM4 is connected with the transistor PM5 through a capacitor C1; the transistor NM3 is grounded through a current tube I2; the transistor NM4 is grounded through a current tube I3; the transistor NM3 is connected with the transistor NM4 through a capacitor C2; the common mode feedback circuit is respectively connected with a transistor PM6 and a transistor PM7; the differential signal input ends are respectively connected with a transistor PM4, a transistor PM5, a transistor NM3 and a transistor NM4; the signal output terminals are respectively connected to the transistor PM4, the transistor PM5, the transistor NM3 and the transistor NM4.
3. The LVDS output driver circuit with pre-emphasis of claim 2, wherein: the LVDS pre-emphasis circuit further comprises a capacitor C3 and a capacitor C4; the power supply VCC is connected to the transistor PM4 through the capacitor C3; the power supply VCC is connected to the transistor PM5 via the capacitor C4.
4. The pre-emphasized LVDS output driver circuit of claim 3, wherein: the LVDS pre-emphasis circuit further comprises a capacitor C5 and a capacitor C6; the transistor NM3 is grounded through a capacitor C5; the transistor NM4 is grounded via a capacitor C6.
5. The pre-emphasized LVDS output driver circuit of claim 4, wherein: the power supply VCC is respectively connected with the source electrode of the transistor PM6 and the source electrode of the transistor PM7; the gate of the transistor PM6 is connected with the gate of the transistor PM7; the drain of the transistor PM6 is connected with the source of the transistor PM4; the gate of the transistor PM4 is connected to the gate of the transistor NM 3; the drain of the transistor PM4 is connected to the drain of the transistor NM 3; the drain of the transistor PM7 is connected with the source of the transistor PM 5; the gate of the transistor PM5 is connected to the gate of the transistor NM4; the drain of the transistor PM5 is connected to the drain of the transistor NM4; the source of the transistor PM4 is connected with the source of the transistor PM5 through a capacitor C1; the source electrode of the transistor NM3 is grounded through a current tube I2; the source electrode of the transistor NM4 is grounded through a current tube I3; the source electrode of the transistor NM3 is connected with the source electrode of the transistor NM4 through a capacitor C2; the common mode feedback circuit is respectively connected with the grid electrode of the transistor PM6 and the grid electrode of the transistor PM7; the differential signal input end is respectively connected with the grid electrode of the transistor PM4, the grid electrode of the transistor PM5, the grid electrode of the transistor NM3 and the grid electrode of the transistor NM4; the signal output end is respectively connected with the drain electrode of the transistor PM4, the drain electrode of the transistor PM5, the drain electrode of the transistor NM3 and the drain electrode of the transistor NM4; the power supply VCC is connected to the source electrode of the transistor PM4 through a capacitor C3; the power supply VCC is connected to the source electrode of the transistor PM5 through a capacitor C4; the source electrode of the transistor NM3 is grounded through a capacitor C5; the source of the transistor NM4 is grounded through a capacitor C6.
6. The pre-emphasized LVDS output driver circuit of claim 5, wherein: the differential signal input end comprises a differential signal forward input end Vip and a differential signal reverse input end Vin; the signal output end comprises a forward signal output end Vop and a reverse signal output end Von; the differential signal positive input end Vip is respectively connected to the grid electrode of the transistor PM4 and the grid electrode of the transistor NM 3; the differential signal reverse input end Vin is respectively connected to the grid electrode of the transistor PM5 and the grid electrode of the transistor NM4; the positive signal output end Vop is respectively connected with the drain electrode of the transistor PM4 and the drain electrode of the transistor NM 3; the reverse signal output terminal Von is connected to the drain of the transistor PM5 and the drain of the transistor NM4, respectively.
7. The pre-emphasized LVDS output driver circuit of claim 6, wherein: the LVDS output stage circuit comprises a power supply VCC, a transistor PM3, a transistor PM1, a transistor PM2, a transistor NM1, a transistor NM2 and a current tube I1; the power supply VCC is respectively connected to the transistor PM1 and the transistor PM2 through the transistor PM3; the transistor PM1 is grounded through a transistor NM1 and a current tube I1; the transistor PM2 is grounded through a transistor NM2 and a current tube I1; the common mode feedback circuit is connected with a transistor PM3; the differential signal positive input end Vip is respectively connected to the transistor PM1 and the transistor NM1; the differential signal reverse input end Vin is respectively connected to the transistor PM2 and the transistor NM2; the forward signal output end Vop is respectively connected to the transistor PM2 and the transistor NM2; the reverse signal output terminal Von is connected to the transistor PM1 and the transistor NM1, respectively.
8. The pre-emphasized LVDS output driver circuit of claim 7, wherein: the power supply VCC is connected to the source electrode of the transistor PM3; the common mode feedback circuit is connected to the grid electrode of the transistor PM3; the drain electrode of the transistor PM3 is connected to the source electrode of the transistor PM1 and the source electrode of the transistor PM2 respectively; the gate of the transistor PM1 is connected to the gate of the transistor NM1; the drain of the transistor PM1 is connected with the drain of the transistor NM1; the source electrode of the transistor NM1 is grounded through a current tube I1; the gate of the transistor PM2 is connected to the gate of the transistor NM2; the drain of the transistor PM2 is connected to the drain of the transistor NM2; the source electrode of the transistor NM2 is grounded through a current tube I1; the differential signal positive input end Vip is respectively connected to the grid electrode of the transistor PM1 and the grid electrode of the transistor NM1; the differential signal reverse input end Vin is respectively connected to the grid electrode of the transistor PM2 and the grid electrode of the transistor NM2; the positive signal output end Vop is respectively connected to the drain electrode of the transistor PM2 and the drain electrode of the transistor NM2; the reverse signal output terminal Von is connected to the drain of the transistor PM1 and the drain of the transistor NM1, respectively.
9. The LVDS output driver circuit with pre-emphasis of claim 8, wherein: the common mode feedback circuit comprises a resistor R1, a resistor R2 and a reference level V REF Input terminal and comparisonA device; the forward signal output end Vop is connected to the forward input end of the comparator through a resistor R1; the reverse signal output end Von is connected to the positive input end of the comparator through a resistor R2; the reference level V REF The input end is connected with the negative input end of the comparator; the output end of the comparator is respectively connected with the source electrode of the transistor PM3, the grid electrode of the transistor PM6 and the grid electrode of the transistor PM 7.
CN202311743052.3A 2023-12-18 2023-12-18 LVDS output driving circuit with pre-emphasis Pending CN117879590A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118100990A (en) * 2024-04-26 2024-05-28 成都电科星拓科技有限公司 Method for driving forward branch output stage in forward de-emphasis circuit in receiver
CN118101392A (en) * 2024-04-26 2024-05-28 成都电科星拓科技有限公司 Method for reducing backward crosstalk in communication and backward synthesis circuit
CN118100988A (en) * 2024-04-25 2024-05-28 成都电科星拓科技有限公司 Method for reducing forward crosstalk in communication and forward synthesis circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118100988A (en) * 2024-04-25 2024-05-28 成都电科星拓科技有限公司 Method for reducing forward crosstalk in communication and forward synthesis circuit
CN118100988B (en) * 2024-04-25 2024-07-02 成都电科星拓科技有限公司 Method for reducing forward crosstalk in communication and forward synthesis circuit
CN118100990A (en) * 2024-04-26 2024-05-28 成都电科星拓科技有限公司 Method for driving forward branch output stage in forward de-emphasis circuit in receiver
CN118101392A (en) * 2024-04-26 2024-05-28 成都电科星拓科技有限公司 Method for reducing backward crosstalk in communication and backward synthesis circuit
CN118101392B (en) * 2024-04-26 2024-07-02 成都电科星拓科技有限公司 Method for reducing backward crosstalk in communication and backward synthesis circuit

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