CN110932714B - Transmission interface circuit based on SUBLVDS - Google Patents
Transmission interface circuit based on SUBLVDS Download PDFInfo
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- CN110932714B CN110932714B CN201911306254.5A CN201911306254A CN110932714B CN 110932714 B CN110932714 B CN 110932714B CN 201911306254 A CN201911306254 A CN 201911306254A CN 110932714 B CN110932714 B CN 110932714B
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Abstract
The invention provides a high-speed transmission interface circuit based on SUBLVDS technology, and belongs to the technical field of integrated circuits. The circuit mainly comprises three parts: the device comprises a single-ended rotating differential module, an input buffer module and a common mode feedback output driving module. The method is used for converting a single-ended signal inside the chip into a pair of low-voltage differential signals meeting the SUBLVDS protocol standard and outputting the signals to the outside of the chip at high speed. The invention can work under 1.2V low voltage, the output swing is 150mV, the transmission speed is fast, and the invention can be used for high frequency signal transmission. Meanwhile, the driver circuit with the slew rate compensation structure is adopted, and an adjustable internal termination resistor is added, so that the impedance matching performance of the circuit is greatly improved, overshoot and ringing phenomena of a transmission signal are greatly reduced, and the transmission quality is improved. The circuit forms a common mode feedback loop inside, so that the output common mode is stable, and the output signal can be stably received.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a transmission interface circuit based on SUBLVDS.
Background
Today, where information technology is rapidly developed, high-speed transmission of signals becomes an important part of the information world. Since it is difficult for high-speed signals to be directly transmitted from the inside of the chip to the outside of the chip, there is a large difference in data transmission speeds inside and outside the chip, and this difference becomes an important factor affecting the system performance. The use of a low voltage, low swing high speed data transmission interface is an effective solution to this problem.
The LVDS interface is an interface technology for realizing high-speed data transmission between point-to-point by utilizing low-voltage low-swing differential signals, and has the advantages of high speed, low power consumption, low cost and the like. The sullvds interface is a new technology developed from the LVDS interface, and its operating voltage is further reduced relative to LVDS, so that it can operate at a supply voltage of 1.2V. The common mode level value is reduced to 0.9V, and the differential swing is reduced to 150mV, so that the power consumption is further reduced compared with LVDS.
The conventional sulflvds output interface is shown in fig. 1, and the disadvantage of this structure is as follows: firstly, due to the existence of an external terminal resistor, serious signal reflection can be caused when a signal passes through a transmission line with abrupt resistance, and the impedance matching performance is poor; second, the output common mode of the signal cannot be maintained, and the output cannot be stably received; third, due to parasitic capacitance and inductance on the transmission line, overshoot and oscillation damping of the response signal tend to occur, affecting the transmission quality.
Disclosure of Invention
In order to overcome the above disadvantages of the prior art, such as poor impedance matching, unstable output common mode, overshoot of output signal, and oscillation damping, the present invention provides a transmission interface circuit based on sulfds.
The invention is realized by the following technical scheme:
the transmission interface circuit based on SUBLVDS is used for transmitting high-speed signals inside a chip to the outside of the chip and comprises a single-ended-to-differential module, an input buffer module and a common-mode feedback output driving module; the single-ended to differential module is used for converting an input single-ended signal into a differential signal and outputting the differential signal to the input buffer module; the input buffer module improves the signal driving capability of the received differential signals through a two-stage buffer and then sends the differential signals to the common mode feedback output driving module; the common mode feedback output driving module changes the received signals into differential sublvds signals with the swing of 150mV through an internal double current source driver structure.
Further, the single-ended-to-differential module consists of a positive phase signal output part and an inverse phase signal output part, and the input ends of the two parts are connected together and used for receiving an input single-ended signal; the inverting signal output part is formed by cascading three inverters, and an input single-ended signal is subjected to three times of inversion and then an inverting signal is output; the positive phase signal output part is formed by sequentially connecting two inverters and a TG transmission gate, the input end of the TG transmission gate is connected with the output end of the two-stage inverters, and an input single-ended signal firstly passes through the two cascaded inverters and outputs positive phase signals after two times of inversion. Since the inverted signal passes through one inverter more than the positive phase signal, a transmission delay is caused, so the positive phase signal needs to pass through a TG transmission gate to increase the transmission delay, and the delayed positive phase signal and the inverted signal can be delayed to be consistent by adjusting the transmission gate parameters.
Further, the input buffer module is divided into two parts which are respectively used for providing driving force for the normal phase output signal and the reverse phase output signal, and the two parts have the same circuit structure and are formed by cascading four-stage inverters; the sizes of the NMOS tube and the PMOS tube of the inverter are amplified four times step by step from the first stage to the fourth stage, namely the size of the inverter of the fourth stage is 64 times that of the first stage.
Further, the common mode feedback output driving module is a common mode feedback loop formed by a core driving module, an internal terminal resistance module, a common mode adjusting module and a reference common mode generating module; the core driving module is provided with four input ends, namely two signal input ends and two current source input ends, wherein the two signal input ends of the core driving module are connected with an input differential signal, and the two current source input ends are respectively connected with the two output ends of the common mode adjusting module; the two output ends of the core driving module are connected to the two input ends of the internal terminal resistor module, the internal terminal resistor module has three output ends, the two signal output ends are differential output ends of the whole interface circuit, and the other is an inductive common-mode voltage output end; the input end of the reference common mode generating module is connected with externally provided band gap reference voltage with the voltage value of 1.2V, and the output end of the reference common mode generating module is common mode reference voltage with the voltage value of 0.9V; the two input ends of the common mode adjusting module are respectively connected with the sensing common mode voltage output end of the internal termination resistor module and the output end of the reference common mode generating module.
Further, as shown in fig. 7, the core driving module adopts a dual current source driving structure with slew rate compensation, and adopts a method of combining output transconductance and an RC network to pre-emphasis an output signal, so as to compensate the oscillation ringing phenomenon of a response signal. The core driving module comprises two pairs of mirror image current sources, two pairs of inverters, four driver switching tubes and an RC delay network; the dual current source driving structure is two pairs of mirror current sources, wherein the two pairs of mirror current sources are M1 and M2, M3 and M4 respectively and are used for pairs of mirror current sourcesThe driver supplies current; the drain end of M2 is connected with the source ends of M7 and M9; the drain end of M4 is connected with the source ends of M8 and M10; the two pairs of inverters are an inverter formed by M11 and M12 and an inverter formed by M5 and M6 respectively; the gate ends of M5 and M6, namely the input end of the inverter, are connected with a normal phase input signal INP, and the output end is connected with one end of a resistor RD 1; the gate ends of M11 and M12 are the input end of the other inverter, are connected with the inverted input signal INN, and the output end is connected with one end of the resistor RD 2; the four driver switching tubes are M7, M8, M9 and M10; m7 and M9 are PMOS tubes, and the source ends of the two are connected; m8 and M10 are NMOS tubes, and the source ends of the NMOS tubes are connected; m7 is connected with the drain terminal of M8, and the junction of the drain terminal and the drain terminal is used as an inverted output signal OUTN; m9 is connected with the drain terminal of M10, and the junction of the drain terminal and the drain terminal is used as a positive phase output signal OUTP. M7 is connected with the gate end of M8 and is connected with one end of the resistor RD 1; m9 is connected with the gate end of M10 and is connected with one end of a resistor RD 2; the RC delay network is composed of two resistors RD and a capacitor C D The method comprises the steps of carrying out a first treatment on the surface of the One end of the resistor RD1 is connected to the drain ends of the M5 and the M6, namely the output end of the inverter, and the other end of the resistor RD is connected to the gate ends of the M7 and the M8; one end of the resistor RD2 is connected to the drain ends of the M11 and the M12, namely the output end of the inverter, and the other end of the resistor RD is connected to the gate ends of the M9 and the M10; capacitor C D One end is connected to the gate terminals of M7 and M8, and the other end is connected to the gate terminals of M9 and M10.
Further, the internal termination resistor module is used for performing impedance matching and sensing output common mode value and consists of a resistor array and a switch MOS tube; the resistor array comprises a matching resistor, a shunt resistor and an induction resistor; m1 and M2 are the switch MOS pipes used for controlling whether to shunt, R0 is the internal matching resistor with the resistance value of 100 omega, and the internal matching resistor is used for impedance matching. The adjustable resistor is manufactured into the adjustable resistor, and the on-off of the branch where the adjustable resistor is located can be changed by adjusting the gate terminal voltages of M1 and M2, so that the internal matching resistor is reduced. The resistors R1, R2, R3, R4 are shunt resistors. R5 and R6 are sense resistors for sensing the value of the output common mode voltage. R1, M1, R2 are connected in series, R3, M2, R4 are connected in series, R5 is connected in series with R6, and the three branches are connected in parallel with R0. The resistances of R5 and R6 are the same, and are all 100kΩ resistances for sensing the output common mode level of the SUBLVDS driver.
Further, the common mode adjusting module adjusts the grid voltages VB1 and VB2 of the two mirror image current sources of the core driving module through the input reference common mode value and the output common mode value sensed by the internal terminal resistor, so as to adjust the magnitude of current and enable the output common mode to tend to a reference value; the module has two input ends, one end is connected with a reference common-mode voltage VREF, the other end is connected with an induced common-mode voltage VCM, when the two voltage values are different, the voltage VB1 and the voltage VB2 can be changed, the change of the current values of two current sources of the core driving module can be controlled through the change of the voltage VB1 and the voltage VB2, and the module is formed by a typical fully-differential five-tube operational amplifier.
Further, the reference common mode generating module is an operational amplifier working in a negative feedback mode, and obtains an output standard voltage VREF through the positive input voltage VBG; three resistors R1, R2 and R3 are connected in series between the output end of the operational amplifier and the ground, the negative input end of the operational amplifier is connected to the intersection point of the resistors R1 and R2 to form a negative feedback mode, the positive input end of the amplifier is connected to the band gap reference voltage VBG, and the output end VREF is connected to the intersection point of the resistors R2 and R3.
Compared with the prior art, the invention has the following advantages:
the transmission interface circuit based on SUBLVDS adopts a driving structure with slew rate compensation, designs a high-speed transmission interface circuit, pre-emphasizes output signals, reduces ringing and overshoot of the output signals, and enhances signal quality; the circuit forms a common mode feedback loop, so that the output common mode is more stable, stable reception is easier to realize, and the data transmission rate can reach 1.28Gbps.
Drawings
FIG. 1 is a schematic diagram of a conventional SUBLVDS output interface;
fig. 2 is a schematic structural diagram of a transmission interface circuit based on a sulvds according to the present invention;
FIG. 3 is a schematic diagram of a single ended differential module of the present invention;
FIG. 4 is a schematic diagram of an input buffer module according to the present invention;
FIG. 5 is a schematic diagram of a common mode feedback output driving module according to the present invention;
FIG. 6 is a schematic circuit diagram of a common mode feedback output driving module according to the present invention;
FIG. 7 is a schematic diagram of a core driver module according to the present invention;
FIG. 8 is a schematic diagram of an internal termination resistor module according to the present invention;
FIG. 9 is a schematic diagram of a resistor matching model between a transmitting end and a receiving end according to the present invention;
FIG. 10 is a schematic diagram of a common mode adjustment module of the present invention;
FIG. 11 is a schematic diagram of a reference common mode generating module according to the present invention;
FIG. 12 is a schematic diagram of a five-tube op-amp structure of the present invention;
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
The transmission interface circuit based on SUBLVDS is used for transmitting high-speed signals inside a chip to the outside of the chip and comprises a single-ended-to-differential module, an input buffer module and a common-mode feedback output driving module; the single-ended to differential module is used for converting an input single-ended signal into a differential signal and outputting the differential signal to the input buffer module; the input buffer module improves the signal driving capability of the received differential signals through a two-stage buffer and then sends the differential signals to the common mode feedback output driving module; the common mode feedback output driving module changes the received signals into differential sublvds signals with the swing of 150mV through an internal double current source driver structure.
The single-ended differential module, the specific embodiment of which is combined with fig. 3. The module consists of a positive phase signal output part and an inverse phase signal output part, wherein the input ends of the two parts are connected together and are used for receiving an input single-ended signal IN. The inverted signal output part is composed of three inverter cascade connection, and the input single-ended signal is inverted for three times and then the inverted signal OUTN is output. The positive phase signal output part is composed of two inverters and a TG transmission gate, wherein the input end of the TG transmission gate is connected with the output end of the two-stage inverters. The input single-ended signal passes through two cascaded inverters, and after two inversions, positive phase signals are output. Since the inverted signal passes through one more inverter than the positive phase signal, a transmission delay is caused. The positive phase signal needs to pass through a TG transmission gate to increase the transmission delay and output the signal OUTP. By adjusting the transmission gate parameters, the delayed positive phase signal OUTP can be made to coincide with the inverted signal OUTN delay.
The input buffer module, the specific embodiment of which is combined with fig. 4. The module is divided into two parts which are respectively used for improving the driving capability of a positive phase output signal and a negative phase output signal. The two parts of the circuit have the same structure and are formed by cascade connection of 4-stage inverters. The inverter size is scaled up four times from the first stage to the fourth stage, i.e., the fourth stage inverter size is 64 times the first stage. The positive phase signal input INN is cascaded through 4-stage inverters to output the signal OUTN. The inverted signal input INP is cascaded through 4-stage inverters to output the signal OUTP.
The common mode feedback loop realizes output common mode stabilization, and the specific embodiment is combined with fig. 6. M9 is connected with a reference common mode level VREF, and M10 is connected with an output common mode level VCM sensed by the internal termination resistance module. When the two are equal, the current flowing through M9 and M10 are the same, and a dual current source is provided for the core driving module through bias voltages VB1 and VB 2. When the inductive common mode is lower than the reference value, the current flowing through M9 will be greater than M10, so that the current flowing through M2 by the core drive module is greater than the current flowing through M4. Due to early effect, the drain-source voltage of M2 will decrease and the drain-source voltage of M4 will increase, thereby realizing an improvement of the output common mode value. Similarly, when the induced common mode is higher than the reference value, the current flowing through M9 is smaller than the current flowing through M10, and at this time, the drain-source voltage of M2 increases and the drain-source voltage of M4 decreases due to early effect, thereby realizing a reduction in the output common mode value. Thus, the output common mode is regulated to be stabilized around the reference common mode through the common mode feedback loop.
The core driving module, as shown in FIG. 7, employs a driving circuit with slew rate compensationThe dual current source driving structure adopts a method of combining output transconductance and RC network to pre-emphasis the output signal and compensates the oscillation ringing phenomenon of the response signal. The core driving module comprises two pairs of mirror image current sources, two pairs of inverters, four driver switching tubes and an RC delay network; the dual current source driving structure is two pairs of mirror current sources, wherein the two pairs of mirror current sources are M1 and M2, and M3 and M4 respectively and are used for providing current for a driver; the drain end of M2 is connected with the source ends of M7 and M9; the drain end of M4 is connected with the source ends of M8 and M10; the two pairs of inverters are an inverter formed by M11 and M12 and an inverter formed by M5 and M6 respectively; the gate ends of M5 and M6, namely the input end of the inverter, are connected with a normal phase input signal INP, and the output end is connected with one end of a resistor RD 1; the gate ends of M11 and M12 are the input end of the other inverter, are connected with the inverted input signal INN, and the output end is connected with one end of the resistor RD 2; the four driver switching tubes are M7, M8, M9 and M10; m7 and M9 are PMOS tubes, and the source ends of the two are connected; m8 and M10 are NMOS tubes, and the source ends of the NMOS tubes are connected; m7 is connected with the drain terminal of M8, and the junction of the drain terminal and the drain terminal is used as an inverted output signal OUTN; m9 is connected with the drain terminal of M10, and the junction of the drain terminal and the drain terminal is used as a positive phase output signal OUTP. M7 is connected with the gate end of M8 and is connected with one end of the resistor RD 1; m9 is connected with the gate end of M10 and is connected with one end of a resistor RD 2; the RC delay network is composed of two resistors RD and a capacitor C D The method comprises the steps of carrying out a first treatment on the surface of the One end of the resistor RD1 is connected to the drain ends of the M5 and the M6, namely the output end of the inverter, and the other end of the resistor RD is connected to the gate ends of the M7 and the M8; one end of the resistor RD2 is connected to the drain ends of the M11 and the M12, namely the output end of the inverter, and the other end of the resistor RD is connected to the gate ends of the M9 and the M10; capacitor C D One end is connected to the gate ends of M7 and M8, and the other end is connected to the gate ends of M9 and M10; when INP is high, INN is low, M7 and M10 are on, M8 and M9 are off, and current flows from OUTN to OUTP through the external termination resistor, creating a negative voltage drop; when INP is low-INN is high, M8 and M10 are open, and current flows from OUTP to OUTN, creating a forward voltage drop.
The slew rate compensation pre-emphasis structure is implemented as follows. As shown in FIG. 7, the input signal INP is connected to M11 and M12, the input signal INN is connected to the gate terminals of M13 and M14. M11 and M12 form an inverter, and M13 and M14 form an inverter. Resistor RD1 has one end connected to the drain terminals of M11 and M12, i.e., the output terminals of the inverters, and the other end connected to the gate terminals of M5 and M6. Resistor RD2 has one end connected to the drain terminals of M13 and M14, i.e., the output terminals of the inverters, and the other end connected to the gate terminals of M7 and M8. Capacitor C D One end is connected to the gate terminals of M5 and M6, and the other end is connected to the gate terminals of M7 and M8. The method of combining output transconductance and RC network is adopted to pre-emphasis the output signal and compensate the oscillation ringing phenomenon of the response signal. With the RC delay network, a portion of the output current is delayed from passing to the load, thereby suppressing the output overshoot.
The internal termination resistor module, the specific embodiment of which is shown in fig. 8. For impedance matching and sensing output common mode values. Since the sultvds completes the current loop by using a termination resistor with a resistance value of 100 Ω at the receiving end, a matching resistor of 100 Ω is also connected in parallel between the differential output end and the transmission line. R0 is an internal matching resistor with a resistance value of 100 Ω for impedance matching. The adjustable resistor is manufactured into the adjustable resistor, and the on-off of the branch where the adjustable resistor is located can be changed by adjusting the gate terminal voltages of M1 and M2, so that the internal matching resistor is reduced. R1, M1, R2 are connected in series, R3, M2, R4 are connected in series, and the two groups of branches are connected in parallel with R0. By default, the gate voltage of M1, M2 is low. R5 is connected in series with R6 and in parallel with R0. The resistances of R5 and R6 are the same and are 100kΩ resistances for sensing the output common-mode level of the SUBLVDS driver, and the intersection point of R5 and R6 is used as the output sensing common-mode voltage VCM. The impedance of R5, R6 is selected to be so large that the output impedance of the driver is not affected. If the driving capability of the driver is found to be insufficient, the current of the driver can be regulated to be large, and the output swing is increased beyond the regulation of a protocol, and at the moment, the branch circuit can be started to split the current, so that the output swing meets the requirement.
The common mode adjustment module is specifically implemented in connection with fig. 10. The module adjusts the grid voltages of two mirror image current sources of the core driving module through the input reference common mode value and the output common mode value sensed by the internal terminal resistor so as to adjust the current, and the output common mode tends to a reference value. The module has two input ends, namely a pair of PMOS input pair tubes, and the two input ends are respectively connected with a reference common-mode voltage VREF and an induced common-mode voltage VCM. When the two voltage values are the same. The current flowing through these two PMOS's is the same, so that the gate voltages VB1 and VB2 of the two NMOS transistors connected thereto are also the same. When VREF and VCM are different, the voltages VB1 and VB2 are changed, and the change of the current values of the two current sources of the core driving module can be controlled through the change of VB1 and VB 2. The module is composed of a fully differential five-tube operational amplifier, VREF and VCM are used as differential input ends, and VB1 and VB2 are used as differential output ends.
The reference common mode generating module is specifically implemented in connection with fig. 11. Mainly by an operational amplifier operating in a negative feedback mode. The bandgap reference voltage VBG is connected as an input to this block, at the positive input of the amplifier. Three resistors R1, R2 and R3 are connected in series between the output end of the amplifier and the ground. The negative input end of the amplifier is connected to the intersection point of the connection of the resistor R1 and the resistor R2 to form a negative feedback mode. The output VREF is connected at the intersection of resistors R2 and R3. The VBG voltage value is 1.2V, and is used as a bandgap reference voltage which does not vary with temperature and supply voltage. According to the negative feedback operation mode, the voltage at the intersection of the resistors R1 and R2 is the same as VBG. The ratio of R2 to R3 resistance is 4:3, the voltage value of the output VREF is 0.9V according to the voltage division of the resistor, and the voltage value is unchanged with temperature and power supply voltage like VBG.
The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the scope of the technical concept of the present invention, and all the simple modifications belong to the protection scope of the present invention.
In addition, the specific features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various possible combinations are not described further.
Moreover, any combination of the various embodiments of the invention can be made without departing from the spirit of the invention, which should also be considered as disclosed herein.
Claims (1)
1. The transmission interface circuit based on SUBLVDS is used for transmitting high-speed signals inside a chip to the outside of the chip and is characterized by comprising a single-ended-to-differential module, an input buffer module and a common-mode feedback output driving module; the single-ended to differential module is used for converting an input single-ended signal into a differential signal and outputting the differential signal to the input buffer module; the input buffer module improves the signal driving capability of the received differential signals through a two-stage buffer and then sends the differential signals to the common mode feedback output driving module; the common mode feedback output driving module changes the received signals into differential subvds signals to be output through an internal double current source driver structure;
the single-ended-to-differential module consists of a positive phase signal output part and an inverse phase signal output part, and the input ends of the two parts are connected together and used for receiving an input single-ended signal; the inverting signal output part is formed by cascading three inverters, and an input single-ended signal is subjected to three times of inversion and then an inverting signal is output; the positive phase signal output part is formed by sequentially connecting two inverters and a TG transmission gate, the input end of the TG transmission gate is connected with the output end of the two-stage inverters, and an input single-ended signal firstly passes through the two cascaded inverters and outputs positive phase signals after two times of inversion; the transmission delay is caused because the inverted signal passes through one inverter more than the positive phase signal, so the positive phase signal needs to pass through a TG transmission gate to increase the transmission delay, and the delayed positive phase signal and the inverted signal are delayed to be consistent by adjusting the parameters of the transmission gate;
the input buffer module is divided into two parts which are respectively used for providing driving force for a normal phase output signal and an inverse phase output signal, and the two parts have the same circuit structure and are formed by cascading four-stage inverters; the sizes of the NMOS tube and the PMOS tube of the inverter are amplified four times step by step from the first stage to the fourth stage, namely the size of the inverter of the fourth stage is 64 times that of the first stage;
the common mode feedback output driving module is a common mode feedback loop consisting of a core driving module, an internal terminal resistance module, a common mode adjusting module and a reference common mode generating module; the core driving module is provided with four input ends, namely two signal input ends and two current source input ends, wherein the two signal input ends of the core driving module are connected with an input differential signal, and the two current source input ends are respectively connected with the two output ends of the common mode adjusting module; the two output ends of the core driving module are connected to the two input ends of the internal terminal resistor module, the internal terminal resistor module has three output ends, the two signal output ends are differential output ends of the whole interface circuit, and the other is an inductive common-mode voltage output end; the input end of the reference common mode generating module is connected with externally provided band gap reference voltage with the voltage value of 1.2V, and the output end of the reference common mode generating module is common mode reference voltage with the voltage value of 0.9V; the two input ends of the common mode adjusting module are respectively connected with the sensing common mode voltage output end of the internal termination resistor module and the output end of the reference common mode generating module;
the core driving module comprises two pairs of mirror image current sources, two pairs of inverters, four driver switching tubes and an RC delay network; the dual current source driving structure is two pairs of mirror current sources, wherein the two pairs of mirror current sources are M1 and M2, and M3 and M4 respectively and are used for providing current for a driver; the drain end of M2 is connected with the source ends of M7 and M9; the drain end of M4 is connected with the source ends of M8 and M10; the two pairs of inverters are an inverter formed by M11 and M12 and an inverter formed by M5 and M6 respectively; the gate ends of M5 and M6, namely the input end of the inverter, are connected with a normal phase input signal INP; the gate ends of M11 and M12 are the input end of the other inverter and are connected with an inverted input signal INN; the four driver switching tubes are M7, M8, M9 and M10; m7 and M9 are PMOS tubes, and the source ends of the two are connected; m8 and M10 are NMOS tubes, and the source ends of the NMOS tubes are connected; m7 is connected with the drain terminal of M8, and the junction of the drain terminal and the drain terminal is used as an inverted output signal OUTN; m9 is connected with the drain terminal of M10, and the junction of the drain terminal and the drain terminal is used as a positive phase output signal OUTP; m7 is connected with the gate end of M8 and is connected with one end of the resistor RD 1; m9 is connected with the gate end of M10 and is connected with one end of a resistor RD 2; the RC delay network is composed of two resistors RD and a capacitor CD; one end of the resistor RD1 is connected to the drain ends of the M5 and the M6, namely the output end of the inverter, and the other end of the resistor RD is connected to the gate ends of the M7 and the M8; one end of the resistor RD2 is connected to the drain ends of the M11 and the M12, namely the output end of the inverter, and the other end of the resistor RD is connected to the gate ends of the M9 and the M10; one end of the capacitor CD is connected to the gate ends of M7 and M8, and the other end is connected to the gate ends of M9 and M10;
the on-off of the branch where the M1 and the M2 are positioned can be changed by adjusting the gate terminal voltages of the M1 and the M2, so that the internal matching resistance is reduced; resistors R1, R2, R3, R4 are shunt resistors; r5 and R6 are sense resistors for sensing the value of the output common mode voltage; r1, M1, R2 are connected in series, R3, M2, R4 are connected in series, R5 is connected in series with R6, and the three branches are connected in parallel with R0; the resistance values of R5 and R6 are the same and are 100kΩ resistances for sensing the output common mode level of the SUBLVDS driver;
the internal termination resistor module is used for performing impedance matching and sensing output common mode value and consists of a resistor array and a switch MOS tube; the resistor array comprises a matching resistor, a shunt resistor and an induction resistor; m1 and M2 are switch MOS tubes for controlling whether to split, R0 is an internal matching resistor with a resistance value of 100 omega, and the internal matching resistor is used for impedance matching; the on-off of the branch where the M1 and the M2 are positioned can be changed by adjusting the gate terminal voltages of the M1 and the M2, so that the internal matching resistance is reduced; resistors R1, R2, R3, R4 are shunt resistors; r5 and R6 are sense resistors for sensing the value of the output common mode voltage; r1, M1, R2 are connected in series, R3, M2, R4 are connected in series, R5 is connected in series with R6, and the three branches are connected in parallel with R0; the resistance values of R5 and R6 are the same and are 100kΩ resistances for sensing the output common mode level of the SUBLVDS driver;
the reference common mode generating module is an operational amplifier working in a negative feedback mode, and obtains an output standard voltage VREF through positive input voltage VBG; three resistors R1, R2 and R3 are connected in series between the output end of the operational amplifier and the ground, the negative input end of the operational amplifier is connected to the intersection point of the resistors R1 and R2 to form a negative feedback mode, the positive input end of the amplifier is connected to the band gap reference voltage VBG, and the output end VREF is connected to the intersection point of the resistors R2 and R3.
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| US11502649B2 (en) * | 2020-04-16 | 2022-11-15 | Mediatek Inc. | High-linearity differential to single ended buffer amplifier |
| CN113541671B (en) * | 2020-04-21 | 2022-06-14 | 复旦大学 | Output drive circuit with self-adaptive adjustable driving capability and control method thereof |
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| CN112751549B (en) * | 2020-12-24 | 2024-07-12 | 西安翔腾微电子科技有限公司 | High-speed LVDS resistance state control circuit and control method |
| CN114564431B (en) * | 2022-02-28 | 2022-12-02 | 北京奕斯伟计算技术股份有限公司 | Hybrid transmit side driver and method of using the same |
| CN116418301B (en) * | 2023-03-28 | 2024-02-13 | 成都电科星拓科技有限公司 | Method and device for automatically matching output impedance |
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