CN117810249A - P-type gate HEMT device and preparation method thereof - Google Patents
P-type gate HEMT device and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims description 7
- 230000004888 barrier function Effects 0.000 claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims description 7
- 230000006911 nucleation Effects 0.000 claims description 5
- 238000010899 nucleation Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 6
- 238000002161 passivation Methods 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 abstract description 3
- 229910002601 GaN Inorganic materials 0.000 description 91
- 238000000034 method Methods 0.000 description 19
- 239000000463 material Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 230000005533 two-dimensional electron gas Effects 0.000 description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 208000033999 Device damage Diseases 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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Abstract
The P-type gate HEMT device comprises a substrate layer, a buffer layer, a channel layer and a barrier layer which are sequentially stacked from bottom to top; and a source structure, a gate structure, and a drain structure sequentially disposed on the barrier layer at intervals from each other in the first direction. The grid structure comprises a P-GaN structure layer and a grid metal layer, the P-GaN structure layer is arranged on the barrier layer, and the grid metal layer is arranged on the P-GaN structure layer; the P-GaN structure layer includes a plurality of P-GaN substructure sequentially disposed on the barrier layer at intervals along a second direction, wherein the first direction and the second direction are perpendicular to each other. The P-GaN substructure extending in the first direction can play a role of a field plate, the electric field between the source electrode structure and the drain electrode structure is uniform, the withstand voltage of the device is improved, and no additional capacitor is introduced. In addition, the P-GaN structure layer can be used as a passivation layer, which is beneficial to improving the current collapse resistance.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a P-type gate HEMT device and a preparation method thereof.
Background
Currently, high electron mobility transistors (High electron mobility transistor; HEMTs), also known as modulation doped field effect transistors, are one type of field effect transistor. Currently, HEMT devices using gallium nitride (GaN) as a core material are becoming mainstream HEMT devices, and compared with Si and SiC power devices, gaN HEMT power devices using AlGaN/GaN heterojunction can obtain lower specific on-resistance under the same breakdown voltage condition.
The main of the current commercial HEMT device is an enhanced (E-Mode) HEMT device with a grid made of P-GaN material, and the current collapse phenomenon of the current E-Mode HEMT device easily occurs in the switching process.
Disclosure of Invention
The invention aims to provide a P-type gate HEMT device and a preparation method thereof, and aims to solve the problem of current collapse of a traditional E-Mode HEMT device in a switching process.
A first aspect of an embodiment of the present application provides a P-type gate HEMT device, including: the substrate layer, the buffer layer, the channel layer and the barrier layer are sequentially stacked from bottom to top; and a source structure, a gate structure, and a drain structure sequentially disposed on the barrier layer at intervals from each other in a first direction; the grid structure comprises a P-GaN structure layer and a grid metal layer, the P-GaN structure layer is arranged on the barrier layer, and the grid metal layer is arranged on the P-GaN structure layer; the P-GaN structure layer comprises a plurality of P-GaN substructures which are sequentially arranged on the barrier layer at intervals along a second direction, wherein the first direction is perpendicular to the second direction, each P-GaN substructures extends along the first direction, and the length of each P-GaN substructures in the first direction is larger than the width of the grid metal layer in the first direction.
In one embodiment, the gate metal layer extends along the second direction and contacts each of the P-GaN substructure.
In one embodiment, two ends of each P-GaN substructure are aligned with each other.
In one embodiment, a distance between an end of the P-GaN substructure near the source structure and the source structure is equal to a distance between the gate structure and the source structure.
In one embodiment, the gate structure further includes an insulating layer disposed between the P-GaN structure layer and the gate metal layer.
In one embodiment, the distance between two adjacent P-GaN substructures ranges from 0.25 micrometers to 1 micrometer.
In one embodiment, a distance between the gate metal layer and the source structure is smaller than a distance between the gate metal layer and the drain structure.
In one embodiment, the P-type gate HEMT device further includes an oxide layer covering a surface of the barrier layer other than the contact surface with the source, gate and drain structures.
In one embodiment, the P-type gate HEMT device further includes a nucleation layer disposed between the substrate layer and the buffer layer.
The second aspect of the embodiment of the application provides a method for preparing a P-type gate HEMT device, which comprises the following steps: sequentially constructing a substrate layer, a buffer layer, a channel layer, a barrier layer and a P-GaN layer from bottom to top; performing thermal oxidation on the P-GaN layer according to a preset pattern to thermally oxidize part of the P-GaN layer into an oxide layer, wherein the part of the P-GaN layer which is not thermally oxidized forms a P-GaN structure layer embedded in the oxide layer; wherein the P-GaN structure layer comprises a plurality of P-GaN substructures which are arranged on the barrier layer at intervals along a second direction in sequence; etching part of the oxide layer to the upper surface of the barrier layer, and constructing a source electrode structure and a drain electrode structure on the barrier layer; and constructing a grid metal layer on the P-GaN structure layer.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: the P-GaN substructure extending in the first direction can play a role of a field plate, the electric field between the source electrode structure and the drain electrode structure is uniform, the withstand voltage of the device is improved, and no additional capacitor is introduced. In addition, the P-GaN structure layer can be used as a passivation layer, which is beneficial to improving the current collapse resistance.
Meanwhile, the P-GaN substructures which are arranged at intervals in sequence can reduce the contact area with the barrier layer which is increased after the P-GaN substructures are prolonged, reduce the influence of the P-GaN material on the channel, and can also transversely deplete the pinch-off channel by controlling the interval between the P-GaN substructures.
The P-GaN structure layer and the oxide layer are constructed through a thermal oxidation process, so that device damage caused by an etching process can be avoided, and the problem of diffusion possibly caused by a traditional ion implantation process is avoided.
Drawings
Fig. 1 is a schematic structural diagram of a P-type gate HEMT device according to an embodiment of the present disclosure;
fig. 2 is a top view of the P-type gate HEMT device shown in fig. 1;
fig. 3 is another schematic structural diagram of a P-type gate HEMT device according to an embodiment of the present disclosure;
fig. 4 is another top view of a P-gate HEMT device according to one embodiment of the present disclosure;
fig. 5 is a flowchart of a method for manufacturing a P-type gate HEMT device according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of the P-type gate HEMT device obtained by executing the step S1 shown in fig. 5;
fig. 7 is a schematic structural diagram of the P-type gate HEMT device obtained by executing step S2 shown in fig. 5;
fig. 8 is a schematic structural diagram of the P-type gate HEMT device obtained by executing step S3 shown in fig. 5;
fig. 9 is a schematic structural diagram of the P-type gate HEMT device obtained by executing step S4 shown in fig. 5.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the present application and simplify description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Fig. 1 shows a schematic structural diagram of a P-type gate HEMT device according to an embodiment of the present application, and for convenience of explanation, only the portions related to the embodiment are shown, which are described in detail below:
as shown in fig. 1, a P-type gate HEMT device includes: a substrate layer 100, a buffer layer 200, a channel layer 300, a barrier layer 400, a source structure 500, a gate structure 600, and a drain structure 700.
The substrate layer 100, the buffer layer 200, the channel layer 300, and the barrier layer 400 are stacked in this order from bottom to top.
The source structure 500, the gate structure 600, and the drain structure 700 are sequentially disposed on the barrier layer 400 at intervals from each other in the first direction.
As shown in fig. 1 and 2, the gate structure 600 includes a P-GaN structure layer 610 and a gate metal layer 620, the P-GaN structure layer 610 is disposed on the barrier layer 400, and the gate metal layer 620 is disposed on the P-GaN structure layer 610. The P-GaN structure layer 610 includes a plurality of P-GaN sub-structures 611 sequentially disposed on the barrier layer 400 at intervals from each other along a second direction, wherein the first direction is perpendicular to the second direction, each of the P-GaN sub-structures 611 extends along the first direction, and a length of the P-GaN sub-structure 611 in the first direction is greater than a width of the gate metal layer 620 in the first direction.
It is understood that the first direction and the second direction may specifically be horizontal directions perpendicular to the vertical direction. The gate metal layer 620 is used for electrical connection with a corresponding external circuit.
In some embodiments, the substrate layer 100 is made of silicon (Si), the buffer layer 200 and the channel layer 300 are made of gallium nitride (GaN), and the barrier layer 400 is made of aluminum gallium nitride (AlGaN).
It should be noted that, the channel layer 300 and the barrier layer 400 may form a two-dimensional electron gas (2 DEG), and the source structure 500 and the drain structure 700 may transmit electric energy through a current path formed by the two-dimensional electron gas. Under the condition that the gate metal layer 620 is not applied with a voltage, the P-GaN structure layer 610 may laterally deplete electrons under the P-GaN structure layer 610, thereby blocking a current path between the source structure 500 and the drain structure 700, and at this time, the P-type gate HEMT device is in an off state. When a positive voltage is applied to the gate metal layer 620, the P-type gate HEMT device is turned back on.
By the P-GaN substructure 611 extending in the first direction, it can function as a field plate, uniform electric field between the source structure 500 to the drain structure 700, and improved device withstand voltage. In addition, the extended portion of the P-GaN substructure 611 may also serve as a passivation layer on the surface of the device, which is beneficial to increase the current collapse resistance of the device during switching.
Meanwhile, the P-GaN sub-structures 611 arranged at intervals in sequence can reduce the contact area with the barrier layer 400, which is increased after the P-GaN sub-structures 611 are prolonged, and reduce the influence of the P-GaN material on the channel, and on the other hand, the pinch-off channel can be also exhausted laterally by controlling the interval between the P-GaN sub-structures 611, so that the two-dimensional electron gas between the source structure 500 and the drain structure 700 is disconnected.
In one embodiment, the gate metal layer 620 extends in the second direction and contacts each P-GaN substructure 611.
In some embodiments, both the source structure 500 and the drain structure 700 extend in the second direction.
It can be appreciated that the P-GaN substructure 611 is in a stripe shape, and when multiple P-GaN substructure 611 are arranged together, it can function like a field plate, and the electric field between the source structure 500 and the drain structure 700 is uniform, so as to improve the voltage endurance of the P-gate HEMT device.
By adjusting the width of the P-GaN substructure 611 in the second direction, the dynamic resistance of the gate structure 600 may be improved, reducing current collapse.
In one embodiment, the two ends of each P-GaN substructure 611 are aligned with each other.
It should be noted that, in the off state of the conventional HEMT device, there is a problem that the electric field between the source and the drain is unevenly distributed, the field lines are usually concentrated on the side of the gate close to the drain, and the electric field in the channel of the device needs to be adjusted by the field plate, but the existence of the field plate introduces a capacitor, which is not beneficial to the performance of the device.
The extended P-GaN substructure 611 can function as a surface passivation layer, which is beneficial to improving the dynamic characteristics of the P-type gate HEMT device, reducing the dynamic on-resistance, and inhibiting the current collapse.
In one embodiment, the distance between the end of the P-GaN substructure 611 near the source structure 500 and the source structure 500 is equal to the distance between the gate structure 600 and the source structure 500.
Specifically, one end of each P-GaN substructure 611 near the source structure 500 is aligned with a side of the gate metal layer 620 near the source structure 500, and the other end of each P-GaN substructure 611 extends toward the drain structure 700.
In one embodiment, as shown in fig. 3, the gate structure 600 further includes an insulating layer 630, and the insulating layer 630 is disposed between the P-GaN structure layer 610 and the gate metal layer 620.
The material of the insulating layer 630 is specifically SiNx.
The gate structure 600 forms a metal-insulator-semiconductor (MIS) structure through the gate metal layer 620, the insulating layer 630 and the P-GaN structure layer 610, which is advantageous in suppressing leakage current of the gate structure 600 and improving breakdown voltage.
In some embodiments, the width of the insulating layer 630 in the first direction is equal to the width of the gate metal layer 620 in the first direction, and the length of the insulating layer 630 in the second direction is equal to the length of the gate metal layer 620 in the second direction.
In one embodiment, the pitch between two adjacent P-GaN substructure 611 ranges from 0.25 microns to 1 micron.
Illustratively, the spacing between two adjacent P-GaN substructure 611 is 1 micron.
It should be noted that, when the distance between two adjacent P-GaN substructure 611 is too large, the P-GaN substructure 611 cannot be laterally depleted to pinch off the channel, and when the distance between two adjacent P-GaN substructure 611 is too small, the contact area between the P-GaN material and the barrier layer 400 is too large, which reduces the two-dimensional electron gas concentration under the P-GaN structure layer 610, greatly affects the on-current of the device, so that the distance between two P-GaN substructure 611 needs to be limited.
In some embodiments, the width of the P-GaN substructure 611 in the second direction is equal to the spacing between two adjacent P-GaN substructure 611.
It is appreciated that the specific dimensions of each P-GaN substructure 611 may be set according to practical requirements.
In an embodiment, as shown in fig. 3 and 4 (gate structure 600 in fig. 4 only shows P-GaN substructure 611), the P-type gate HEMT device further comprises an oxide layer 800, the oxide layer 800 covering the surface of the barrier layer 400 except for the contact surfaces with the source structure 500, gate structure 600 and drain structure 700.
The material of the oxide layer 800 may specifically be gallium oxynitride (GaON), and the oxide layer 800 may be obtained by thermally oxidizing a P-GaN material. A layer of P-GaN material may be thermally oxidized in a predetermined pattern to simultaneously construct the respective P-GaN substructure 611 and the oxide layer 800.
In an embodiment, as shown in fig. 3, the P-type gate HEMT device further includes a nucleation layer 900, the nucleation layer 900 being disposed between the substrate layer 100 and the buffer layer 200.
The nucleation layer 900 may be aluminum nitride (AlN).
It is understood that the source structure 500 and the drain structure 700 each include a metal stack of Ti/Al/Ni/Au disposed on the barrier layer 400 for electrical connection with a corresponding external circuit.
Fig. 5 is a flowchart illustrating a method for manufacturing a P-type gate HEMT device according to an embodiment of the present application, and for convenience of explanation, only the portions related to the embodiment are shown, which is described in detail below:
a preparation method of a P-type gate HEMT device comprises the steps S1-S4, wherein the preparation method is used for preparing the P-type gate HEMT device according to any one of the embodiments.
Step S1: the substrate layer 100, the buffer layer 200, the channel layer 300, the barrier layer 400, and the P-GaN layer 612 are sequentially formed from bottom to top.
Specifically, as shown in fig. 6, the substrate layer 100, the buffer layer 200, the channel layer 300, the barrier layer 400, and the P-GaN layer 612 may be configured by a deposition process. Wherein, the substrate layer 100 is made of silicon (Si), the buffer layer 200 and the channel layer 300 are made of gallium nitride (GaN), and the barrier layer 400 is made of aluminum gallium nitride (AlGaN)
Step S2: the P-GaN layer 612 is thermally oxidized according to a predetermined pattern to thermally oxidize a portion of the P-GaN layer 612 into the oxide layer 800, and a portion of the P-GaN layer 612 that is not thermally oxidized constitutes the P-GaN structure layer 610 embedded in the oxide layer 800. As shown in fig. 7, the P-GaN structure layer 610 includes a plurality of P-GaN sub-structures 611 sequentially disposed on the barrier layer 400 at intervals from each other in the second direction.
Specifically, according to the number, size and position of the P-GaN substructure 611 required in practice, the corresponding P-GaN material is reserved, and the P-GaN layer 612 not belonging to the P-GaN substructure 611 is thermally oxidized, so as to obtain the P-GaN substructure 611 according to any of the embodiments described above.
It should be noted that, if the P-GaN structure layer 610 is configured by an etching process, for a nano-scale device and a micro-scale device, the etching depth is difficult to control, the concentration of two-dimensional electron gas is easy to be affected, and the degradation of the device in the use process is easy to be accelerated by the device damage caused by the etching process, and the device damage caused by the etching process can be avoided by configuring the P-GaN structure layer 610 by a thermal oxidation process, so that the diffusion problem possibly caused by the H ion implantation is avoided.
Step S3: a portion of the oxide layer 800 is etched down to the upper surface of the barrier layer 400 and the source structure 500 and the drain structure 700 are constructed on the barrier layer 400.
Specifically, as shown in fig. 8, a source structure 500, a P-GaN structure layer 610, and a drain structure 700 are sequentially disposed on the barrier layer 400 at intervals from each other in the first direction.
Step S4: a gate metal layer 620 is constructed on the P-GaN structure layer 610. The P-type gate HEMT device shown in fig. 9 can be obtained through step S4.
In an embodiment, unlike the above embodiment, step S4 is specifically: an insulating layer 630 and a gate metal layer 620 are sequentially formed on the P-GaN structure layer 610 from bottom to top.
The material of the insulating layer 630 is specifically SiNx.
A metal-insulator-semiconductor (MIS) structure is composed by the gate metal layer 620, the insulating layer 630, and the P-GaN structure layer 610, which is advantageous in suppressing leakage current of the gate structure 600.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. The utility model provides a P type gate HEMT device which characterized in that includes:
the substrate layer, the buffer layer, the channel layer and the barrier layer are sequentially stacked from bottom to top; and
a source structure, a gate structure, and a drain structure sequentially disposed on the barrier layer at a mutual interval along a first direction;
the grid structure comprises a P-GaN structure layer and a grid metal layer, the P-GaN structure layer is arranged on the barrier layer, and the grid metal layer is arranged on the P-GaN structure layer;
the P-GaN structure layer comprises a plurality of P-GaN substructures which are sequentially arranged on the barrier layer at intervals along a second direction, wherein the first direction is perpendicular to the second direction, each P-GaN substructures extends along the first direction, and the length of each P-GaN substructures in the first direction is larger than the width of the grid metal layer in the first direction.
2. The P-type gate HEMT device of claim 1, wherein said gate metal layer extends along said second direction and is in contact with each of said P-GaN substructures.
3. The P-gate HEMT device of claim 2, wherein both ends of each of said P-GaN substructures are aligned with each other.
4. The P-type gate HEMT device of claim 3, wherein an end of said P-GaN substructure proximate said source structure is equidistant from said source structure by a distance equal to a distance between said gate structure and said source structure.
5. The P-type gate HEMT device of claim 1, wherein the gate structure further comprises an insulating layer disposed between the P-GaN structure layer and the gate metal layer.
6. The P-gate HEMT device of any one of claims 1-5, wherein a pitch between two adjacent P-GaN substructures has a value in the range of 0.25 microns to 1 micron.
7. The P-type gate HEMT device of any one of claims 1-5, wherein a distance between a gate metal layer and said source structure is less than a distance between a gate metal layer and said drain structure.
8. The P-type gate HEMT device of any one of claims 1-5, further comprising an oxide layer overlying a surface of the barrier layer other than the contact surfaces with the source structure, the gate structure, and the drain structure.
9. The P-gate HEMT device of any one of claims 1-5, further comprising a nucleation layer disposed between the substrate layer and the buffer layer.
10. The preparation method of the P-type gate HEMT device is characterized by comprising the following steps:
sequentially constructing a substrate layer, a buffer layer, a channel layer, a barrier layer and a P-GaN layer from bottom to top;
performing thermal oxidation on the P-GaN layer according to a preset pattern to thermally oxidize part of the P-GaN layer into an oxide layer, wherein the part of the P-GaN layer which is not thermally oxidized forms a P-GaN structure layer embedded in the oxide layer; wherein the P-GaN structure layer comprises a plurality of P-GaN substructures which are arranged on the barrier layer at intervals along a second direction in sequence;
etching part of the oxide layer to the upper surface of the barrier layer, and constructing a source electrode structure and a drain electrode structure on the barrier layer;
and constructing a grid metal layer on the P-GaN structure layer.
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