CN218123416U - High electron mobility transistor device - Google Patents
High electron mobility transistor device Download PDFInfo
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- CN218123416U CN218123416U CN202222130781.9U CN202222130781U CN218123416U CN 218123416 U CN218123416 U CN 218123416U CN 202222130781 U CN202222130781 U CN 202222130781U CN 218123416 U CN218123416 U CN 218123416U
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Abstract
The utility model relates to a high electron mobility transistor device, including the substrate, and by nucleation layer, buffer layer, p type buried layer, channel layer, inserted layer and the barrier layer that substrate layer direction of height set gradually, still including setting up p type grid, source electrode, drain electrode and the passivation layer on the barrier layer, the source electrode reaches the drain electrode is located the relative both sides of barrier layer, the passivation layer locate the source electrode with between the drain electrode, p type grid is located the barrier layer middle part; the p-type grid electrode comprises a p-type semiconductor cap layer and a grid metal layer. Compared with the prior art, the utility model discloses a high electron mobility transistor device can obtain high threshold voltage, high saturation current and high breakdown voltage, has satisfied the practical application demand.
Description
Technical Field
The utility model relates to a semiconductor device technical field especially relates to a high electron mobility transistor device.
Background
The A1 GaN/GaN-based polarization effect generates high-concentration and high-mobility 2DEG on an interface, and the GaN material has the advantages of high band gap (3.4 eV), high critical electric field (3.3 MV/cm), low dielectric constant (9) and the like, so that the AIGaN/GaN High Electron Mobility Transistor (HEMT) has the characteristics of high frequency, high efficiency, high temperature resistance, miniaturization and the like, and has a very large application prospect in the future power electronic field. A conventional GaN-based HEMT device is a normally-on type, and in order to make the GaN-based HEMT more safe and efficient for use in a power electronic system, it may be necessary to prepare a normally-off (enhancement type) GaN-based HEMT device. However, the enhancement mode is realized while the saturation current is reduced, so that the output power of the device is greatly reduced.
In addition, the GaN-based HEMT device is often broken down in advance due to the concentration effect of the gate electric field and the leakage current of the buffer layer. The breakdown voltage is only hundreds of volts, which is far lower than the theoretical withstand voltage limit of GaN material. Therefore, the large-scale application of GaN-based HEMT devices is greatly limited.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problem, an object of the present invention is to provide a high electron mobility transistor device capable of obtaining a high threshold voltage, a high saturation current, and a high breakdown voltage.
A high electron mobility transistor device comprises a substrate, a nucleating layer, a buffer layer, a p-type buried layer, a channel layer, an insertion layer and a barrier layer, wherein the nucleating layer, the buffer layer, the p-type buried layer, the channel layer, the insertion layer and the barrier layer are sequentially arranged from the height direction of the substrate layer; the p-type grid electrode comprises a p-type semiconductor cap layer and a grid metal layer.
In addition, according to the present invention, the hemt device may further have the following additional technical features:
further, the p-type gate is provided with a comb-shaped structure in the width direction of the transistor device.
Further, the p-type semiconductor cap layer comprises a p-type GaN semiconductor cap layer, a p-type AlGaN semiconductor cap layer or a p-type NiO semiconductor cap layer; wherein the hole concentration of the p-type semiconductor cap layer is 1E 17-1E 19, and the thickness is 50-150 nm.
Further, the p-type buried layer comprises a p-type GaN buried layer, or a p-type AlGaN buried layer; wherein the hole concentration of the p-type buried layer is 1E 17-1E 18, and the thickness is 50-200 nm.
Further, the channel layer comprises a GaN channel layer, and the thickness of the channel layer is 100-400 nm; the insertion layer comprises an AlN insertion layer, and the thickness of the insertion layer is 1-2 nm; the barrier layer comprises an AlGaN barrier layer, and the thickness of the barrier layer is 10-30 nm.
Further, the buffer layer includes a GaN buffer layer, an AlGaN buffer layer, or an AlInGaN buffer layer; wherein the thickness of the buffer layer is 1-5 μm.
Further, the nucleation layer includes an AlN nucleation layer, or a low-temperature GaN nucleation layer; wherein the thickness of the nucleation layer is 10-60 nm.
Further, the passivation layer comprises a SiNx passivation layer, a SiO2 passivation layer, a HfO2 passivation layer or an Al2O3 passivation layer.
Further, the source electrode and the drain electrode each include a Ti metal electrode, an Al metal electrode, a Ni metal electrode, or an Au metal electrode.
Further, the gate metal layer includes a Ni metal electrode, or an Au metal electrode.
According to the utility model provides a high electron mobility transistor device through introducing pectination p type grid, obtains high saturation current when realizing the device enhancement mode to can also improve the breakdown voltage of device. The comb-shaped p-type grid electrode consists of a p-type semiconductor cap layer and a grid metal layer. The channel 2DEG is depleted through the p-type semiconductor cap layer, so that the enhancement type of the device is realized. By introducing the comb structure, high-concentration 2DEG is remained between the comb-shaped gaps, so that the saturation current of the device is improved. Compared with the traditional strip-shaped p-type grid electrode, the comb-shaped p-type grid electrode can enable the device to achieve enhancement and obtain high saturation current. In addition, the comb-shaped grid can enable the electric field distribution to be more uniform under high voltage, so that the electric field concentration effect of the grid is weakened, and the breakdown voltage of the device is improved. Meanwhile, the p-type buried layer is introduced below the channel layer of the device, electrons can be prevented from entering the buffer layer, the buffer leakage current is reduced, and the voltage-resistant characteristic of the device is further improved.
Drawings
Fig. 1 is a top view of an hemt device structure according to an embodiment of the present invention.
Fig. 2 is a schematic view of an exemplary hemt device epitaxial structure according to the present invention.
Fig. 3 is a cross-sectional view of a p-type cap layer etched in a hemt device according to an embodiment of the present invention.
Fig. 4 is a top view of a p-type cap layer etched in a hemt device according to an embodiment of the present invention.
Fig. 5 is a top view of the hemt device according to the embodiment of the present invention after source and drain metal deposition.
Fig. 6 is a top view of a hemt device according to an embodiment of the present invention after depositing a passivation layer.
The following detailed description of the invention will be further described in conjunction with the above-identified drawings.
Detailed Description
In order to make the objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail with reference to the accompanying drawings. Several embodiments of the invention are given in the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. As used herein, the terms "vertical," "horizontal," "left," "right," "up," "down," and the like are for illustrative purposes only and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1 to fig. 6, a hemt device includes a substrate 1, and a nucleation layer 2, a buffer layer 3, a p-type buried layer 4, a channel layer 5, an insertion layer 6, and a barrier layer 7 sequentially disposed on the substrate 1 from bottom to top, and further includes a p-type gate, a source 9, a drain 10, and a passivation layer 12 disposed in a length direction of the barrier layer 7. The source electrode 9 and the drain electrode 10 are located on opposite sides of the barrier layer 7, that is, on two sides of the barrier layer 7 in the length direction, the passivation layer 12 is disposed between the source electrode 9 and the drain electrode 10, that is, one side of the passivation layer 12 is connected to the source electrode 9, and the other side of the passivation layer 12 is connected to the drain electrode 10. The p-type gate is positioned in the middle of the barrier layer. Preferably, the p-type gate is located on a side of the barrier layer close to the source. Wherein, the substrate 1 adopts a sapphire substrate. Before the nucleation layer 2 is disposed on the substrate 1, the substrate is cleaned. Such as: sequentially placing the substrate 1 in acetone, ethanol and deionized water for ultrasonic treatment for 20min, taking out, washing with deionized water, and drying by N2 to remove pollutants on the surface of the substrate 1.
Specifically, the p-type gate is provided with a comb-shaped structure in the width direction of the transistor device, the depth of teeth of the comb-shaped structure is 0.5 μm to one half of the length of the device, and the width of the teeth is in a range of 0.5 μm to one half of the width of the device, preferably 0.5 μm. The p-type gate comprises a p-type semiconductor cap layer 8 and a gate metal layer 9. Therefore, the p-type gate comprises a p-type semiconductor cap layer 8 and a gate metal layer 9, and a comb-shaped structure is arranged in the width direction of the transistor device. In this embodiment, the comb-shaped structure of the p-type semiconductor cap layer 8 and the gate metal layer 9 extends toward the drain of the transistor device.
Further, the p-type semiconductor cap layer 8 includes a p-type GaN semiconductor cap layer, a p-type AlGaN semiconductor cap layer, or a p-type NiO semiconductor cap layer. That is, the p-type semiconductor cap layer may be a p-type GaN semiconductor cap layer, a p-type AlGaN semiconductor cap layer, or a p-type NiO semiconductor cap layer. The gate metal layer includes a Ni metal electrode, or an Au metal electrode. That is, the gate metal layer may be electrically formed using a Ni metal electrode, or an Au metal. The p-type semiconductor cap layer 8 has a hole concentration of 1E17 to 1E19 and a thickness of 50 to 150nm, preferably 100nm.
Further, the nucleation layer 2 includes an AlN nucleation layer, or a low-temperature GaN nucleation layer, preferably a low-temperature GaN nucleation layer. The thickness of the nucleating layer is 10-60 nm, and preferably 30nm. Further, the buffer layer 3 includes a GaN buffer layer, an AlGaN buffer layer, or an AlInGaN buffer layer, preferably a high-resistance GaN buffer layer. Wherein the thickness of the buffer layer is 1 to 5 μm, preferably 2.5 μm.
Further, the p-type buried layer 4 includes a p-type GaN buried layer, or a p-type AlGaN buried layer, preferably a p-type GaN buried layer. Wherein the hole concentration of the p-type buried layer is 1E 17-1E 18, and the thickness is 50-200 nm, preferably 150nm.
Further, the channel layer 5 includes a GaN channel layer, and the thickness of the channel layer is 100 to 400nm, preferably 450nm. The insertion layer 6 comprises an AlN insertion layer having a thickness of 1 to 2nm, preferably 1nm. The barrier layer 7 includes an AlGaN barrier layer (Al) 0.24 Ga 0.76 N), the thickness of the barrier layer is 10 to 30nm, preferably 20nm.
Specifically, the MOCVD process may be selected, and trimethyl aluminum (TMAl) is used as an aluminum source, trimethyl gallium (TMGa) is used as a gallium source, and ammonia (NH) 3 ) As nitrogen source, cp 2 Mg is used as a magnesium source to grow a low-temperature GaN nucleating layer 2 with the thickness of 30nm, a high-resistance GaN buffer layer 3 with the thickness of 2.5 mu m, a p-type GaN buried layer 4 with the thickness of 150nm, a GaN channel layer 5 with the thickness of 450nm, an AlN insertion layer 6 with the thickness of 1nm and Al with the thickness of 20nm on a substrate 1 in sequence 0.24 Ga 0.76 An N-barrier layer 7 and a 100nm p-type GaN cap layer 8 as shown in figure 2. And etching the selected region of the p-type GaN cap layer 8 by using an Inductively Coupled Plasma (ICP) process until the surface of the AlGaN barrier layer 7 to form the comb-shaped p-type GaN cap layer 8, wherein the cross-sectional view is shown in FIG. 3, and the top view is shown in FIG. 4.
Further, the source electrode 9 and the drain electrode 10 each include a Ti metal electrode, an Al metal electrode, a Ni metal electrode, or an Au metal electrode. In specific implementation, an electron beam evaporation process may be adopted to deposit a Ti/Al/Ni/Au metal electrode on a selected region of the surface of the AlGaN barrier layer 7, and then the metal electrode is rapidly annealed for 40 seconds in a nitrogen atmosphere at 850 ℃ to form the source electrode 9 and the drain electrode 10 which are in ohmic contact, and the top view is shown in fig. 5. Then, continuing to adopt the electron beam evaporation process, depositing a Ni/Au metal electrode on the selected region on the surface of the comb-shaped p-type GaN cap layer 8, and annealing for 10min at 30 ℃ in a nitrogen atmosphere to form a gate metal layer 11 in schottky contact, wherein the top view is shown in fig. 6.
Further, the passivation layer comprises a SiNx passivation layer, a SiO2 passivation layer, a HfO2 passivation layer, or an Al2O3 passivation layer, preferably the SiNx passivation layer. In specific implementation, an ion enhanced chemical vapor deposition (PECVD) process may be used to deposit the SiNx passivation layer 12 on the surface of the epitaxial layer, the top view of which is shown in fig. 1.
The utility model provides a high electron mobility transistor device through introducing pectination p type grid, obtains high saturation current when realizing the device enhancement mode to can also improve the breakdown voltage of device. The comb-shaped p-type grid electrode consists of a p-type semiconductor cap layer and a grid metal layer. The channel 2DEG is depleted through the p-type semiconductor cap layer, so that the enhancement type of the device is realized. By introducing the comb structure, high-concentration 2DEG is remained between the comb-shaped gaps, so that the saturation current of the device is improved. Compared with the traditional strip-shaped p-type grid electrode, the comb-shaped p-type grid electrode can enable the device to achieve enhancement and obtain high saturation current. In addition, the comb-shaped grid can enable the electric field distribution to be more uniform under high voltage, weaken the electric field concentration effect of the grid and improve the breakdown voltage of the device. Meanwhile, the p-type buried layer is introduced below the channel layer of the device, electrons can be prevented from entering the buffer layer, the buffer leakage current is reduced, and the voltage-resistant characteristic of the device is further improved.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the concept of the present invention, several variations and modifications can be made, which all fall within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (10)
1. The high-electron-mobility transistor device is characterized by comprising a substrate, a nucleating layer, a buffer layer, a p-type buried layer, a channel layer, an insertion layer and a barrier layer, wherein the nucleating layer, the buffer layer, the p-type buried layer, the channel layer, the insertion layer and the barrier layer are sequentially arranged from the height direction of the substrate layer; the p-type grid electrode comprises a p-type semiconductor cap layer and a grid metal layer.
2. The hemt device of claim 1, wherein said p-type gate is provided with a comb-like structure in the width direction of the transistor device.
3. The high electron mobility transistor device of claim 1, wherein the p-type semiconductor cap layer comprises a p-type GaN semiconductor cap layer, a p-type AlGaN semiconductor cap layer, or a p-type NiO semiconductor cap layer; wherein the hole concentration of the p-type semiconductor cap layer is 1E 17-1E 19, and the thickness is 50-150 nm.
4. The hemt device of claim 1, wherein said p-type buried layer comprises a p-type GaN buried layer, or a p-type AlGaN buried layer; wherein the hole concentration of the p-type buried layer is 1E 17-1E 18, and the thickness is 50-200 nm.
5. The hemt device of claim 1, wherein said channel layer comprises a GaN channel layer, said channel layer having a thickness of 100-400 nm; the insertion layer comprises an AlN insertion layer, and the thickness of the insertion layer is 1-2 nm; the barrier layer comprises an AlGaN barrier layer, and the thickness of the barrier layer is 10-30 nm.
6. The hemt device of claim 1, wherein said buffer layer comprises a GaN buffer layer, an AlGaN buffer layer or an AlInGaN buffer layer; wherein the thickness of the buffer layer is 1-5 μm.
7. The hemt device of claim 1, wherein said nucleation layer comprises an AlN nucleation layer, or a low-temperature GaN nucleation layer; wherein the thickness of the nucleating layer is 10-60 nm.
8. The hemt device of claim 1, wherein said passivation layer comprises a SiNx passivation layer, a SiO2 passivation layer, a HfO2 passivation layer, or an Al2O3 passivation layer.
9. The hemt device of claim 1, wherein said source and drain electrodes each comprise a Ti metal electrode, an Al metal electrode, a Ni metal electrode, or an Au metal electrode.
10. The hemt device of claim 1, wherein said gate metal layer comprises a Ni metal electrode, or an Au metal electrode.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117810249A (en) * | 2024-02-23 | 2024-04-02 | 深圳天狼芯半导体有限公司 | P-type gate HEMT device and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117810249A (en) * | 2024-02-23 | 2024-04-02 | 深圳天狼芯半导体有限公司 | P-type gate HEMT device and preparation method thereof |
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