CN109920850A - Enhancement transistor and preparation method thereof based on III race's oxide passivation - Google Patents
Enhancement transistor and preparation method thereof based on III race's oxide passivation Download PDFInfo
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Abstract
The invention discloses a kind of enhancement transistors and preparation method thereof based on III race's oxide passivation.The production method includes: that growth on substrate forms hetero-junctions comprising the first semiconductor and the second semiconductor being formed on the first semiconductor, second semiconductor has the band gap for being wider than the first semiconductor, and two-dimensional electron gas is formed in hetero-junctions；Cap is formed on the second semiconductor, it includes doped region and passivation region, the doped region is covered by third semiconductor group at and by grid completely, passivation region is distributed between grid and drain electrode and between grid and source electrode, and the third semiconductor is for exhausting the two-dimensional electron gas for being distributed in region under grid in hetero-junctions；Make source electrode, drain electrode and grid.Enhancement transistor of the invention can avoid uniformity caused by etching P-doped zone, repeatability and introduce damage problem, also can avoid hydrogen plasma and be passivated the resistive formation to be formed may being activated again at high temperature caused device reliability issues.
Description
Technical field
The present invention relates to a kind of enhancement transistors, and in particular to a kind of enhanced crystal based on III race's oxide passivation
Pipe and preparation method thereof, belongs to technical field of semiconductor device.
Background technique
For current era with economic rapid development, the resource-effective consciousness of people's environmental protection is more and more denseer, it is desirable that
Loss in energy sources conversion is lower and lower, efficiency is higher and higher, and in order to realize the efficient requirement of this low-loss,
Power electronic technique is needed to control energy conversion, utilizes core devices-power device of power conversion in power electronic system
Part, to reduce the energy consumption in conversion process, realizes efficient conversion effectively to be converted and be controlled to the energy
Process.But traditional power device is no longer satisfied existing technology development.
As important third generation semiconductor material with wide forbidden band, gallium nitride (GaN) forbidden bandwidth big (3.4eV), breakdown potential
Field is high (> 3MV/cm), the two-dimensional electron gas height (> 10 of AlGaN/GaN hetero-junctions13cm-2), electronics saturation drift velocity it is high
(2.8×107Cm/s), and the chemical inertness of GaN material and high-temperature stability are good.Therefore, AlGaN/GaN high electron mobility is brilliant
Body pipe (HEMT) can obtain very high breakdown voltage, power density and high working frequency, and switching loss is very small.
It, can shape in the interface AlGaN/GaN since there is stronger piezoelectricity and spontaneous polarizations in GaN base hetero-junctions
At the two-dimensional electron gas of high concentration, therefore, conventional GaN base HEMT is depletion device, also referred to as normally on device.In practical electricity
Lu Zhong needs a negative supply to close device, therefore exists and open by mistake the danger opened.So for power electronic circuit
Design, enhanced HEMT device is essential, becomes current research hotspot, and a technology in the urgent need to address at present
Problem.During the realization of enhanced AlGaN/GaN HEMT device, main purpose is by various technological means by grid
Under two-dimensional electron gas exhaust, be in close state device under zero-bias, several mainly realize enhanced HEMT device at present
The method of part has: recessed grid structure, fluorine ion injection technique and p-type cap technology etc., these technologies respectively have its advantage and disadvantage.Closely
Nian Lai has researcher to be passivated P-doped zone nut cap layer method based on hydrogen plasma and realize enhanced high mobility
Transistor, process may include: to form hetero-junctions using AlGaN and GaN, since the polarized hetero-junctions position that acts on generates
Two-dimensional electron gas (2DEG) then grown one layer of P-doped zone (by taking P-GaN as an example) on AlGaN/GaN hetero-junctions, improve
Hole concentration, exhausts the two-dimensional electron gas in channel, then deposit metal electrodes pass through H again2Plasma passivation, so that not having
Have by the P-doped zone and H of gate metal covering part2Passivation reaction occurs and forms resistive formation, loses and exhausts channel two dimension electricity
The effect of sub- gas releases the two-dimensional electron gas in region under non-grid, and under grid region P-doped zone without and H2Deng from
Daughter reaction, still plays a part of exhausting grid lower channel two-dimensional electron gas, realizes the enhanced characteristic of device.This method
Allow the P-doped zone cap and H in region under non-grid2Plasma reaction forms resistive formation, caused by avoiding lithographic method
The problems such as etching homogeneity, repeatability and introducing damage, but region P-doped zone is H under non-grid2Plasma passivation is formed
Resistive formation, when device operating temperature is more than 450 DEG C, the P-doped zone resistive formation being passivated is possible to be reactivated, because
The long-term reliability of this hydrogen plasma passivating method needs further to be verified.Although in addition, under non-grid region P-doped zone by
Passivation is resistive formation, still has certain polarization, and can reduce influences channel two-dimensional electron gas, reduces saturation electricity
Stream.
Summary of the invention
In view of the deficiencies of the prior art, the object of the present invention is to provide a kind of enhanced crystalline substances based on III race's oxide passivation
Body pipe and preparation method thereof.
To realize the above goal of the invention, present invention employs technical solutions as described below:
The embodiment of the invention provides a kind of production method of enhancement transistor based on III race's oxide passivation, packets
It includes:
Growth forms hetero-junctions on substrate comprising the first semiconductor and what is be formed on the first semiconductor the second half lead
Body, second semiconductor has the band gap for being wider than the first semiconductor, and is formed with two-dimensional electron gas in the hetero-junctions；
Cap is formed on second semiconductor, the cap includes doped region and passivation region, the doped region
It is covered completely by third semiconductor group at and by grid, the passivation region is distributed between grid and drain electrode and grid and source electrode
Between, the third semiconductor is for exhausting the two-dimensional electron gas for being distributed in region under grid in the hetero-junctions；
Source electrode, drain electrode and grid are made, wherein grid is located between source electrode and drain electrode, and source electrode and drain electrode can pass through institute
State two-dimensional electron gas electrical connection.
In some embodiments, the production method may also include that
Continuous third semiconductor is grown on second semiconductor,
Oxidation processes are carried out to the third semiconductor being distributed between grid and drain electrode and between grid and source electrode, thus
The passivation region is formed, and is retained and is located at the third semiconductor in region under grid and forms the doped region.
Further, the method for the oxidation processes includes dry method thermal oxide, means of wet thermal oxidation, O2Corona treatment, O3
Any one of corona treatment.
In some embodiments, the production method may also include that
Three semiconductor of growth regulation on second semiconductor, and form the doped region；
It is located between grid and drain electrode on second semiconductor and is grown in the region between grid and source electrode blunt
Change material, to form the passivation region, and the doped region and passivation region is made to cooperatively form the cap.
In some embodiments, the production method may also include that
Continuous third semiconductor is grown on second semiconductor；
Removing is distributed between grid and drain electrode and the third semiconductor between grid and source electrode, and retains and be located under grid
The third semiconductor in region and form the doped region；And
It is located between grid and drain electrode on second semiconductor and is grown in the region between grid and source electrode blunt
Change material, to form the passivation region.
Further, the material of the first semiconductor, the second semiconductor, third semiconductor is described blunt selected from III group-III nitride
Change area to be formed by III race's oxide.
Further, the material of second semiconductor includes AlGaN.
Further, the material of first semiconductor includes GaN.
Further, the material of the third semiconductor includes p-type GaN.
Further, the material of the passivation region includes gallium oxide.
Further, the production method includes: at least to grow shape in a manner of any in MOCVD, HVPE, MBE
At the hetero-junctions, third semiconductor.
Further, the production method include: at least grown in a manner of any in ALD, MOCVD, MBE it is described
Passivating material.
Further, the production method includes: to etch removing distribution using dry etching and/or wet etching mode
Third semiconductor between grid and drain electrode and between grid and source electrode.
The embodiment of the invention also provides a kind of enhancement transistors based on III race's oxide passivation comprising:
Hetero-junctions comprising the first semiconductor and the second semiconductor being formed on the first semiconductor, described the second half lead
Body has the band gap for being wider than the first semiconductor, and is formed with two-dimensional electron gas in the hetero-junctions；
The cap being formed on the second semiconductor comprising doped region and passivation region, the doped region are partly led by third
Body is formed and is covered completely by grid, and the passivation region is distributed between grid and drain electrode and between grid and source electrode, described
Third semiconductor is for exhausting the two-dimensional electron gas for being distributed in region under grid in the hetero-junctions；
Source electrode, drain electrode and grid, wherein grid is located between source electrode and drain electrode, and source electrode and drain electrode can pass through described two
Dimensional electron gas electrical connection.
Further, the doped region is wholely set with passivation region.
Further, insert layer is also distributed between first semiconductor and the second semiconductor.
Further, the hetero-junctions is formed on the buffer layer, and the buffer layer is formed on substrate.
Further, the enhancement transistor further includes the 4th semiconductor, and first semiconductor is formed in the 4th half
On conductor.
Preferably, the material of the 4th semiconductor includes AlGaN.
Further, Ohmic contact is formed between the source electrode, drain electrode and hetero-junctions；And/or the grid and doped region
Between form Schottky contacts.
Further, when the voltage applied on the grid is greater than cut-in voltage, the source electrode and drain electrode passes through two
Dimensional electron gas electrical connection, opens the enhancement transistor；And when the voltage applied on the grid is less than the unlatching
When voltage, the two-dimensional electron gas in the hetero-junctions positioned at region under grid is depleted, and closes the enhancement transistor.
Compared with the prior art, the invention has the advantages that
1) middle partial etching P-doped zone nut cap layer method, the present invention are blunt using III race's oxide compared with the prior art
Change layer since the P-doped zone for not needing to device performs etching, avoid uniformity because etching technics introduces, repeatability and
Damage problem is introduced, thereby may be ensured that the high electron mobility of grid lower channel layer will not be impacted；
2) compared with the prior art in hydrogen plasma passivation P-doped zone nut cap layer method formed resistive formation, this
Region P-doped zone under non-grid is transformed into III race's oxide by oxidizing process or other methods by invention, utilizes III race's oxide
It realizes that passivation effect, III race's oxide have outstanding high-temperature stability, also can guarantee that p-type is adulterated when temperature is higher than 450 DEG C
Area will not be reactivated, and ensure that the reliability of device；In addition, it is (high to be passivated the resistive formation to be formed relative to hydrogen plasma
Hinder GaN or AlGaN etc.), polarity effect is not present in III race's oxide, improves the two-dimensional electron gas in channel layer, can be improved
The conducting electric current of device reduces conducting resistance.
3) since the overall structure of enhancement transistor of the invention is that an epitaxial growth forms, the present invention passes through oxidation
Region P-doped zone under non-grid is transformed into III race's oxide by method or other methods, without technologies such as etching or secondary epitaxies,
Interfacial state will not be introduced；
4) since P-doped zone processing method is optimized, the overall structure of enhancement transistor, which is prepared, to be simplified simultaneously
Reduce the techniques such as etching or ion implanting, it is possible to device complexity and device preparation cost be effectively reduced.
Detailed description of the invention
Fig. 1 is that a kind of structure of the enhancement transistor based on III race's oxide passivation is shown in an of the invention exemplary embodiments
It is intended to.
Fig. 2 is to be epitaxially grown on the substrate hetero-junctions and the epitaxial growth on hetero-junctions in an exemplary embodiments of the invention
The schematic diagram of P-GaN doped region.
Fig. 3 is the schematic diagram of the growth protecting layer on P-GaN doped region in an exemplary embodiments of the invention.
Fig. 4 is to carry out showing for oxidation processes after growth protecting layer on P-GaN doped region in an exemplary embodiments of the invention
It is intended to.
Fig. 5 is the structural schematic diagram for removing protective layer in an exemplary embodiments of the invention after oxidation processes.
Fig. 6 is in another exemplary embodiments of the present invention by region P-GaN doped region etches away under non-grid structural schematic diagram.
Fig. 7 is to have etched the structural schematic diagram behind source-drain electrode region in an exemplary embodiments of the invention.
Fig. 8 a, Fig. 8 b are a kind of enhanced crystal based on III race's oxide passivation in an exemplary embodiments of the invention respectively
Off state, the on state schematic diagram of pipe.
Specific embodiment
In view of deficiency in the prior art, inventor is studied for a long period of time and is largely practiced, and is able to propose of the invention
Region P-doped zone under non-grid is mainly changed into Ш race oxide using oxidizing process or other technologies by technical solution, is protected
The P-doped zone in region under grid is stayed, to realize the transistor of the enhanced operating mode of p-type cap.
Specifically, the present invention is using P-doped zone cap/AlGaN potential barrier/GaN channel layer/substrate, (or p-type is mixed
The similar structures such as miscellaneous area's cap/AlGaN potential barrier/AlN/GaN channel layer/substrate) material structure, by oxidizing process or its
Region P-doped zone under non-grid is become Ш race oxide by his method, is retained region P-doped zone under grid, is exhausted channel layer two
Dimensional electron gas (2DEG) realizes enhanced (normally-off) operating mode of device, avoids caused by etching P-doped zone uniformly
Property, repeatability and introduce damage problem, avoid hydrogen plasma be passivated under the resistive formation high temperature to be formed be possible to swashed again
Long term device integrity problem caused by living.
The technical solution, its implementation process and principle etc. will be further explained as follows.But it should manage
Solution, within the scope of the present invention, each technical characteristic of the invention and specifically described in below (e.g. embodiment) each technical characteristic
Between can be combined with each other, to form a new or preferred technical solution.Due to space limitations, I will not repeat them here.
A kind of system for enhancement transistor based on III race's oxide passivation that the one aspect of the embodiment of the present invention provides
Make method comprising:
Growth forms hetero-junctions on substrate comprising the first semiconductor and what is be formed on the first semiconductor the second half lead
Body, second semiconductor has the band gap for being wider than the first semiconductor, and is formed with two-dimensional electron gas in the hetero-junctions；
Cap is formed on second semiconductor, the cap includes doped region and passivation region, the doped region
It is covered completely by third semiconductor group at and by grid, the passivation region is distributed between grid and drain electrode and grid and source electrode
Between, the third semiconductor is for exhausting the two-dimensional electron gas for being distributed in region under grid in the hetero-junctions；
Source electrode, drain electrode and grid are made, wherein grid is located between source electrode and drain electrode, and source electrode and drain electrode can pass through institute
State two-dimensional electron gas electrical connection.
In some embodiments, the production method may also include that
Continuous third semiconductor is grown on second semiconductor,
Oxidation processes are carried out to the third semiconductor being distributed between grid and drain electrode and between grid and source electrode, thus
The passivation region is formed, and is retained and is located at the third semiconductor in region under grid and forms the doped region.
Further, the method for the oxidation processes includes the dry method thermal oxide of different temperatures, means of wet thermal oxidation, O2Deng from
Daughter, O3The method that P-doped zone can be oxidized to Ш race oxide in all kinds of oxidizing process of the oxygen plasmas such as plasma.
More specifically, the production method may include:
At least third is epitaxially-formed on the hetero-junctions in a manner of any in MOCVD, HVPE, MBE partly to lead
Body；In the grid of the third semiconductor, source-drain regions growth protecting layer at least in a manner of PECVD；
By the third semiconductor oxide in region under non-grid at passivation region at least in a manner of oxidation；
Later, the protective layer is removed at least in a manner of etching, etch areas can be shifted by photoetching and exposure mask
Etc. technologies be determined.
Preferably, the material of the protective layer includes SiO2Or Si3N4, but not limited to this.The growth district of the protective layer
It can be determined by the technologies such as photoetching and exposure mask transfer.
Further, the oxygen source that the oxidation uses can be O2、O3、H2O etc., but not limited to this.
Further, the temperature of the oxidation is 500~1500 DEG C, and the time is that a few minutes are unlimited to tens hours.
Wherein, oxidation rate and oxidated layer thickness can be adjusted according to experiment conditions such as oxidizing temperature, times.Meanwhile Ш race
Thickness, pattern and crystal quality of oxide etc. can also accurately be controlled according to oxidation or growth conditions.
In some embodiments, region P-doped zone under non-grid can also be transformed into Ш by other methods by the present invention
Race's oxide." other methods " above-mentioned, which refers to, is able to achieve under non-grid under region Ш race's oxide and grid that region p-type is mixed including all
Miscellaneous district's groups at cap structure all methods.
In some embodiments, the production method may also include that
Three semiconductor of growth regulation on second semiconductor, and form the doped region；
It is located between grid and drain electrode on second semiconductor and is grown in the region between grid and source electrode blunt
Change material, to form the passivation region, and the doped region and passivation region is made to cooperatively form the cap.
In some embodiments, the production method may also include that
Continuous third semiconductor is grown on second semiconductor；
Removing is distributed between grid and drain electrode and the third semiconductor between grid and source electrode, and retains and be located under grid
The third semiconductor in region and form the doped region；And
It is located between grid and drain electrode on second semiconductor and is grown in the region between grid and source electrode blunt
Change material, to form the passivation region.
More specifically, outer on the hetero-junctions in region under non-grid at least in a manner of any in ALD, MOCVD, MBE
Prolong growth and forms passivation region.
Specifically, utilizing growth deposition method (such as atomic layer deposition (ALD), metallochemistry organic vapor phase deposition
(MOCVD), the methods of molecular beam epitaxy (MBE)) the grown Ga that is etched away in aforementioned P-doped zone2O3Passivation region.
Further, the production method may also include that and at least lead to the second half be located at immediately below source electrode and drain electrode
Body performs etching, until reaching hetero-junctions surface.
Further, the material of the first semiconductor, the second semiconductor, third semiconductor is described blunt selected from III group-III nitride
Change area to be formed by III race's oxide.
Further, the material of second semiconductor includes AlGaN, but not limited to this.
Further, the material of first semiconductor includes GaN, but not limited to this.
Further, the material of the third semiconductor includes p-type GaN, but not limited to this.
Further, the material of the passivation region includes gallium oxide, but not limited to this.
Further, the production method includes: at least to grow shape in a manner of any in MOCVD, HVPE, MBE
At the hetero-junctions, third semiconductor.
Further, the production method include: at least grown in a manner of any in ALD, MOCVD, MBE it is described
Passivating material.
Further, the production method includes: to etch removing distribution using dry etching and/or wet etching mode
Third semiconductor between grid and drain electrode and between grid and source electrode.
Specifically, will be needed for source and drain areas using the dry or wet etch such as reactive ion etching, ion beam etching technology
Depth, in order to form good Ohmic contact, etch areas can be determined purpose by the technologies such as photoetching and exposure mask transfer.
Preferably, etching above-mentioned includes the dry etchings, wet etching technique such as reactive ion etching, ion beam etching,
But not limited to this.
Further, the production method may also include that the system at least in a manner of any in electron beam evaporation, sputtering
Form source electrode, drain electrode, grid.
The embodiment of the invention also provides a kind of enhancement transistors based on III race's oxide passivation comprising:
Hetero-junctions comprising the first semiconductor and the second semiconductor being formed on the first semiconductor, described the second half lead
Body has the band gap for being wider than the first semiconductor, and is formed with two-dimensional electron gas in the hetero-junctions；
The cap being formed on the second semiconductor comprising doped region and passivation region, the doped region are partly led by third
Body is formed and is covered completely by grid, and the passivation region is distributed between grid and drain electrode and between grid and source electrode, described
Third semiconductor is for exhausting the two-dimensional electron gas for being distributed in region under grid in the hetero-junctions；
Source electrode, drain electrode and grid, wherein grid is located between source electrode and drain electrode, and source electrode and drain electrode can pass through described two
Dimensional electron gas electrical connection.
Further, the material of the first semiconductor, the second semiconductor, third semiconductor is described blunt selected from III group-III nitride
Change area to be formed by III race's oxide.
Further, the material of second semiconductor includes AlGaN, but not limited to this.
Further, the material of first semiconductor includes GaN, but not limited to this.
Further, the material of the third semiconductor includes p-type GaN, but not limited to this.
Further, the material of the passivation region includes gallium oxide, but not limited to this.
Further, the doped region is wholely set with passivation region.
Further, insert layer is also distributed between first semiconductor and the second semiconductor.
Further, the material of the insert layer includes AlN, but not limited to this.
Further, the hetero-junctions is formed on the buffer layer, and the buffer layer is formed on substrate.
Further, the enhancement transistor further includes the 4th semiconductor, and first semiconductor is formed in the 4th half
On conductor, wherein the 4th semiconductor is for two-dimensional electron gas is limited in channel layer (i.e. the first half as back barrier layer
Conductor) in, prevent electronics from entering buffer layer.
Preferably, the material of the 4th semiconductor includes AlGaN, but not limited to this.
In some embodiment of the invention, below the cap can for AlGaN potential barrier/GaN channel layer/substrate,
AlGaN potential barrier/AlN/GaN channel layer/substrate, AlGaN potential barrier/AlN/GaN channel layer/AlGaN back barrier layer/substrate etc.
Similar structures, but not limited to this.
Further, Ohmic contact is formed between the source electrode, drain electrode and hetero-junctions.
Further, Schottky contacts are formed between the grid and doped region.
Further, when the voltage applied on the grid is greater than cut-in voltage, the source electrode and drain electrode passes through two
Dimensional electron gas electrical connection, opens the enhancement transistor；And when the voltage applied on the grid is less than the unlatching
When voltage, the two-dimensional electron gas in the hetero-junctions positioned at region under grid is depleted, and closes the enhancement transistor.
In conclusion enhancement transistor of the invention can avoid uniformity caused by etching P-doped zone, repeatability and
Damage problem is introduced, also can avoid hydrogen plasma and be passivated the resistive formation to be formed may being activated again at high temperature caused device
Part integrity problem.
Below in conjunction with attached drawing and more specifically embodiment makees further clear, complete solution to technical solution of the present invention
Release explanation.
It please refers to Fig. 1 and shows a kind of enhanced crystalline substance based on III race's oxide passivation in a typical embodiments of the invention
Body pipe comprising substrate, buffer layer, GaN channel layer (i.e. the first semiconductor), AlGaN potential barrier (i.e. the second semiconductor), p-
GaN doped region (i.e. third semiconductor), Ga2O3Passivation region and grid G, source S and drain D.
An of the invention exemplary embodiments pass through in AlGaN/GaN/ substrate (or the similar knot such as AlGaN/AlN/GaN/ substrate
Structure) material structure on one layer of P-doped zone (in Fig. 1 by taking P-GaN as an example) of extension, and pass through oxidizing process (including the hot oxygen of dry method
Change, means of wet thermal oxidation, O2Plasma, O3All kinds of oxidizing process such as plasma) or other methods region p-type under non-grid is adulterated
Area is transformed into Ш race oxide (Ga in Fig. 12O3For), passivation is realized by Ш race oxide, it is lost and exhausts channel
Two-dimensional electron gas effect, the two-dimensional electron gas in region under non-grid is released, and the P-doped zone in region still plays under grid
The effect of grid lower channel two-dimensional electron gas is exhausted, to realize the enhanced characteristic of device.
Material structure key in an exemplary embodiments of the invention is one layer of the top by region Ш race oxide under non-grid
(with Ga in Fig. 12O3For) and grid under the cap that forms of region P-doped zone (in Fig. 1 by taking P-GaN as an example), below cap
Can for AlGaN potential barrier/GaN channel layer/substrate, AlGaN potential barrier/AlN/GaN channel layer/substrate, AlGaN potential barrier/
The similar structures such as AlN/GaN channel layer/AlGaN back barrier layer/substrate.
A typical embodiments of the invention, will using oxidizing process or other technologies by device design structure shown in FIG. 1
Region P-doped zone is changed into Ш race oxide (Ga in Fig. 1 under non-grid2O3For), retain the P-doped zone (figure in region under grid
In 1 by taking P-GaN as an example), to realize the transistor of the enhanced operating mode of p-type cap.With current partial etching, hydrogen etc. from
The methods of daughter passivation is compared, and Ш race proposed by the present invention oxid passivation does not need under the grid to device and grid are with outskirt
Domain performs etching, and effectively prevents the uniformity because etching technics introduces, repeatability and introduces damage problem；Relative to hydrogen etc. from
Daughter is passivated for the resistive formation to be formed, and chemical property physical property is all highly stable at high temperature for Ш race oxide, is had excellent
Elegant high-temperature stability guarantees that device works under the hot environment higher than 450 DEG C, and Ш race oxide passivation will not be passivated
Layer is activated the case where failing again, and the reliability of device has been effectively ensured；In addition, being passivated the resistive formation to be formed relative to hydrogen
Polarity effect is not present in (high resistant GaN or AlGaN etc.), Ш race oxide, and the conducting electric current of device can be improved, and reduces electric conduction
Resistance.Further, since the overall structure growth of device is simplified and reduces the techniques such as etching or ion implanting, it is possible to have
Effect reduces device complexity and device preparation cost.
A kind of preparation process stream of the enhancement transistor based on III race's oxide passivation in an exemplary embodiments of the invention
Specific step is as follows for journey:
(1) Metal Organic Chemical Vapor Deposition (MOCVD) or molecular beam epitaxy (MBE) or hydrite vapor phase are utilized
Extension (HVPE) homepitaxy technology grows material structure as shown in Figure 2 (in Fig. 2 by taking P-GaN/AlGaNGaN/ substrate as an example),
Before (a) is growth P-doped zone (the present embodiment is by taking P-GaN doped region as an example) in Fig. 2, since polarity effect generates two dimension electricity
Sub- gas, (b) is that two-dimensional electron gas is depleted after extension P-GaN doped region in Fig. 2, and from (a) to (b) is an extension in Fig. 2
Growth is formed.
(2) the material structure table obtained using the methods of plasma enhanced chemical vapor deposition (PECVD) in step (1)
Face defines figure growth protecting layer (such as SiO2Or Si3N4Deng with SiO in text2For), growth district by photoetching and can be covered
The technologies such as film transfer are determined, as shown in Figure 3.
(3) oxidizing process (including dry method thermal oxide, means of wet thermal oxidation, O are utilized2Plasma, O3All kinds of oxygen such as plasma
Change method, oxygen source can be O2、O3、H2O etc. uses O in Fig. 4 with dry method thermal oxide, oxygen source2For) to what is obtained in step (2)
Material is aoxidized, by the P-GaN zone oxidation of not protective layer at Ш race oxide (with Ga in the present embodiment2O3For), oxygen
Changing speed and oxidated layer thickness can be adjusted according to experiment conditions such as oxidizing temperature, times, as shown in Figure 4.
When oxidizing temperature is 850 DEG C, and oxidization time is 5h, the oxidated layer thickness for obtaining Ш race oxide is 50nm；
When oxidizing temperature is 900 DEG C, and oxidization time is 5h, the oxidated layer thickness for obtaining Ш race oxide is 120nm；
When oxidizing temperature is 950 DEG C, and oxidization time is 5h, the oxidated layer thickness for obtaining Ш race oxide is 300nm.
(4) protective layer is removed using the dry or wet etch technology such as reactive ion etching, ion beam etching, etched area
Domain can be determined by the technologies such as photoetching and exposure mask transfer, as shown in Figure 5.
(5) using the dry or wet etch technology such as reactive ion etching, ion beam etching by depth needed for source and drain areas,
Purpose is in order to form good Ohmic contact, and etch areas can be determined by the technologies such as photoetching and exposure mask transfer, such as Fig. 7
It is shown.
(6) using metal deposition techniques such as electron beam evaporation or sputterings, source electrode is made on step (5) obtained material structure
S, drain D and grid G, finally obtained structure is as shown in Figure 1.
(7) (the V when meeting gate source voltage less than threshold voltageGS<VTH), the enhancement transistor is in an off state (such as
Shown in Fig. 8 a)；(the V when meeting gate source voltage greater than threshold voltageGS>VTH), the enhancement transistor is in the conductive state (such as
Shown in Fig. 8 b).
A kind of preparation process of the enhancement transistor based on III race's oxide passivation in another exemplary embodiments of the present invention
Specific step is as follows for process:
(1) Metal Organic Chemical Vapor Deposition (MOCVD) or molecular beam epitaxy (MBE) or hydrite vapor phase are utilized
Extension (HVPE) homepitaxy technology grows material structure as shown in Figure 2 (in Fig. 2 by taking P-GaN/AlGaNGaN/ substrate as an example),
Before (a) is growth P-doped zone (the present embodiment is by taking P-GaN doped region as an example) in Fig. 5, since polarity effect generates two dimension electricity
Sub- gas, (b) is that two-dimensional electron gas is depleted after extension P-GaN doped region in Fig. 2, and from (a) to (b) is an extension in Fig. 2
Growth is formed.
It (2) will be under the non-grid in step (1) using dry or wet etch technologies such as reactive ion etching, ion beam etchings
The technologies such as region P-GaN doped layer etches away, and etch areas can be shifted by photoetching and exposure mask are determined, as shown in Figure 6.
(3) using growth deposition method, (such as atomic layer deposition (ALD), is divided metallochemistry organic vapor phase deposition (MOCVD)
The methods of beamlet extension (MBE)) the grown Ga that falls of the material etch in step (2)2O3, obtain knot as shown in Figure 5
Structure.
(4) using the dry or wet etch technology such as reactive ion etching, ion beam etching by depth needed for source and drain areas,
Purpose is in order to form good Ohmic contact, and etch areas can be determined by the technologies such as photoetching and exposure mask transfer, such as Fig. 7
It is shown.
(5) using metal deposition techniques such as electron beam evaporation or sputterings, source electrode is made on step (4) obtained material structure
S, drain D and grid G, finally obtained structure is as shown in Figure 1.
(6) (the V when meeting gate source voltage less than threshold voltageGS<VTH), the enhancement transistor is in an off state (such as
Shown in Fig. 8 a)；(the V when meeting gate source voltage greater than threshold voltageGS>VTH), the enhancement transistor is in the conductive state (such as
Shown in Fig. 8 b).
Through the foregoing embodiment it can be found that the present invention uses P-doped zone cap/AlGaN potential barrier/GaN channel
The material knot of layer/substrate (or the similar structures such as P-doped zone cap/AlGaN potential barrier/AlN/GaN channel layer/substrate)
Region P-doped zone under non-grid is become Ш race oxide by oxidizing process or other methods, retains region p-type under grid and mix by structure
Miscellaneous area exhausts channel layer two-dimensional electron gas (2DEG), realizes enhanced (normally-off) operating mode of device, avoids etching P
Uniformity caused by type doped region, repeatability and introducing damage problem avoid hydrogen plasma and are passivated the resistive formation to be formed height
Temperature is lower to be possible to long term device integrity problem caused by being activated again.
It should be noted that the terms "include", "comprise" or its any other variant are intended in the present specification
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence " including one ... ", it is not excluded that wrapping
Include in the process, method, article or equipment of the element that there is also other identical elements.
It should be appreciated that the above preferred embodiment is merely to illustrate the contents of the present invention, in addition to this, there are also other by the present invention
Embodiment, as long as those skilled in the art because of technical inspiration involved in the present invention, and use equivalent replacement or equivalent deformation
The technical solution that mode is formed is fallen within the scope of protection of the present invention.
Claims (19)
1. a kind of production method of the enhancement transistor based on III race's oxide passivation, characterized by comprising:
Growth forms hetero-junctions on substrate comprising the first semiconductor and the second semiconductor being formed on the first semiconductor,
Second semiconductor has the band gap for being wider than the first semiconductor, and is formed with two-dimensional electron gas in the hetero-junctions；
Cap is formed on second semiconductor, the cap includes doped region and passivation region, and the doped region is by
Three semiconductor groups are covered completely at and by grid, the passivation region be distributed between grid and drain electrode and grid and source electrode it
Between, the third semiconductor is for exhausting the two-dimensional electron gas for being distributed in region under grid in the hetero-junctions；
Source electrode, drain electrode and grid are made, wherein grid is located between source electrode and drain electrode, and source electrode and drain electrode can pass through described two
Dimensional electron gas electrical connection.
2. manufacturing method according to claim 1, characterized by comprising:
Continuous third semiconductor is grown on second semiconductor,
Oxidation processes are carried out to the third semiconductor being distributed between grid and drain electrode and between grid and source electrode, to be formed
The passivation region, and retain and be located at the third semiconductor in region under grid and form the doped region.
3. production method according to claim 2, which is characterized in that the method for the oxidation processes includes the hot oxygen of dry method
Change, means of wet thermal oxidation, O2Corona treatment, O3Any one of corona treatment.
4. manufacturing method according to claim 1, characterized by comprising:
Three semiconductor of growth regulation on second semiconductor, and form the doped region；
On second semiconductor be located at grid and drain electrode between and the region between grid and source electrode in growth of passivation material
Material to form the passivation region, and makes the doped region and passivation region cooperatively form the cap.
5. production method according to claim 4, characterized by comprising:
Continuous third semiconductor is grown on second semiconductor；
Removing is distributed between grid and drain electrode and the third semiconductor between grid and source electrode, and retains and be located at region under grid
Third semiconductor and form the doped region；And
On second semiconductor be located at grid and drain electrode between and the region between grid and source electrode in growth of passivation material
Material, to form the passivation region.
6. production method according to any one of claims 1-5, it is characterised in that: the first semiconductor, the second semiconductor,
The material of third semiconductor is selected from III group-III nitride, and the passivation region is formed by III race's oxide.
7. production method according to claim 6, it is characterised in that: the material of second semiconductor includes AlGaN；
And/or the material of first semiconductor includes GaN；And/or the material of the third semiconductor includes p-type GaN；And/or
The material of the passivation region includes gallium oxide.
8. production method according to any one of claims 1-5, characterized by comprising: at least with MOCVD, HVPE,
Any mode in MBE grows to form the hetero-junctions, third semiconductor.
9. the production method according to any one of claim 4-5, characterized by comprising: at least with ALD, MOCVD,
Any mode in MBE grows the passivating material.
10. production method according to claim 5, characterized by comprising: use dry etching and/or wet etching side
Formula etching removing is distributed between grid and drain electrode and the third semiconductor between grid and source electrode.
11. a kind of enhancement transistor based on III race's oxide passivation, characterized by comprising:
Hetero-junctions comprising the first semiconductor and the second semiconductor being formed on the first semiconductor, the second semiconductor tool
There is the band gap for being wider than the first semiconductor, and is formed with two-dimensional electron gas in the hetero-junctions；
The cap being formed on the second semiconductor comprising doped region and passivation region, the doped region is by third semiconductor group
It is covered completely at and by grid, the passivation region is distributed between grid and drain electrode and between grid and source electrode, the third
Semiconductor is for exhausting the two-dimensional electron gas for being distributed in region under grid in the hetero-junctions；
Source electrode, drain electrode and grid, wherein grid is located between source electrode and drain electrode, and source electrode and drain electrode can pass through the two dimension electricity
Sub- pneumoelectric connection.
12. the enhancement transistor according to claim 11 based on III race's oxide passivation, it is characterised in that: the first half
Conductor, the second semiconductor, third semiconductor material be selected from III group-III nitride, the passivation region formed by III race's oxide.
13. the enhancement transistor according to claim 12 based on III race's oxide passivation, it is characterised in that: described
The material of semiconductor includes GaN；And/or the material of second semiconductor includes AlGaN；And/or the third is partly led
The material of body includes p-type GaN；And/or the material of the passivation region includes gallium oxide.
14. the enhancement transistor based on III race's oxide passivation described in any one of 1-13 according to claim 1, feature
Be: the doped region is wholely set with passivation region.
15. the enhancement transistor according to claim 11 based on III race's oxide passivation, it is characterised in that: described
Insert layer is also distributed between semiconductor and the second semiconductor；Preferably, the material of the insert layer includes AlN.
16. the enhancement transistor according to claim 11 based on III race's oxide passivation, it is characterised in that: described different
Matter knot is formed on the buffer layer, and the buffer layer is formed on substrate.
17. the enhancement transistor according to claim 11 based on III race's oxide passivation, it is characterised in that further include
4th semiconductor, first semiconductor are formed on the 4th semiconductor；Preferably, the material of the 4th semiconductor includes
AlGaN。
18. the enhancement transistor according to claim 11 based on III race's oxide passivation, it is characterised in that: the source
Ohmic contact is formed between pole, drain electrode and hetero-junctions；And/or Schottky contacts are formed between the grid and doped region.
19. the enhancement transistor based on III race's oxide passivation described in any one of 1-13,15-18 according to claim 1,
It is characterized by: the source electrode and drain electrode passes through Two-dimensional electron when the voltage applied on the grid is greater than cut-in voltage
Pneumoelectric connection, opens the enhancement transistor；And when the voltage applied on the grid is less than the cut-in voltage,
Two-dimensional electron gas in the hetero-junctions positioned at region under grid is depleted, and closes the enhancement transistor.
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