CN116825829A - Semiconductor super junction power device - Google Patents
Semiconductor super junction power device Download PDFInfo
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- CN116825829A CN116825829A CN202210281110.4A CN202210281110A CN116825829A CN 116825829 A CN116825829 A CN 116825829A CN 202210281110 A CN202210281110 A CN 202210281110A CN 116825829 A CN116825829 A CN 116825829A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 210000000746 body region Anatomy 0.000 claims abstract description 42
- 230000010355 oscillation Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
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- Junction Field-Effect Transistors (AREA)
Abstract
The embodiment of the invention provides a semiconductor super junction power device, which comprises: an n-type drain region; an n-type drift region located over the n-type drain region; a plurality of p-type pillars forming a charge balance structure between the p-type pillars and the n-type drift region; the top of the p-type column is provided with a first p-type body region, and a first n-type source region is arranged in the first p-type body region; a first gate groove is arranged between the first p-type body regions which are partially adjacent, and a first gate dielectric layer and a first gate are arranged in the first gate groove; at least two second gate trenches are arranged between the rest adjacent first p-type body regions, and a second gate dielectric layer and a second gate are arranged in each second gate trench. The invention can adjust the change curve of the gate-drain capacitance of the semiconductor superjunction power device and reduce the grid voltage oscillation caused by abrupt change of the gate-drain capacitance.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a semiconductor super junction power device.
Background
The semiconductor super-junction power device is based on a charge balance technology, so that on-resistance and parasitic capacitance can be reduced, the semiconductor super-junction power device has extremely fast switching characteristics, switching loss can be reduced, and higher power conversion efficiency is realized. In the turn-on and turn-off process of the semiconductor super junction power device, the miller capacitance (Crss) and the corresponding gate-drain capacitance (Cgd) play an important role in the switching process of the semiconductor super junction power device. When the known semiconductor super junction power device is turned on and turned off, the gate-drain capacitance (Cgd) is suddenly changed, so that the electrical performance of the semiconductor super junction power device is also suddenly changed.
Disclosure of Invention
Therefore, the invention aims to provide a semiconductor super junction power device capable of adjusting the change curve of the gate-drain capacitance, so as to solve the problem of abrupt change of the gate-drain capacitance of the semiconductor super junction power device in the prior art.
The embodiment of the invention provides a semiconductor super junction power device, which comprises:
an n-type drain region;
an n-type drift region located over the n-type drain region;
a plurality of p-type pillars forming a charge balance structure between the p-type pillars and the n-type drift region;
the top of the p-type column is provided with a first p-type body region, and a first n-type source region is arranged in the first p-type body region;
a first gate groove is arranged between the first p-type body regions which are partially adjacent, and a first gate dielectric layer and a first gate are arranged in the first gate groove;
at least two second gate trenches are arranged between the rest adjacent first p-type body regions, and a second gate dielectric layer and a second gate are arranged in each second gate trench.
Optionally, the semiconductor superjunction power device of the present invention further comprises a second p-type body region interposed between adjacent first p-type body regions and between adjacent second gate trenches
Optionally, in the semiconductor super junction power device of the present invention, a second n-type source region is disposed in the second p-type body region.
Optionally, in the semiconductor super junction power device of the present invention, the width of the second gate trench is smaller than the width of the first gate trench.
Another embodiment of the present invention provides a semiconductor superjunction power device, including:
an n-type drain region;
an n-type drift region located over the n-type drain region;
a plurality of p-type pillars forming a charge balance structure between the p-type pillars and the n-type drift region;
the top of the p-type column is provided with a first p-type body region, and a first n-type source region is arranged in the first p-type body region;
a first gate groove is arranged between the first p-type body regions which are partially adjacent, and a first gate dielectric layer and a first gate are arranged in the first gate groove;
and a third gate groove is arranged between the rest adjacent first p-type body regions, and a third gate dielectric layer and two third gates are arranged in the third gate groove.
Optionally, in the semiconductor super junction power device of the present invention, the width of the third gate trench is greater than the width of the first gate trench.
Optionally, in the semiconductor super junction power device of the present invention, the two third gates are respectively located at two sides of the third gate trench, and the two third gates are insulated and isolated.
According to the semiconductor super-junction power device, the first gate grooves are formed between the first p-type body regions which are partially adjacent, and the at least two second gate grooves are formed between the rest of the first p-type body regions which are adjacent, so that the change curve of gate-drain capacitance can be adjusted, and gate voltage oscillation caused by abrupt change of the gate-drain capacitance is reduced.
Drawings
In order to more clearly illustrate the technical solution of the exemplary embodiments of the present invention, a brief description is given below of the drawings required for describing the embodiments.
Fig. 1 is a schematic cross-sectional structure of a first embodiment of a semiconductor superjunction power device provided by the present invention;
fig. 2 is a schematic cross-sectional structure of a second embodiment of the semiconductor super junction power device provided by the present invention;
fig. 3 is a schematic cross-sectional structure of a third embodiment of the semiconductor super junction power device provided by the present invention.
Detailed Description
The technical solutions of the present invention will be fully described below by way of specific modes in connection with the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. Meanwhile, in order to clearly illustrate the specific embodiments of the present invention, the sizes of the figures listed in the drawings are not represented by actual sizes, and the drawings in the description are schematic and should not limit the scope of the present invention.
Fig. 1 is a schematic cross-sectional structure of a first embodiment of a semiconductor superjunction power device according to the present invention, as shown in fig. 1, where the semiconductor superjunction power device according to the embodiment of the present invention includes an n-type drain region 20, and the n-type drain region 20 may be externally connected to a drain voltage through a metal layer. An n-type drift region 21 located above the n-type drain region 20.
A plurality of p-type pillars 22, wherein a charge balance structure is formed between the p-type pillars 22 and the n-type drift region 21. For ease of illustration and description, only three p-type pillar 22 structures are shown by way of example in fig. 1.
A first p-type body region 23 is provided at the top of each p-type column 22, and a first n-type source region 24 is provided within the first p-type body region 23.
Between some adjacent first p-type body regions 23, there are at least two second gate trenches 31 between the remaining adjacent first p-type body regions 23, and for convenience of illustration and explanation, only two second gate trench 31 structures are shown in fig. 1 by way of example, the first gate trench 30 is provided with the first gate dielectric layer 25 and the first gate 26, and the second gate trench 31 is provided with the second gate dielectric layer 35 and the second gate 36. In order to facilitate the provision of a charge balance structure formed between the p-type pillars 22 and the n-type drift region 21, it is preferable that the width of the second gate trench 31 is made smaller than the width of the first gate trench 30.
The semiconductor super junction power device is characterized in that a first gate groove is arranged between part of adjacent first p-type body regions, and at least two second gate grooves are arranged between the rest of adjacent first p-type body regions, so that at least two different gate-drain capacitance values are arranged in the semiconductor super junction power device, and in the switching process, abrupt change points of gate-drain capacitance are separated onto different source-drain voltage points, so that the abrupt change speed of the gate-drain capacitance is reduced, and gate voltage oscillation caused by abrupt change of the gate-drain capacitance is reduced.
Fig. 2 is a schematic cross-sectional structure of a second embodiment of the semiconductor superjunction power device provided in the present invention, where the semiconductor superjunction power device shown in fig. 2 is based on the semiconductor superjunction power device shown in fig. 1, and further includes a second p-type body region 33 between adjacent first p-type body regions 23 and between adjacent second gate trenches 31, and optionally, a second n-type source region (not shown in the embodiment of the present invention) may be further disposed in the second p-type body region 33. By arranging the second p-type body region, the abrupt change speed of the gate-drain capacitance can be further regulated.
Fig. 3 is a schematic cross-sectional structure of a third embodiment of the semiconductor superjunction power device provided by the present invention, and as shown in fig. 3, the semiconductor superjunction power device of the present invention includes an n-type drain region 20, and an n-type drift region 21 located above the n-type drain region 20. A plurality of p-type pillars 22, wherein a charge balance structure is formed between the p-type pillars 22 and the n-type drift region 21. A first p-type body region 23 is provided at the top of each p-type column 22, and a first n-type source region 24 is provided within the first p-type body region 23.
A first gate trench 30 between two adjacent first p-type body regions 23, a third gate trench 32 between the remaining adjacent first p-type body regions 23, a first gate dielectric layer 25 and a first gate 26 disposed in the first gate trench 30, and a third gate dielectric layer 45 and two third gates 46 disposed in the third gate trench 32. Preferably, two third gates 46 are respectively located at two sides of the third gate trench 32, and the two third gates 46 are insulated and isolated by an insulating layer 47.
In order to facilitate the provision of a charge balance structure formed between the p-type pillars 22 and the n-type drift region 21, it is preferable to make the width of the third gate trench 32 larger than the width of the first gate trench 30.
The above specific embodiments and examples are specific support for the technical idea of the present invention, and the scope of the present invention is not limited thereby, and any equivalent changes or equivalent modifications made on the basis of the technical scheme according to the technical idea of the present invention still belong to the scope of the technical scheme of the present invention.
Claims (7)
1. The semiconductor super junction power device is characterized by comprising:
an n-type drain region;
an n-type drift region located over the n-type drain region;
a plurality of p-type pillars forming a charge balance structure between the p-type pillars and the n-type drift region;
the top of the p-type column is provided with a first p-type body region, and a first n-type source region is arranged in the first p-type body region;
a first gate groove is arranged between the first p-type body regions which are partially adjacent, and a first gate dielectric layer and a first gate are arranged in the first gate groove;
at least two second gate trenches are arranged between the rest adjacent first p-type body regions, and a second gate dielectric layer and a second gate are arranged in each second gate trench.
2. The semiconductor superjunction power device of claim 1, further comprising a second p-type body region interposed between adjacent ones of the first p-type body regions and between adjacent ones of the second gate trenches.
3. The semiconductor superjunction power device of claim 2, wherein a second n-type source region is provided within the second p-type body region.
4. The semiconductor superjunction power device of claim 1, wherein the width of the second gate trench is less than the width of the first gate trench.
5. The semiconductor super junction power device is characterized by comprising:
an n-type drain region;
an n-type drift region located over the n-type drain region;
a plurality of p-type pillars forming a charge balance structure between the p-type pillars and the n-type drift region;
the top of the p-type column is provided with a first p-type body region, and a first n-type source region is arranged in the first p-type body region;
a first gate groove is arranged between the first p-type body regions which are partially adjacent, and a first gate dielectric layer and a first gate are arranged in the first gate groove;
and a third gate groove is arranged between the rest adjacent first p-type body regions, and a third gate dielectric layer and two third gates are arranged in the third gate groove.
6. The semiconductor superjunction power device of claim 5, wherein the width of the third gate trench is greater than the width of the first gate trench.
7. The semiconductor superjunction power device of claim 5, wherein two of said third gates are respectively located on two sides of said third gate trench, and wherein two of said third gates are insulated from each other.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210281110.4A CN116825829A (en) | 2022-03-21 | 2022-03-21 | Semiconductor super junction power device |
| PCT/CN2022/101560 WO2023178865A1 (en) | 2022-03-21 | 2022-06-27 | Semiconductor super-junction power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210281110.4A CN116825829A (en) | 2022-03-21 | 2022-03-21 | Semiconductor super junction power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116825829A true CN116825829A (en) | 2023-09-29 |
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ID=88099727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210281110.4A Pending CN116825829A (en) | 2022-03-21 | 2022-03-21 | Semiconductor super junction power device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN116825829A (en) |
| WO (1) | WO2023178865A1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9099320B2 (en) * | 2013-09-19 | 2015-08-04 | Force Mos Technology Co., Ltd. | Super-junction structures having implanted regions surrounding an N epitaxial layer in deep trench |
| CN104952928A (en) * | 2015-04-30 | 2015-09-30 | 苏州东微半导体有限公司 | Gate-drain capacitance slow change super-junction power device and manufacturing method thereof |
| CN106229343B (en) * | 2016-08-12 | 2019-05-03 | 上海鼎阳通半导体科技有限公司 | Superjunction devices |
| CN112447822A (en) * | 2019-09-03 | 2021-03-05 | 苏州东微半导体股份有限公司 | Semiconductor power device |
-
2022
- 2022-03-21 CN CN202210281110.4A patent/CN116825829A/en active Pending
- 2022-06-27 WO PCT/CN2022/101560 patent/WO2023178865A1/en unknown
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| Publication number | Publication date |
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| WO2023178865A1 (en) | 2023-09-28 |
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