CN111599866A - Low-grid charge power MOSFET device with U-shaped separation grid and manufacturing method thereof - Google Patents
Low-grid charge power MOSFET device with U-shaped separation grid and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a low-gate charge power MOSFET device with a U-shaped separation gate and a manufacturing method thereof, and the low-gate charge power MOSFET device comprises a first conduction type substrate, wherein a first conduction type epitaxial layer is arranged on the upper surface of the first conduction type substrate, a groove structure is arranged in the first conduction type epitaxial layer, a control gate electrode and a separation gate electrode are contained in the groove structure, a second conduction type well region is arranged above the first conduction type epitaxial layer, a second conduction type heavily doped region is arranged above the second conduction type well region, the control gate electrode and the second conduction type well region are separated by a gate dielectric layer, and a first conduction type heavily doped source region is arranged above the second conduction type well region. Thereby achieving the goals of high switching speed and low switching loss.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a low-gate charge power MOSFET device with a U-shaped separation gate and a manufacturing method thereof.
Background
A double-step separation gate Trench MOSFET is provided in an article '100-V Class Two-step-oxide Field-plate Trench MOSFET to Achieve optimal RESURF Effect and ultra low On-resistance' of Kenya Kobayashi et al, and the Effect of the double-step separation gate Trench MOSFET can greatly optimize an electric Field between a groove structure and a groove structure, so that the withstand voltage can be improved or the doping can be improved under the condition of keeping the same withstand voltage, and the On-resistance is further reduced. However, the power management system requires a low parasitic capacitance of the power semiconductor device to reduce the switching loss of the device, and the structure proposed in the article by Kenya Kobayashi et al has a larger coupling area between the split gate and the control gate, which results in an increase in gate charge, thereby reducing the switching time and increasing the switching loss.
Therefore, in response to the above problems, there is a need to reduce the large gate charge problem of the structures proposed by Kenya Kobayashi et al, against which embodiments of the present invention arise.
Disclosure of Invention
The invention provides a low-gate charge power MOSFET device with a U-shaped separation gate and a manufacturing method thereof, and a structure proposed by Kenyakubayashi et al is shown in figure 1, wherein a larger area at the top of the separation gate is coupled with a control gate, so that the gate-source capacitance is increased, the input capacitance is increased, and further, the problems of low switching speed, increased switching loss and the like are caused. In the invention, as shown in fig. 2, the upper half part of the separation gate is hollowed on the basic structure proposed by Kenya Kobayashi et al to form a U-shaped separation gate, which reduces the coupling area between the separation gate electrode and the control gate electrode, and increases the coupling distance between the separation gate electrode and the control gate electrode, thereby reducing the coupling capacitance between the separation gate electrode and the control gate electrode, i.e. the gate-source capacitance, and realizing the purposes of high switching speed and low switching loss, and forming a low-gate-charge power MOSFET device with the U-shaped separation gate.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a low-gate charge power MOSFET device with a U-shaped separation gate comprises a first conduction type substrate 10, a first conduction type epitaxial layer 11 is arranged on the upper surface of the first conduction type substrate 10, a groove structure 12 is arranged in the first conduction type epitaxial layer 11, the groove structure 12 comprises a control gate electrode 15 and a separation gate electrode 14, wherein the control gate electrode 15 is positioned on the upper half portion of the groove structure 12, the separation gate electrode 14 is positioned on the lower half portion of the groove structure 12, the control gate electrode 15 and the separation gate electrode 14 are separated by a second dielectric layer 132 and a third dielectric layer 133, the third dielectric layer 133 is positioned above the second dielectric layer 132, the separation gate electrode 14 and the first conduction type epitaxial layer 11 are separated by a first dielectric layer 131, a second conduction type well region 16 is arranged above the first conduction type epitaxial layer 11, a second conduction type heavily doped region 18 is arranged above the inner portion of the second conduction type well region 16, the control gate electrode 15 and the second conductive type well region 16 are separated by a gate dielectric layer 134, a first conductive type heavily doped source region 19 is arranged above the second conductive type well region 16, a hole is punched in the first conductive type heavily doped source region 19 and the second conductive type heavily doped region 18 to lead out a metal 20, and the metal 20 and the control gate electrode 15 are separated by a fourth dielectric layer 135.
Preferably, the lower half of the split gate electrode 14 is a longitudinal linear split gate, and the upper half is a U-shaped split gate.
Preferably, the device is prepared by the following manufacturing method:
1) forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner wall of each groove structure;
2) depositing heavily doped polysilicon in the trench structure to fill the trench with the heavily doped polysilicon;
3) etching the heavily doped polysilicon deposited in the step 2);
4) etching the first dielectric layer, wherein a part of the first dielectric layer is still remained on the inner side wall of the groove structure and is not etched;
6) depositing heavily doped polysilicon to make the upper part of the heavily doped polysilicon in a U shape, wherein a gap is still left in the middle of the U shape and is not filled;
7) forming a second dielectric layer in the groove structure without leaving a gap;
8) etching the second dielectric layer, wherein a part of the second dielectric layer is still remained in the U-shaped structure and is not etched;
9) etching the heavily doped polysilicon deposited in the step 6) to form a final U-shaped heavily doped polysilicon structure;
10) forming a third dielectric layer in the groove structure without leaving a gap;
11) etching the first dielectric layer, the second dielectric layer and the third dielectric layer to enable the upper surfaces of the first dielectric layer, the second dielectric layer and the third dielectric layer to be higher than the upper surface of the U-shaped heavily doped polysilicon;
12) forming a gate dielectric layer, depositing and etching heavily doped polysilicon to form a control gate electrode;
13) and forming a second conductive type well region and a first conductive type heavily doped source region, forming a fourth dielectric layer, punching holes in the first conductive type heavily doped source region and the second conductive type well region to form a second conductive type heavily doped region, injecting metal and leading out potential.
Preferably, a step 5) is further included between the step 4) and the step 6):
5) and etching the heavily doped polysilicon after the etching in the step 3) to ensure that the upper surface of the heavily doped polysilicon is not higher than the lower surface of the first dielectric layer after the etching of the first dielectric layer in the step 4).
Preferably, a step 5) is further included between the step 4) and the step 6):
and 5) through an oxidation process, enabling the upper surface of the heavily doped polysilicon not to be higher than the lower surface of the first dielectric layer after the etching of the first dielectric layer in the step 4).
Preferably, the third dielectric layer 133 is a low K dielectric.
Preferably, the second dielectric layer 132 is a low K dielectric.
Preferably, the first dielectric layer 131 is a low K dielectric.
In order to achieve the above object, the present invention further provides a low gate charge power MOSFET device with a U-shaped split gate, comprising a first conductivity type substrate 10, a first conductivity type epitaxial layer 11 is disposed on the upper surface of the first conductivity type substrate 10, a trench structure 12 is disposed in the first conductivity type epitaxial layer 11, the trench structure 12 includes a control gate electrode 15 and a hollow U-shaped split gate electrode 14, wherein the control gate electrode 15 is disposed on the upper half portion of the trench structure 12, the hollow U-shaped split gate electrode 14 is disposed on the lower half portion of the trench structure 12, the control gate electrode 15 and the hollow U-shaped split gate electrode 14 are separated by a first dielectric layer 131, the hollow U-shaped split gate electrode 14 is separated from the first conductivity type epitaxial layer 11 by a first dielectric layer 131, a second conductivity type well region 16 is disposed above the first conductivity type epitaxial layer 11, and a second conductivity type heavily doped region 18 is disposed above the inside the second conductivity type well region 16, a first conductive type heavily doped source region 19 is arranged above the second conductive type well region 16, a hole is punched in the first conductive type heavily doped source region 19 and the second conductive type heavily doped region 18 to lead out a metal 20, and the metal 20 is separated from the control gate electrode 15 by a fourth dielectric layer 135.
In order to achieve the above object, the present invention further provides a method for manufacturing a low gate charge power MOSFET device with a U-shaped split gate, comprising the following steps:
1) forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner wall of each groove structure;
2) depositing heavily doped polysilicon in the trench structure to fill the trench with the heavily doped polysilicon;
3) etching the heavily doped polysilicon deposited in the step 2);
4) etching the first dielectric layer, wherein a part of the first dielectric layer is still remained on the inner side wall of the groove structure and is not etched;
5) etching or oxidizing the heavily doped polysilicon after the etching in the step 3) to ensure that the upper surface of the heavily doped polysilicon is not higher than the lower surface of the first dielectric layer after the etching of the first dielectric layer in the step 4);
6) depositing heavily doped polysilicon to make the upper part of the heavily doped polysilicon in a U shape, wherein a gap is still left in the middle of the U shape and is not filled;
7) forming a second dielectric layer in the groove structure without leaving a gap;
8) etching the second dielectric layer, wherein a part of the second dielectric layer is still remained in the U-shaped structure and is not etched;
9) etching the heavily doped polysilicon deposited in the step 6) to form a final U-shaped heavily doped polysilicon structure;
10) forming a third dielectric layer in the groove structure without leaving a gap;
11) etching the first dielectric layer, the second dielectric layer and the third dielectric layer to enable the upper surfaces of the first dielectric layer, the second dielectric layer and the third dielectric layer to be higher than the upper surface of the U-shaped heavily doped polysilicon;
12) forming a gate dielectric layer, depositing and etching heavily doped polysilicon to form a control gate electrode;
13) and forming a second conductive type well region and a first conductive type heavily doped source region, forming a fourth dielectric layer, punching holes in the first conductive type heavily doped source region and the second conductive type well region to form a second conductive type heavily doped region, injecting metal and leading out potential.
The invention has the beneficial effects that: the upper half part of the separation gate is hollowed on the basic structure proposed by Kenya Kobayashi et al to be made into a U-shaped separation gate, and the structure reduces the coupling area between the separation gate electrode and the control gate electrode, and simultaneously increases the coupling distance between the separation gate electrode and the control gate electrode, so that the coupling capacitance between the separation gate electrode and the control gate electrode, namely the gate source capacitance, is reduced, the purposes of high switching speed and low switching loss are achieved, and the low-gate charge power MOSFET device with the U-shaped separation gate is formed.
Drawings
FIG. 1 is a basic structure proposed by Kenya Kobayashi et al.
Fig. 2 is a diagram of a low-gate charge power MOSFET device with U-shaped split gate according to the present invention.
Fig. 3 is a manufacturing method of a low-gate charge power MOSFET device with U-shaped split gate according to the present invention, which is performed from left to right and from top to bottom.
FIG. 4 shows the structure of the present invention and the basic structure of Kenya Kobayashi et al at a second conductivity type well region concentration of 5e16cm-3And a first conductivity type epitaxial layer concentration of 6.5e16 cm-3The comparison graph of the gate voltage and the charging time curve under the condition of the invention can be obtained from the graph, and the structure of the invention is used for chargingThere is a significant decrease in time.
Fig. 5 shows an embodiment of the proposed structure, which is different from the structure of the present invention in that the dielectric layer between the split gate electrode and the control gate electrode is a low-K dielectric layer, which can further reduce the gate-source capacitance.
Fig. 6 shows an embodiment of a proposed structure, which is different from the structure of the present invention in that a low-K dielectric layer is filled in the U-shaped split gate electrode, so that the gate-source capacitance can be further reduced.
Fig. 7 shows a structure proposed in the embodiment, which is different from the structure of the present invention in that the entire split gate electrode is surrounded by a low-K dielectric, so that the gate-source capacitance and the source-drain capacitance can be further reduced.
Fig. 8 shows an embodiment of a proposed structure, which is different from the structure of the present invention in that the split gate electrode has a hollow trapezoid shape, so that the coupling area between the control gate electrode and the split gate electrode can be further reduced, the coupling distance can be increased, and the gate-source capacitance can be further reduced.
10 is a first conductive type substrate, 11 is a first conductive type epitaxial layer, 12 is a trench structure, 131 is a first dielectric layer, 132 is a second dielectric layer, 133 is a third dielectric layer, 134 is a gate dielectric layer, 135 is a fourth dielectric layer, 14 is a split gate electrode, 15 is a control gate electrode, 16 is a second conductive type well region, 18 is a second conductive type heavily doped region, 19 is a first conductive type heavily doped source region, and 20 is a metal.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
As shown in fig. 2, a low gate charge power MOSFET device with U-shaped split gate includes a first conductivity type substrate 10, a first conductivity type epitaxial layer 11 is disposed on the upper surface of the first conductivity type substrate 10, a trench structure 12 is disposed in the first conductivity type epitaxial layer 11, the trench structure 12 includes a control gate electrode 15 and a split gate electrode 14, wherein the control gate electrode 15 is disposed on the upper half of the trench structure 12, the split gate electrode 14 is disposed on the lower half of the trench structure 12, the control gate electrode 15 and the split gate electrode 14 are separated by a second dielectric layer 132 and a third dielectric layer 133, the third dielectric layer 133 is disposed above the second dielectric layer 132, the split gate electrode 14 and the first conductivity type epitaxial layer 11 are separated by a first dielectric layer 131, a second conductivity type well region 16 is disposed above the first conductivity type epitaxial layer 11, a second conductivity type heavily doped region 18 is disposed above the inside the second conductivity type well region 16, the control gate electrode 15 and the second conductive type well region 16 are separated by a gate dielectric layer 134, a first conductive type heavily doped source region 19 is arranged above the second conductive type well region 16, a hole is punched in the first conductive type heavily doped source region 19 and the second conductive type heavily doped region 18 to lead out a metal 20, and the metal 20 and the control gate electrode 15 are separated by a fourth dielectric layer 135.
The lower half part of the split gate electrode 14 is a longitudinal linear split gate, and the upper half part is a U-shaped split gate.
The device is prepared by the following manufacturing method:
1) forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner wall of each groove structure;
2) depositing heavily doped polysilicon in the trench structure to fill the trench with the heavily doped polysilicon;
3) etching the heavily doped polysilicon deposited in the step 2);
4) etching the first dielectric layer, wherein a part of the first dielectric layer is still remained on the inner side wall of the groove structure and is not etched;
5) and etching or oxidizing the heavily doped polysilicon after the etching in the step 3) to ensure that the upper surface of the heavily doped polysilicon is not higher than the lower surface of the first dielectric layer after the etching of the first dielectric layer in the step 4).
6) Depositing heavily doped polysilicon to make the upper part of the heavily doped polysilicon in a U shape, wherein a gap is still left in the middle of the U shape and is not filled;
7) forming a second dielectric layer in the groove structure without leaving a gap;
8) etching the second dielectric layer, wherein a part of the second dielectric layer is still remained in the U-shaped structure and is not etched;
9) etching the heavily doped polysilicon deposited in the step 6) to form a final U-shaped heavily doped polysilicon structure;
10) forming a third dielectric layer in the groove structure without leaving a gap;
11) etching the first dielectric layer, the second dielectric layer and the third dielectric layer to enable the upper surfaces of the first dielectric layer, the second dielectric layer and the third dielectric layer to be higher than the upper surface of the U-shaped heavily doped polysilicon;
12) forming a gate dielectric layer, depositing and etching heavily doped polysilicon to form a control gate electrode;
13) and forming a second conductive type well region and a first conductive type heavily doped source region, forming a fourth dielectric layer, punching holes in the first conductive type heavily doped source region and the second conductive type well region to form a second conductive type heavily doped region, injecting metal and leading out potential.
Example 2
As shown in fig. 5, the present embodiment is different from the structure described in embodiment 1 in that: the third dielectric layer 133 is a low K dielectric to further reduce the gate-source capacitance.
Example 3
As shown in fig. 6, the present embodiment differs from embodiment 1 in that: the second dielectric layer 132 is a low-K dielectric, which can further reduce the gate-source capacitance.
Example 4
As shown in fig. 7, the present embodiment differs from embodiment 1 in that: the first dielectric layer 131 is a low-K dielectric, which can further reduce the gate-source capacitance and the source-drain capacitance.
Example 5
As shown in fig. 8, the present embodiment provides a low gate charge power MOSFET device with a U-shaped split gate, including a first conductivity type substrate 10, a first conductivity type epitaxial layer 11 is disposed on an upper surface of the first conductivity type substrate 10, a trench structure 12 is disposed in the first conductivity type epitaxial layer 11, the trench structure 12 includes a control gate electrode 15 and a hollow U-shaped split gate electrode 14, wherein the control gate electrode 15 is disposed on an upper half portion of the trench structure 12, the hollow U-shaped split gate electrode 14 is disposed on a lower half portion of the trench structure 12, the control gate electrode 15 and the hollow U-shaped split gate electrode 14 are separated by a first dielectric layer 131, the hollow U-shaped split gate electrode 14 is separated from the first conductivity type epitaxial layer 11 by the first dielectric layer 131, a second conductivity type well region 16 is disposed above the first conductivity type epitaxial layer 11, a second conductivity type heavily doped region 18 is disposed above an inside the second conductivity type well region 16, a first conductive type heavily doped source region 19 is arranged above the second conductive type well region 16, a hole is punched in the first conductive type heavily doped source region 19 and the second conductive type heavily doped region 18 to lead out a metal 20, and the metal 20 is separated from the control gate electrode 15 by a fourth dielectric layer 135.
The present embodiment is different from embodiment 1 in that the split gate has a hollow U-shape without a lower longitudinal linear split gate portion, which can further reduce the coupling area between the control gate electrode and the split gate electrode, increase the coupling distance, and further reduce the gate-source capacitance.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A low-gate charge power MOSFET device with a U-shaped split gate, comprising: the device comprises a first conductive type substrate (10), wherein a first conductive type epitaxial layer (11) is arranged on the upper surface of the first conductive type substrate (10), a groove structure (12) is arranged in the first conductive type epitaxial layer (11), the groove structure (12) comprises a control gate electrode (15) and a separation gate electrode (14), the control gate electrode (15) is positioned on the upper half part of the groove structure (12), the separation gate electrode (14) is positioned on the lower half part of the groove structure (12), the control gate electrode (15) and the separation gate electrode (14) are separated by a second medium layer (132) and a third medium layer (133), the third medium layer (133) is positioned above the second medium layer (132), the separation gate electrode (14) and the first conductive type epitaxial layer (11) are separated by a first medium layer (131), and a second conductive type well region (16) is arranged above the first conductive type epitaxial layer (11), a second conductive type heavily doped region (18) is arranged above the inside of the second conductive type well region (16), the control gate electrode (15) and the second conductive type well region (16) are separated by a gate dielectric layer (134), a first conductive type heavily doped source region (19) is arranged above the second conductive type well region (16), a hole is punched in the first conductive type heavily doped source region (19) and the second conductive type heavily doped region (18) to lead out metal (20), and the metal (20) and the control gate electrode (15) are separated by a fourth dielectric layer (135).
2. A low gate charge power MOSFET device according to claim 1 having a U-shaped split gate, wherein: the lower half part of the separation gate electrode (14) is a longitudinal linear separation gate, and the upper half part is a U-shaped separation gate.
3. A low gate charge power MOSFET device according to claim 1 having a U-shaped split gate, wherein the method of manufacturing comprises the steps of:
1) forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner wall of each groove structure;
2) depositing heavily doped polysilicon in the trench structure to fill the trench with the heavily doped polysilicon;
3) etching the heavily doped polysilicon deposited in the step 2);
4) etching the first dielectric layer, wherein a part of the first dielectric layer is still remained on the inner side wall of the groove structure and is not etched;
6) depositing heavily doped polysilicon to make the upper part of the heavily doped polysilicon in a U shape, wherein a gap is still left in the middle of the U shape and is not filled;
7) forming a second dielectric layer in the groove structure without leaving a gap;
8) etching the second dielectric layer, wherein a part of the second dielectric layer is still remained in the U-shaped structure and is not etched;
9) etching the heavily doped polysilicon deposited in the step 6) to form a final U-shaped heavily doped polysilicon structure;
10) forming a third dielectric layer in the groove structure without leaving a gap;
11) etching the first dielectric layer, the second dielectric layer and the third dielectric layer to enable the upper surfaces of the first dielectric layer, the second dielectric layer and the third dielectric layer to be higher than the upper surface of the U-shaped heavily doped polysilicon;
12) forming a gate dielectric layer, depositing and etching heavily doped polysilicon to form a control gate electrode;
13) and forming a second conductive type well region and a first conductive type heavily doped source region, forming a fourth dielectric layer, punching holes in the first conductive type heavily doped source region and the second conductive type well region to form a second conductive type heavily doped region, injecting metal and leading out potential.
4. A low gate charge power MOSFET device according to claim 3 having a U-shaped split gate, wherein: between step 4) and step 6) further comprising step 5):
5) and etching the heavily doped polysilicon after the etching in the step 3) to ensure that the upper surface of the heavily doped polysilicon is not higher than the lower surface of the first dielectric layer after the etching of the first dielectric layer in the step 4).
5. A low gate charge power MOSFET device according to claim 3 having a U-shaped split gate, wherein: between step 4) and step 6) further comprising step 5):
and 5) through an oxidation process, enabling the upper surface of the heavily doped polysilicon not to be higher than the lower surface of the first dielectric layer after the etching of the first dielectric layer in the step 4).
6. A low gate charge power MOSFET device according to claim 1 having a U-shaped split gate, wherein: the third dielectric layer (133) is a low-K dielectric.
7. A low gate charge power MOSFET device according to claim 1 having a U-shaped split gate, wherein: the second dielectric layer (132) is a low-K dielectric.
8. A low gate charge power MOSFET device according to claim 1 having a U-shaped split gate, wherein: the first dielectric layer (131) is a low-K dielectric.
9. A low-gate charge power MOSFET device with a U-shaped split gate, comprising: the device comprises a first conductive type substrate (10), wherein a first conductive type epitaxial layer (11) is arranged on the upper surface of the first conductive type substrate (10), a groove structure (12) is arranged in the first conductive type epitaxial layer (11), the groove structure (12) comprises a control gate electrode (15) and a hollow U-shaped separation gate electrode (14), the control gate electrode (15) is positioned on the upper half part of the groove structure (12), the hollow U-shaped separation gate electrode (14) is positioned on the lower half part of the groove structure (12), the control gate electrode (15) and the hollow U-shaped separation gate electrode (14) are separated by a first medium layer (131), the hollow U-shaped separation gate electrode (14) and the first conductive type epitaxial layer (11) are separated by the first medium layer (131), a second conductive type well region (16) is arranged above the first conductive type epitaxial layer (11), and a second conductive type heavily doped region (18) is arranged above the interior of the second conductive type well region (16), a first conductive type heavily doped source region (19) is arranged above the second conductive type well region (16), a hole is punched in the first conductive type heavily doped source region (19) and the second conductive type heavily doped region (18) to lead out metal (20), and the metal (20) and the control gate electrode (15) are separated by a fourth dielectric layer (135).
10. A manufacturing method of a low-grid charge power MOSFET device with a U-shaped separation grid is characterized by comprising the following steps:
1) forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner wall of each groove structure;
2) depositing heavily doped polysilicon in the trench structure to fill the trench with the heavily doped polysilicon;
3) etching the heavily doped polysilicon deposited in the step 2);
4) etching the first dielectric layer, wherein a part of the first dielectric layer is still remained on the inner side wall of the groove structure and is not etched;
5) etching or oxidizing the heavily doped polysilicon after the etching in the step 3) to ensure that the upper surface of the heavily doped polysilicon is not higher than the lower surface of the first dielectric layer after the etching of the first dielectric layer in the step 4);
6) depositing heavily doped polysilicon to make the upper part of the heavily doped polysilicon in a U shape, wherein a gap is still left in the middle of the U shape and is not filled;
7) forming a second dielectric layer in the groove structure without leaving a gap;
8) etching the second dielectric layer, wherein a part of the second dielectric layer is still remained in the U-shaped structure and is not etched;
9) etching the heavily doped polysilicon deposited in the step 6) to form a final U-shaped heavily doped polysilicon structure;
10) forming a third dielectric layer in the groove structure without leaving a gap;
11) etching the first dielectric layer, the second dielectric layer and the third dielectric layer to enable the upper surfaces of the first dielectric layer, the second dielectric layer and the third dielectric layer to be higher than the upper surface of the U-shaped heavily doped polysilicon;
12) forming a gate dielectric layer, depositing and etching heavily doped polysilicon to form a control gate electrode;
13) and forming a second conductive type well region and a first conductive type heavily doped source region, forming a fourth dielectric layer, punching holes in the first conductive type heavily doped source region and the second conductive type well region to form a second conductive type heavily doped region, injecting metal and leading out potential.
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