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CN116137282A - Semiconductor super junction power device - Google Patents

Semiconductor super junction power device Download PDF

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Publication number
CN116137282A
CN116137282A CN202111359631.9A CN202111359631A CN116137282A CN 116137282 A CN116137282 A CN 116137282A CN 202111359631 A CN202111359631 A CN 202111359631A CN 116137282 A CN116137282 A CN 116137282A
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type
body regions
type body
adjacent
power device
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CN202111359631.9A
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Inventor
刘伟
刘磊
袁愿林
王睿
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Suzhou Dongwei Semiconductor Co ltd
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Suzhou Dongwei Semiconductor Co ltd
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Priority to CN202111359631.9A priority Critical patent/CN116137282A/en
Priority to PCT/CN2022/101535 priority patent/WO2023087714A1/en
Publication of CN116137282A publication Critical patent/CN116137282A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Junction Field-Effect Transistors (AREA)

Abstract

The semiconductor super junction power device provided by the embodiment of the invention comprises an n-type drain region, an n-type drift region and a plurality of p-type columns, wherein the width of each p-type column in the plurality of p-type columns is equal, and the interval between two adjacent p-type columns is equal; the top of the p-type column is provided with p-type body regions which are in one-to-one correspondence with the p-type column, n-type source regions are arranged in the p-type body regions, and the widths of the p-type body regions are equal; two gate trenches between two adjacent p-type body regions, the gate trenches having equal widths; at least some of the p-type body regions have their axes of symmetry offset from their axes of symmetry of the corresponding p-type pillars such that the spacing between two gate trenches between adjacent two of the p-type body regions has at least two different spacing values. The invention can reduce the abrupt change speed of the gate-drain capacitance of the semiconductor super junction power device when the semiconductor super junction power device is turned on or turned off, and reduce the grid voltage oscillation of the semiconductor super junction power device.

Description

Semiconductor super junction power device
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a semiconductor super junction power device.
Background
The semiconductor super-junction power device is based on a charge balance technology, so that on-resistance and parasitic capacitance can be reduced, the semiconductor super-junction power device has extremely fast switching characteristics, switching loss can be reduced, and higher power conversion efficiency is realized. When the semiconductor super junction power device in the prior art is turned on and turned off, the gate-drain capacitance (Cgd) is suddenly changed, so that the grid voltage of the semiconductor super junction power device is severely oscillated.
Disclosure of Invention
In view of the above, the present invention is to provide a semiconductor super junction power device to solve the problem of abrupt change of gate-drain capacitance of the semiconductor super junction power device in the prior art.
The embodiment of the invention provides a semiconductor super junction power device, which comprises a terminal area and a cell area, wherein the cell area comprises:
the device comprises an n-type drain region, an n-type drift region and a plurality of p-type columns, wherein the width of each p-type column in the plurality of p-type columns is equal, and the distance between two adjacent p-type columns is equal;
the top of each p-type column in the plurality of p-type columns is respectively provided with a p-type body region corresponding to the p-type column one by one, n-type source regions are arranged in the p-type body regions, and the widths of the p-type body regions are equal;
two gate trenches between two adjacent p-type body regions, wherein the widths of the gate trenches are equal, and a gate dielectric layer and a gate are arranged in the gate trenches;
at least some of the p-type body regions have their axes of symmetry offset from their axes of symmetry of the corresponding p-type pillars such that the spacing between two gate trenches between adjacent two of the p-type body regions has at least two different spacing values.
Optionally, the distance value between two gate trenches between two adjacent p-type body regions is set as follows: C. c+ D, C, C +1D, C, …; or set up in turn as: C. C+1D, …, C+nD, C+ (n-1) D, …, C, C +1D, …, C+nD, C+ (n-1) D, …, C, …; or set up in turn as: C. c, …, c+ D, C +1d, …, c+nd, …, c+ (n-1) D, C + (n-1) D, …, C, C, …, wherein: n is more than or equal to 2, n is an integer, C is a basic spacing value of the spacing between two gate trenches between two adjacent p-type body regions, and C is more than 0; d is the value of the variation in the spacing between two gate trenches between adjacent two of the p-type body regions and D >0.
According to the semiconductor superjunction power device, a double-trench gate structure is adopted between adjacent p-type body regions, and the offset between the symmetry axis of the p-type body regions and the symmetry axis of the corresponding p-type column is regulated, so that the distance between two gate trenches between two adjacent p-type body regions has at least two different distance values, the gate-drain capacitance mutation speed of the semiconductor superjunction power device when the semiconductor superjunction power device is turned on or turned off is reduced, and the gate voltage oscillation of the semiconductor superjunction power device is reduced.
Drawings
In order to more clearly illustrate the technical solution of the exemplary embodiments of the present invention, a brief description is given below of the drawings required for describing the embodiments.
Fig. 1 is a schematic cross-sectional structure of a first embodiment of a semiconductor superjunction power device according to the present invention.
Detailed Description
The technical solutions of the present invention will be fully described below by way of specific modes in connection with the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. Meanwhile, in order to clearly illustrate the specific embodiments of the present invention, the sizes of the figures listed in the drawings are not represented by actual sizes, and the drawings in the description are schematic and should not limit the scope of the present invention.
Fig. 1 is a schematic cross-sectional structure of a first embodiment of a semiconductor superjunction power device according to the present invention, as shown in fig. 1, where the semiconductor superjunction power device according to the embodiment of the present invention includes an n-type drain region 20, and the n-type drain region 20 may be externally connected to a drain voltage through a metal layer. An n-type drift region 21 located above the n-type drain region 20.
A plurality of p-type pillars 22, three p-type pillars 22 being shown in fig. 1 for ease of illustration and description. Each p-type pillar 22 of the plurality of p-type pillars 22 has an equal width and the spacing between two adjacent p-type pillars 22 is equal, and a charge-balanced pn junction structure is formed between the p-type pillar 22 and the adjacent n-type drift region 21.
The top of each p-type pillar 22 of the plurality of p-type pillars 22 is provided with a p-type body region in one-to-one correspondence with the p-type pillar 22, three p-type body regions, p-type body region 23a, p-type body region 23b and p-type body region 23c, are exemplarily shown in fig. 1, and the widths of the p-type body regions are all equal. Within each p-type body region is an n-type source region 24.
The widths of the p-type body regions are set to be equal, so that the layout design sizes of the p-type body regions are identical, the layout design sizes of the n-type source regions are identical, and the design of the semiconductor superjunction power device is simplified.
Two gate trenches between two adjacent p-type body regions, the widths of the gate trenches are equal, a gate dielectric layer 26 and a gate 27 are arranged in the gate trenches, and the gate 27 controls the opening and closing of a current channel between the n-type source region 24 and the n-type drift region 21 through a gate voltage.
The semiconductor super junction power device of the invention has at least partial p-type body regions with the symmetry axes offset from the symmetry axes of the corresponding p-type columns, and the widths of the p-type columns 22 are equal, and the distances between the adjacent p-type columns 22 are equal, and the widths of the p-type body regions are equal, so that the distances between two gate grooves between two adjacent p-type body regions have at least two different distance values. Illustratively, in fig. 1, p- type body regions 23a and 23c are coincident with the symmetry axis of their corresponding p-type pillars 22, and the symmetry axis of p-type body region 23b is offset to the right by a distance b from the symmetry axis of its corresponding p-type pillar 22, thereby providing a spacing between two gate trenches between adjacent two p-type body regions in fig. 1 having two different spacing values of a1 and a2, with a difference of a1 and a2 being 2b.
By setting the offset of one or more p-type body regions, the distance value between two gate trenches between two adjacent p-type body regions can be set as follows: C. c+ D, C, C + D, C, …, namely that the spacing between two gate trenches between at least part of two adjacent p-type body regions has two different spacing values and is sequentially and circularly arranged at intervals; or set up in turn as: C. c+1d, …, c+nd, c+ (n-1) D, …, C, C +1d, …, c+nd, c+ (n-1) D, …, C, …, i.e., the spacing value between two gate trenches between at least a portion of two adjacent p-type body regions increases sequentially and then decreases sequentially and then increases sequentially and then decreases sequentially, thus cycling; or set up in turn as: C. c, …, c+ D, C +1d, …, c+nd, …, c+ (n-1) D, C + (n-1) D, …, C, C, …, i.e., the spacing values between two gate trenches between two adjacent p-type body regions comprise multiple sets of spacing values, the spacing values in the same set of spacing values are the same, the spacing values in different sets of spacing values increase sequentially and decrease sequentially, and so cycle, wherein: n is more than or equal to 2 and n is an integer; c is a basic pitch value of the pitch between two gate trenches between two adjacent p-type body regions and C >0; d is the value of the variation of the spacing between two gate trenches between two adjacent p-type body regions and the specific values of D >0, n, C, D are determined according to the product design requirements. By setting the distance value between two gate grooves between two adjacent p-type body regions, when the semiconductor super junction power device is turned on and turned off, the region with smaller distance value is firstly depleted along with the rising of source-drain voltage, and the gate-drain capacitance is suddenly reduced at the source-drain voltage point; then, as the source-drain voltage further rises, the region with larger spacing value is sequentially depleted, and the gate-drain capacitance is sequentially suddenly reduced at the source-drain voltage points, so that the abrupt points of the gate-drain capacitance of the semiconductor superjunction power device are divided into a plurality of different source-drain voltage points, the abrupt speed of the gate-drain capacitance of the semiconductor superjunction power device is reduced when the semiconductor superjunction power device is turned on and turned off, and the gate voltage oscillation of the semiconductor superjunction power device is reduced.
The above specific embodiments and examples are specific support for the technical idea of the present invention, and the scope of the present invention is not limited thereby, and any equivalent changes or equivalent modifications made on the basis of the technical scheme according to the technical idea of the present invention still belong to the scope of the technical scheme of the present invention.

Claims (2)

1. The semiconductor super junction power device is characterized by comprising a terminal area and a cell area, wherein the cell area comprises:
the device comprises an n-type drain region, an n-type drift region and a plurality of p-type columns, wherein the width of each p-type column in the plurality of p-type columns is equal, and the distance between two adjacent p-type columns is equal;
the top of each p-type column in the plurality of p-type columns is respectively provided with a p-type body region corresponding to the p-type column one by one, n-type source regions are arranged in the p-type body regions, and the widths of the p-type body regions are equal;
two gate trenches between two adjacent p-type body regions, wherein the widths of the gate trenches are equal, and a gate dielectric layer and a gate are arranged in the gate trenches;
at least some of the p-type body regions have their axes of symmetry offset from their axes of symmetry of the corresponding p-type pillars such that the spacing between two gate trenches between adjacent two of the p-type body regions has at least two different spacing values.
2. The semiconductor superjunction power device according to claim 1, wherein the value of the interval between two gate trenches between two adjacent p-type body regions is set to: C. c+ D, C, C +1D, C, …; or set up in turn as: C. C+1D, …, C+nD, C+ (n-1) D, …, C, C +1D, …, C+nD, C+ (n-1) D, …, C, …; or set up in turn as: C. c, …, c+ D, C +1d, …, c+nd, …, c+ (n-1) D, C + (n-1) D, …, C, C, …, wherein: n is more than or equal to 2, n is an integer, C is a basic spacing value of the spacing between two gate trenches between two adjacent p-type body regions, and C is more than 0; d is the value of the variation in the spacing between two gate trenches between adjacent two of the p-type body regions and D >0.
CN202111359631.9A 2021-11-17 2021-11-17 Semiconductor super junction power device Pending CN116137282A (en)

Priority Applications (2)

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CN202111359631.9A CN116137282A (en) 2021-11-17 2021-11-17 Semiconductor super junction power device
PCT/CN2022/101535 WO2023087714A1 (en) 2021-11-17 2022-06-27 Semiconductor super-junction power device

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Application Number Priority Date Filing Date Title
CN202111359631.9A CN116137282A (en) 2021-11-17 2021-11-17 Semiconductor super junction power device

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Publication number Priority date Publication date Assignee Title
JP3731523B2 (en) * 2001-10-17 2006-01-05 富士電機デバイステクノロジー株式会社 Semiconductor element
CN104952928A (en) * 2015-04-30 2015-09-30 苏州东微半导体有限公司 Gate-drain capacitance slow change super-junction power device and manufacturing method thereof
CN105428397B (en) * 2015-11-17 2019-07-02 深圳尚阳通科技有限公司 Superjunction devices and its manufacturing method
CN107464837B (en) * 2017-08-07 2020-07-31 电子科技大学 Super junction power device
CN112447822A (en) * 2019-09-03 2021-03-05 苏州东微半导体股份有限公司 Semiconductor power device

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