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CN116137282A - 半导体超结功率器件 - Google Patents

半导体超结功率器件 Download PDF

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CN116137282A
CN116137282A CN202111359631.9A CN202111359631A CN116137282A CN 116137282 A CN116137282 A CN 116137282A CN 202111359631 A CN202111359631 A CN 202111359631A CN 116137282 A CN116137282 A CN 116137282A
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刘伟
刘磊
袁愿林
王睿
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Suzhou Dongwei Semiconductor Co ltd
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Abstract

本发明实施例提供的一种半导体超结功率器件，包括n型漏区、n型漂移区、多个p型柱，所述多个p型柱中的每个p型柱的宽度相等，且相邻的两个所述p型柱之间的间距相等；所述p型柱的顶部设有与所述p型柱一一对应的p型体区，所述p型体区内设有n型源区，所述p型体区的宽度均相等；介于相邻两个所述p型体区之间的两个栅沟槽，所述栅沟槽的宽度均相等；至少有部分p型体区的对称轴线与其对应的p型柱的对称轴线产生偏移，使得相邻两个所述p型体区之间的两个栅沟槽之间的间距具有至少两种不同的间距值。本发明可以使得半导体超结功率器件在开启或关断时的栅漏电容突变速度降低，减小半导体超结功率器件的栅极电压震荡。

Description

半导体超结功率器件
技术领域
本发明属于半导体功率器件技术领域，特别是涉及一种半导体超结功率器件。
背景技术
半导体超结功率器件是基于电荷平衡技术，可以降低导通电阻和寄生电容，使得半导体超结功率器件具有极快的开关特性，可以降低开关损耗，实现更高的功率转换效率。现有技术的半导体超结功率器件在开启和关断时，栅漏电容(Cgd)会发生突变，这使得半导体超结功率器件的栅极电压震荡严重。
发明内容
有鉴于此，本发明的目的是提供一种半导体超结功率器件，以解决现有技术中的半导体超结功率器件的栅漏电容突变问题。
本发明实施例提供的一种半导体超结功率器件，包括终端区和元胞区，所述元胞区包括：
n型漏区、n型漂移区和多个p型柱，所述多个p型柱中的每个p型柱的宽度相等，且相邻的两个所述p型柱之间的间距相等；
所述多个p型柱中的每个所述p型柱的顶部分别设有与所述p型柱一一对应的p型体区，所述p型体区内设有n型源区，所述p型体区的宽度均相等；
介于相邻两个所述p型体区之间的两个栅沟槽，所述栅沟槽的宽度均相等，所述栅沟槽内设有栅介质层和栅极；
至少有部分p型体区的对称轴线与其对应的p型柱的对称轴线产生偏移，使得相邻两个所述p型体区之间的两个栅沟槽之间的间距具有至少两种不同的间距值。
可选的，相邻两个所述p型体区之间的两个栅沟槽之间的间距值依次设为：C、C+1D、C、C+1D、C、…；或者依次设为：C、C+1D、…、C+nD、C+(n-1)D、…、C、C+1D、…、C+nD、C+(n-1)D、…、C、…；或者依次设为：C、C、…、C+1D、C+1D、…、C+nD、C+nD、…、C+(n-1)D、C+(n-1)D、…、C、C、…，其中：n≥2且n为整数，C为相邻两个所述p型体区之间的两个栅沟槽之间的间距的基本间距值且C>0；D为相邻两个所述p型体区之间的两个栅沟槽之间的间距的变化的值且D>0。
本发明的一种半导体超结功率器件在相邻的p型体区之间采用双沟槽栅极结构，通过调节p型体区的对称轴线与其对应的p型柱的对称轴线的偏移，使得相邻两个所述p型体区之间的两个栅沟槽之间的间距具有至少两种不同的间距值，能够使得半导体超结功率器件在开启或关断时的栅漏电容突变速度降低，减小了半导体超结功率器件的栅极电压震荡。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1是本发明提供的半导体超结功率器件的第一个实施例的剖面结构示意图。
具体实施方式
以下将结合本发明实施例中的附图，通过具体方式，完整地描述本发明的技术方案。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。同时，为清楚地说明本发明的具体实施方式，说明书附图中所列图形大小并不代表实际尺寸，说明书附图是示意性的，不应限定本发明的范围。
图1是本发明提供的半导体超结功率器件的第一个实施例的剖面结构示意图，如图1所示，本发明实施例提供的一种半导体超结功率器件，包括n型漏区20，n型漏区20可以通过金属层外接漏极电压。位于n型漏区20之上的n型漂移区21。
多个p型柱22，为了方便展示和说明，图1中仅示例性的示出了三个p型柱22。多个p型柱22中的每个p型柱22的宽度相等，且相邻的两个p型柱22之间的间距相等，p型柱22与相邻的n型漂移区21之间形成电荷平衡的pn结结构。
多个p型柱22中的每个p型柱22的顶部分别设有与p型柱22一一对应的p型体区，图1中示例性的示出了p型体区23a、p型体区23b和p型体区23c三个p型体区，p型体区的宽度均相等。在每个p型体区内均设有n型源区24。
将每个p型体区的宽度设置为均相等，可以使得每个p型体区的版图设计尺寸均相同，同时每个n型源区的版图设计尺寸也相同，简化半导体超结功率器件的设计。
介于相邻两个p型体区之间的两个栅沟槽，所述栅沟槽的宽度均相等，所述栅沟槽内设有栅介质层26和栅极27，栅极27通常通过栅极电压来控制n型源区24与n型漂移区21之间的电流沟道的开启和关断。
本发明的半导体超结功率器件，至少有部分p型体区的对称轴线与其对应的p型柱的对称轴线产生偏移，由于多个p型柱22中的每个p型柱22的宽度相等，且相邻的p型柱22之间的间距相等，同时p型体区的宽度均相等，这使得相邻两个p型体区之间的两个栅沟槽之间的间距具有至少两种不同的间距值。示例性的，图1中，p型体区23a和p型体区23c与其对应的p型柱22的对称轴线重合，p型体区23b的对称轴线与其对应的p型柱22的对称轴线向右偏移距离b，由此，使得图1中的相邻两个p型体区之间的两个栅沟槽之间的间距具有a1和a2两种不同的间距值，a1与a2的差为2b。
通过设定一个或多个p型体区的偏移，可以使得相邻两个p型体区之间的两个栅沟槽之间的间距值依次设为：C、C+1D、C、C+1D、C、…，即至少部分相邻两个p型体区之间的两个栅沟槽之间的间距具有两种不同的间距值，并依次间隔循环设置；或者依次设为：C、C+1D、…、C+nD、C+(n-1)D、…、C、C+1D、…、C+nD、C+(n-1)D、…、C、…，即至少部分相邻两个p型体区之间的两个栅沟槽之间的间距值先依次增大，再依次减小，再依次增大，再依次减小，如此循环；或者依次设为：C、C、…、C+1D、C+1D、…、C+nD、C+nD、…、C+(n-1)D、C+(n-1)D、…、C、C、…，即相邻两个p型体区之间的两个栅沟槽之间的间距值包括多组间距值组，同一间距值组中的间距值相同，不同间距值组中的间距值先依次增大，再依次减小，如此循环，其中：n≥2且n为整数；C为相邻两个p型体区之间的两个栅沟槽之间的间距的基本间距值且C>0；D为相邻两个p型体区之间的两个栅沟槽之间的间距的变化的值且D>0，n、C、D的具体数值依据产品设计要求确定。通过设置不同的相邻两个p型体区之间的两个栅沟槽之间的间距值，半导体超结功率器件在开启和关断时，随着源漏电压的上升，间距值较小的区域会被先耗尽，栅漏电容会在这个源漏电压点突然下降；然后，随着源漏电压的进一步上升，间距值较大的区域会被依次耗尽，栅漏电容会在这些源漏电压点依次突然下降，从而，半导体超结功率器件的栅漏电容的突变点被分到几个不同的源漏电压点上，这使得半导体超结功率器件在开启和关断时的栅漏电容突变速度降低，减小了半导体超结功率器件的栅极电压震荡。
以上具体实施方式及实施例是对本发明的技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。

Claims (2)

1.半导体超结功率器件，其特征在于，包括终端区和元胞区，所述元胞区包括：
n型漏区、n型漂移区和多个p型柱，所述多个p型柱中的每个p型柱的宽度相等，且相邻的两个所述p型柱之间的间距相等；
所述多个p型柱中的每个所述p型柱的顶部分别设有与所述p型柱一一对应的p型体区，所述p型体区内设有n型源区，所述p型体区的宽度均相等；
介于相邻两个所述p型体区之间的两个栅沟槽，所述栅沟槽的宽度均相等，所述栅沟槽内设有栅介质层和栅极；
至少有部分p型体区的对称轴线与其对应的p型柱的对称轴线产生偏移，使得相邻两个所述p型体区之间的两个栅沟槽之间的间距具有至少两种不同的间距值。
2.根据权利要求1所述的半导体超结功率器件，其特征在于，相邻两个所述p型体区之间的两个栅沟槽之间的间距值依次设为：C、C+1D、C、C+1D、C、…；或者依次设为：C、C+1D、…、C+nD、C+(n-1)D、…、C、C+1D、…、C+nD、C+(n-1)D、…、C、…；或者依次设为：C、C、…、C+1D、C+1D、…、C+nD、C+nD、…、C+(n-1)D、C+(n-1)D、…、C、C、…，其中：n≥2且n为整数，C为相邻两个所述p型体区之间的两个栅沟槽之间的间距的基本间距值且C>0；D为相邻两个所述p型体区之间的两个栅沟槽之间的间距的变化的值且D>0。
CN202111359631.9A 2021-11-17 2021-11-17 半导体超结功率器件 Pending CN116137282A (zh)

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