CN115811448B - AXI bus and EMIF bus time sequence conversion connection method - Google Patents
AXI bus and EMIF bus time sequence conversion connection method Download PDFInfo
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Abstract
The application provides a method for converting and connecting AXI bus and EMIF bus time sequence, which comprises the steps of firstly defining control logic of the EMIF bus, selecting specific AXI bus signals, supplementing internal intermediate logic signals for the two signals, and carrying out logic and time sequence bonding to realize stable and reliable data transmission of two different data interfaces. By the method, reliable conversion of logic and time sequence between the AXI bus and the EMIF bus can be realized.
Description
Technical Field
The application relates to the technical field of bus interface time sequence control in an aerospace system, in particular to a method for converting and connecting AXI bus and EMIF bus time sequence.
Background
For most fully programmable logic devices (APSOC), ARM is used as its hard core processor. The internal bus of the device thus employs the AXI bus of the ARM architecture. However, for special asynchronous buses such as 1553B buses, the research and development time is early, the technology is relatively stable, the updating is slow, and the external interface is a slow asynchronous parallel bus EMIF logic. In order to enable 1553B bus time sequence to run stably and reliably under APSOC device application environment, an AXI bus and EMIF bus time sequence conversion connection method is designed, and the problem that the AXI bus time sequence is not matched with the EMIF bus time sequence can be effectively solved. And the DSP processor is adopted to communicate with the protocol chip for 1553B buses at home and abroad. Because the DSP itself has an EMIF bus interface, the configuration can be effectively configured to communicate with the 1553B bus. As there is no such demanding application.
Disclosure of Invention
In order to solve the above technical problems, the present application is directed to a method for converting and connecting AXI bus and EMIF bus time sequences, which can realize reliable logic and time sequence conversion between AXI bus and EMIF bus. The technical scheme adopted by the application is as follows:
An AXI bus and EMIF bus timing conversion connection method, the connection method comprising:
step 1, determining control logic of an EMIF bus;
step 2, selecting a specific signal interface from an AXI bus;
step 3, supplementing internal intermediate logic of the EMIF bus and the AXI bus, and performing logic and time sequence bonding;
and 4, realizing data transmission between the EMIF bus and the AXI bus.
Further, in step 2, the specific signal interface of the AXI bus comprises S_AXI_RDATA、S_AXI_WDATA、S_AXI_ARVALID、S_AXI_RREADY、S_AXI_AWVALID、S_AXI_WVALID、S_AXI_AWADDR、S_AXI_ARADDR.
Further, in step 3, logic and timing bonding is performed, including:
directly connecting the DATA_IN of the EMIF bus to the S_AXI_RDATA of the AXI bus for DATA input of the EMIF bus;
Directly connecting the DATA_OUT of the EMIF bus to the S_AXI_WDATA of the AXI bus for DATA output of the EMIF bus;
Further, in step 3, logic and timing bonding is performed, which further includes: the internal signals b of the AXI buses after the s_axi_ ARVALID and the s_axi_ RREADY are delayed by 50ns and then are low, and when the internal signal a rises, the delayed internal signal b and the internal signal a are simultaneously high to be used as an EMIF bus read enable signal RDn.
Further, in step 3, logic and timing bonding is performed, which further includes: and delaying the internal signals c of the AXI buses, which are the S_AXI_ AWVALID and the S_AXI_WVALID after the internal signals c are subjected to NAND logic c, for 50ns to be low, and setting the delayed internal signals c and the internal signals a to be high simultaneously when the internal signals a rise, so as to be used as an EMIF bus write enable signal WEn.
Further, in step 3, logic and timing bonding is performed, which further includes: the signal generated by the or logic of the internal signal b and the internal signal c after the internal signal b is not logically used as the EMIF bus read/write determination signal RnW.
Further, in step 3, logic and timing bonding is performed, which further includes: the internal signal d is obtained by AND logic of the S_AXI_ AWVALID and the S_AXI_WVALID of the AXI bus, the internal signal e is obtained by AND logic of the S_AXI_ ARVALID and the S_AXI_ RREADY of the AXI bus, and the signals obtained by nor logic of the internal signal d and the internal signal e are used as the EMIF bus strobe signal CSn.
Further, in step 3, logic and timing bonding is performed, which further includes: judging the signal state of the EMIF bus read-write judging signal RnW, if the signal state is high, connecting the S_AXI_ AWADDR of the AXI bus to the ADDR of the EMIF bus to be used as an address bus signal of the EMIF bus; if the signal state is low, then S_AXI_ ARADDR of the AXI bus is connected to ADDR of the EMIF bus to be used as an address bus signal of the EMIF bus.
Further, in step 3, logic and timing bonding is performed, which further includes: the input READY signal of the EMIF bus is forcibly pulled down by 260ns and then used as the internal signal a.
Further, the internal intermediate logic includes nand logic, and logic, nor logic, or logic, nor logic.
By the embodiment of the application, the following technical effects can be obtained:
(1) The method can realize the time sequence and logic butt joint of signals in the AXI bus and the EMIF bus; the ARM-based communication module can be used as an independent IP core and applied to communication between a programmable logic device based on ARM and a 1553B bus protocol chip; the interface logic can be used for the IP core communication of the ARM-based programmable logic device on the EMIF-based slow asynchronous storage logic;
(2) The input READY signal of the EMIF bus is forced to be pulled down for 260ns after receiving the falling edge time sequence; the RDn signal of the EMIF bus consists of NAND logic of S_AXI_ ARVALID and S_AXI_ RREADY, and the delay is set to be 50ns; the WEn signal of the EMIF bus consists of nand logic of s_axi_ AWVALID and s_axi_wvalid, with a low latency of 50ns.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a functional block diagram of the timing logic matching of an AXI bus to an EMIF bus;
FIG. 2 is a topology of DATA bus DATA_IN and S_AXI_RDATA connections;
FIG. 3 is a topology diagram of the connection of the DATA buses DATA_OUT and S_AXI_WDATA;
FIG. 4 is a schematic diagram of READY and RDn signals, WEn signal connections of the EMIF bus;
FIG. 5 is a topology diagram of the RDn signal of the EMIF bus and the internal signals a, S_AXI_RREADY and S_AXI_ ARVALID of the AXI bus;
FIG. 6 is a topology diagram of the connection of the WEn signal of the EMIF bus with the internal signal a, the S_AXI_WVVALID of the AXI bus, and the S_AXI_ AWVALID signal;
FIG. 7 is a topology diagram of the RnW signal of the EMIF bus and the S_AXI_RREADY, S_AXI_WVVALID, S_AXI_AWVALID, S_AXI_ ARVALID signals of the AXI bus;
FIG. 8 is a topology diagram of the CSn signal of the EMIF bus and the S_AXI_RREADY, S_AXI_WVVALID, S_AXI_AWALID, S_AXI_ ARVALID signals of the AXI bus;
FIG. 9 is a topology diagram of the connection of the ADDR signal of the EMIF bus with the RnW signal, S_AXI_AWADR, S_AXI_ ARADDR signals of the EMIF bus.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
FIG. 1 is a functional block diagram of the timing logic matching of an AXI bus and an EMIF bus. The connection method comprises the following steps:
step 1, determining control logic of an EMIF bus;
step 2, selecting a specific signal interface from an AXI bus;
step 3, supplementing internal intermediate logic of the EMIF bus and the AXI bus, and performing logic and time sequence bonding;
and 4, realizing data transmission between the EMIF bus and the AXI bus.
In step 2, the specific signal interface of the AXI bus comprises S_AXI_RDATA、S_AXI_WDATA、S_AXI_ARVALID、S_AXI_RREADY、S_AXI_AWVALID、S_AXI_WVALID、S_AXI_AWADDR、S_AXI_ARADDR;
In step 3, logic and timing bonding is performed, including:
The input READY signal of the EMIF bus is forced to be pulled down for 260ns, and then the input READY signal is used as an internal signal a;
directly connecting the DATA_IN of the EMIF bus to the S_AXI_RDATA of the AXI bus for DATA input of the EMIF bus;
Directly connecting the DATA_OUT of the EMIF bus to the S_AXI_WDATA of the AXI bus for DATA output of the EMIF bus;
delaying the internal signals b of the AXI buses, which are S_AXI_ ARVALID and S_AXI_ RREADY after the internal signals b are subjected to NAND logic b, for 50ns, and setting the delayed internal signals b and the internal signals a to be high simultaneously when the internal signals a rise, and using the delayed internal signals b and the internal signals a as EMIF bus read enable signals RDn;
delaying the internal signals c of the AXI buses, which are S_AXI_ AWVALID and S_AXI_WVALID after the internal signals c are subjected to NAND logic c, for 50ns, and then setting the delayed internal signals c and the internal signals a to be high simultaneously when the internal signals a rise, and using the delayed internal signals c and the internal signals a as an EMIF bus write enable signal WEn;
The signal generated by the OR logic of the internal signal b and the internal signal c after the internal signal b is not logically used as an EMIF bus read-write judgment signal RnW;
The method comprises the steps of obtaining an internal signal d after an AND logic is carried out on an S_AXI_ AWVALID and an S_AXI_WVALID of an AXI bus, obtaining an internal signal e after an AND logic is carried out on an S_AXI_ ARVALID and an S_AXI_ RREADY of the AXI bus, and using signals obtained after an NOR logic is carried out on the internal signal d and the internal signal e as an EMIF bus strobe signal CSn;
Judging the signal state of the EMIF bus read-write judging signal RnW, if the signal state is high, connecting the S_AXI_ AWADDR of the AXI bus to the ADDR of the EMIF bus to be used as an address bus signal of the EMIF bus; if the signal state is low, then S_AXI_ ARADDR of the AXI bus is connected to ADDR of the EMIF bus to be used as an address bus signal of the EMIF bus.
Fig. 2 is a topology diagram of connection between DATA bus data_in of the EMIF bus and s_axi_rdata of the AXI bus according to the present application. The AXI bus s_axi_rdata signal (2) is directly connected to the EMFI bus data_in signal (29).
Fig. 3 is a topology diagram of connection between the DATA bus data_out of the EMIF bus and the s_axi_wdata of the AXI bus according to the present application. The AXI bus s_axi_wdata signal (3) is directly connected to the EMFI bus data_out signal (30).
Fig. 4 is a topology diagram of READY of the EMIF bus and RDn signal and WEn signal connection of the EMIF bus provided by the present application. After the EMFI bus READY signal (28) detects a falling edge, a forced pull-down operation of 260ns (19) is performed, and the signal after the operation is performed is defined as an internal signal a (20). The internal signal b (15) performs a delay operation of 50ns (21), and outputs a high level (26) when the internal signal a rises, and outputs the signal as an EMFI bus RDn signal (31); similarly, the internal signal c (16) performs a delay operation of 50ns (22), and outputs a high level (27) when the internal signal a rises, as an EMFI bus WEn signal (32).
Fig. 5 is a topology diagram of the connection of RDn signals of the EMIF bus with internal signals a and s_axi_rready and s_axi_ ARVALID signals of AXI bus. The AXI bus s_axi_ RREADY signal (1) and AXI bus s_axi_ ARVALID signal (6) perform nand logic (9), define the signals as an internal signal b (15), perform a delay 50ns (21) operation on the internal signal b (15), and output a high level (26) when the internal signal a rises, as an EMFI bus RDn signal (31).
Fig. 6 is a topology diagram of connection between WEn signal and internal signal a of the EMIF bus and s_axi_wvvalid and s_axi_ AWVALID signal of AXI bus according to the present application. The AXI bus s_axi_wvalid signal (4) and AXI bus s_axi_ AWVALID signal (5) perform nand logic (10), define the signals as an internal signal c (16), perform a delay 50ns (22) operation on the internal signal c (16), and output a high level (27) when the internal signal a rises, as an EMFI bus WEn signal (32).
Fig. 7 is a topology diagram of the connection of RnW signals from the EMIF bus to the s_axi_rready, s_axi_wvvalid, s_axi_awvalid, s_axi_ ARVALID signals from the AXI bus. The AXI bus s_axi_ RREADY signal (1) and AXI bus s_axi_ ARVALID signal (6) perform nand logic (9), which is defined as internal signal b (15). The axibus s_axi_wvalid signal (4) and axibus s_axi_ AWVALID signal (5) perform nand logic (10), defining this signal as an internal signal c (16). After the internal signal b (15) performs the NOT logic (23), and the internal signal c (16) performs the OR logic (24), the signal is taken as an EMFI bus RnW signal (33).
Fig. 8 is a topology diagram of the connection of CSn signals of the EMIF bus and s_axi_rready, s_axi_wvvalid, s_axi_awvalid, s_axi_ ARVALID signals of the AXI bus provided by the present application. The axibus s_axi_ RREADY signal (1) and the axibus s_axi_ ARVALID signal (6) execute and logic (12), defining this signal as internal signal e (18); the axibus s_axi_wvalid signal (4) and the axibus s_axi_ AWVALID signal (5) perform and logic (11), which is defined as internal signal d (17). The internal signal d (17) and the internal signal e (18) perform nor logic (25), which is referred to as an EMFI bus CSn signal (34).
FIG. 9 is a diagram showing the topology of the connection of the ADDR signal of the EMIF bus with the RnW signal, S_AXI_AWADR, S_AXI_ ARADDR signal of the EMIF bus. When the EMFI bus RnW signal (33) signal is "high" (13), the AXI bus S_AXI_ AWADDR signal (7) is used as the EMIF bus ADDR signal (35); when the EMFI bus RnW signal (33) signal is "low" (14), the AXI bus S_AXI_ ARADDR signal (8) is used as the EMIF bus ADDR signal (35).
In summary, because the AXI bus includes a plurality of signals, the timing is complex; meanwhile, the EMIF bus has time sequence constraint, the application firstly definitely determines the control logic of the EMIF bus, simultaneously selects specific AXI bus signals, supplements internal intermediate logic signals for the two signals, carries out logic and time sequence bonding, realizes the matching of the AXI bus and the EMIF bus time sequence, and can finish the data receiving and transmitting of the two standard buses in the mode.
While specific embodiments of the application have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and the scope of the application is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the application, but such changes and modifications fall within the scope of the application.
Claims (2)
1. An AXI bus and EMIF bus time sequence conversion connection method is characterized in that the connection method comprises the following steps:
step 1, determining control logic of an EMIF bus;
step 2, selecting a specific signal interface from an AXI bus;
step 3, supplementing internal intermediate logic of the EMIF bus and the AXI bus, and performing logic and time sequence bonding;
Step 4, realizing data transmission between the EMIF bus and the AXI bus;
in step 2, the specific signal interface of the AXI bus comprises S_AXI_RDATA、S_AXI_WDATA、S_AXI_ARVALID、S_AXI_RREADY、S_AXI_AWVALID、S_AXI_WVALID、S_AXI_AWADDR、S_AXI_ARADDR;
In step 3, logic and timing bonding is performed, including:
directly connecting the DATA_IN of the EMIF bus to the S_AXI_RDATA of the AXI bus for DATA input of the EMIF bus;
Directly connecting the DATA_OUT of the EMIF bus to the S_AXI_WDATA of the AXI bus for DATA output of the EMIF bus;
in step 3, logic and timing bonding is performed, further comprising: delaying the internal signals b of the AXI buses, which are S_AXI_ ARVALID and S_AXI_ RREADY after the internal signals b are subjected to NAND logic b, for 50ns, and setting the delayed internal signals b and the internal signals a to be high simultaneously when the internal signals a rise, and using the delayed internal signals b and the internal signals a as EMIF bus read enable signals RDn;
In step 3, logic and timing bonding is performed, further comprising: delaying the internal signals c of the AXI buses, which are S_AXI_ AWVALID and S_AXI_WVALID after the internal signals c are subjected to NAND logic c, for 50ns, and then setting the delayed internal signals c and the internal signals a to be high simultaneously when the internal signals a rise, and using the delayed internal signals c and the internal signals a as an EMIF bus write enable signal WEn;
in step 3, logic and timing bonding is performed, further comprising: the signal generated by the OR logic of the internal signal b and the internal signal c after the internal signal b is not logically used as an EMIF bus read-write judgment signal RnW;
In step 3, logic and timing bonding is performed, further comprising: the method comprises the steps of obtaining an internal signal d after an AND logic is carried out on an S_AXI_ AWVALID and an S_AXI_WVALID of an AXI bus, obtaining an internal signal e after an AND logic is carried out on an S_AXI_ ARVALID and an S_AXI_ RREADY of the AXI bus, and using signals obtained after an NOR logic is carried out on the internal signal d and the internal signal e as an EMIF bus strobe signal CSn;
In step 3, logic and timing bonding is performed, further comprising: judging the signal state of the EMIF bus read-write judging signal RnW, if the signal state is high, connecting the S_AXI_ AWADDR of the AXI bus to the ADDR of the EMIF bus to be used as an address bus signal of the EMIF bus; if the signal state is low, connecting S_AXI_ ARADDR of the AXI bus to ADDR of the EMIF bus to be used as an address bus signal of the EMIF bus;
In step 3, logic and timing bonding is performed, further comprising: the input READY signal of the EMIF bus is forcibly pulled down by 260ns and then used as the internal signal a.
2. The method of claim 1, wherein the internal intermediate logic comprises nand logic, and logic, nor logic, or logic, nor logic.
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| GB2176976A (en) * | 1985-06-15 | 1987-01-07 | Gen Electric Co Plc | A data bus system |
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| CN104750644B (en) * | 2015-04-20 | 2017-11-03 | 哈尔滨工业大学 | The conversion method of DSP EMIF read-write sequences and FPGA AVALON read-write sequences |
| CN205028284U (en) * | 2015-09-24 | 2016-02-10 | 北京精密机电控制设备研究所 | Interface converting circuit of harvard structure bus and multiplex bus |
| US10216669B2 (en) * | 2016-02-23 | 2019-02-26 | Honeywell International Inc. | Bus bridge for translating requests between a module bus and an axi bus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| GB2176976A (en) * | 1985-06-15 | 1987-01-07 | Gen Electric Co Plc | A data bus system |
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