CN205028284U - Interface converting circuit of harvard structure bus and multiplex bus - Google Patents

Abstract

An interface conversion circuit between a Harvard structure bus and a multiplexing bus. When data interaction between the two buses is required, the utility model is based on the time difference between the valid DSP chip selection signal and the valid read and write signal, that is, the time of the DSP establishment stage The length is used as the effective duration of the address latch of the multiplexed bus, that is, the write address stage of the multiplexed bus; the logical relationship of the read and write signals of the DSP is used to generate the chip selection signal of the multiplexed bus, and the read and write signals of the DSP are respectively used as the multiplexed bus Use the read and write signals of the bus; adopt the bus switching switch design scheme, connect the address bus of the DSP to the multiplex bus in the stage of writing the address of the multiplex bus, and connect the data bus of the DSP to the multiplex bus in the stage of reading and writing data of the multiplex bus Multiplexing bus connection; in this way, in a read-write cycle of DSP, in the setup phase, the address signal is written into the multiplexed bus, and in the activation and hold phases, data interaction is performed, and DSP completes it in one read-write cycle Operations on multiplexed buses.

Description

A kind of interface conversion circuit between Harvard structure bus and multiplexing bus

technical field

The utility model relates to an interface conversion circuit between a Harvard structure bus and a multiplexing bus, which is used for data interactive transmission between a DSP processor based on the Harvard structure and a digital device using a multiplexing bus, and belongs to the technical field of electrical communication.

Background technique

Mainstream DSP processors mostly adopt Harvard structure, and its external parallel data interface adopts independent interface of address bus and data bus. A type of digital device with a limited number of pins uses a multiplexed bus interface, that is, address and data signals are transmitted on a bus in time division, such as CAN bus interface chips, clock management chips, etc. When designing an embedded system based on a DSP processor, it is often necessary to perform data interaction, register configuration, and other work with the digital devices of the multiplexing bus.

Existing DSP and the method for multiplexed bus interface mainly divide two kinds, a kind of is to adopt the GPIO (general purpose input and output) of DSP and multiplexed bus direct interface, operate GPIO in DSP software to simulate the read and write sequence of multiplexed bus, Realize data interaction; the second is to use the DSP data bus to directly connect with the multiplexing bus, use the DSP address bus to generate the chip selection signal of the multiplexing bus device through the programmable logic device, and write the data bus to the data bus first in the DSP software Use the address of the bus, and then read and write data to the multiplexed bus to complete data interaction.

The shortcoming that prior art exists is: DSP processor has provided online emulation function, can check the internal data and the register situation of the external digital device of DSP internal memory and the external digital device of parallel interface with DSP in real time by compiling software, but real-time checking function is based on address, If the data is independent of the bus, the above two methods cannot be used for real-time viewing of multiplexed bus devices; in addition, to complete a data read and write for DSP, multiple statements need to be used in the software to simulate the timing of the multiplexed bus, which improves the data transmission time. , which reduces the real-time performance, and the software code is more complex and cumbersome.

Contents of the invention

The problem solved by the technology of the present invention is: to overcome the deficiencies of the prior art, and to provide an interface conversion circuit between a Harvard structured bus and a multiplexed bus, which uses a hardware circuit to directly match the timing of the two bus interfaces.

Technical solution of the present invention is:

An interface conversion circuit between a Harvard structure bus and a multiplexing bus, characterized in that it comprises: a first buffer BF1, a second buffer BF2, a first AND gate AG1, a second AND gate AG2, a third AND gate AG3, The fourth AND gate AG4, the fifth AND gate AG5, the first NOT gate NG1, the second NOT gate NG2, the third NOT gate NG3, the fourth NOT gate NG4, the first OR gate OG1, the second OR gate OG2, the first NOT gate Tri-state buffer TSB1, second tri-state buffer TSB2, third tri-state buffer TSB3, fourth tri-state buffer TSB4 and data selector MUX;

The read signal cpu_rd of the DSP is input to the input end of the first buffer BF1, and the output end of the first buffer BF1 is output as the read signal can_rd of the multiplexing bus; the input end of the first buffer BF1 is also connected with the first AND gate AG1 one input connected together;

The write signal cpu_we of the DSP is input to the input end of the second buffer BF2, and the output end of the second buffer BF2 is output as the write signal can_wr of the multiplexing bus; the input end of the second buffer BF2 is also connected with the first AND gate AG1 The other inputs are connected together;

The output signal of the first AND gate AG1 is output as the chip select signal can_cs of the multiplexing bus, and at the same time, the output signal of the first AND gate AG1 is also used as an input signal of the second AND gate AG2;

The chip select signal cpu_ce of the DSP external storage space is connected to the other input end of the second AND gate AG2 after being reversed by the first NOT gate NG1, and the output signal of the second AND gate AG2 is connected to the data selection end of the data selector MUX At the same time, the output signal of the second AND gate AG2 is also output as the address latch signal can_ale of the multiplexing bus, and the output signal of the second AND gate AG2 is reversed by the second NOT gate NG2 and then connected to one of the third AND gate AG3 input terminal;

The address bus cpu_addr of the DSP is connected to an input end of the data selector MUX, the data bus cpu_data of the DSP is connected to the other input end of the data selector MUX through the first tri-state buffer TSB1, and the output signal of the data selector MUX passes through the first three-state buffer TSB1. The three-state buffer TSB3 is connected to the multiplexing bus can_data;

The multiplexing bus can_data is sequentially connected to the data bus cpu_data of the DSP through the fourth tri-state buffer TSB4 and the second tri-state buffer TSB2;

The two input ends of the first OR gate OG1 are respectively connected to the chip select signal cpu_ce of the DSP external storage space and the output enable signal cpu_aoe of the DSP, and the output end of the first OR gate OG1 is connected to the enabling of the first tri-state buffer TSB1 At the same time, the output terminal of the first OR gate OG1 is also connected to the enable terminal of the second tri-state buffer TSB2 through the third NOT gate NG3,

The output end of the third NOT gate NG3 is connected to an input end of the third AND gate AG3 and an input end of the fourth AND gate AG4 at the same time, and the output end of the third AND gate AG3 is connected to the enabler of the fourth tri-state buffer TSB4 Capable end;

The output signal of the second AND gate AG2 is used as an input signal of the fourth AND gate AG4, and the output end of the fourth AND gate AG4 is connected to an input end of the second OR gate OG2;

The output enable signal cpu_aoe of the DSP is connected to one input terminal of the fifth AND gate AG5, and the chip select signal cpu_ce of the DSP external storage space is connected to the other input terminal of the fifth AND gate AG5 after passing through the fourth NOT gate NG4, and the fifth The output terminal of the AND gate AG5 is connected to the other input terminal of the second OR gate OG2; the output terminal of the second OR gate OG2 is connected to the enable terminal of the third tri-state buffer TSB3.

The beneficial effect of the present invention compared with prior art is:

The interface conversion circuit of the present invention can enable the DSP based on the Harvard structure to complete the data access to the multiplexed bus digital device in a read-write cycle in an addressing manner, so as to improve the real-time performance of the software, reduce the complexity of the code, and realize the simulation in the simulation. Real-time viewing of multiplexed bus digital device memory data purposes in the environment.

Description of drawings

Fig. 1 is the circuit schematic diagram of the present invention;

Fig. 2 is a DSP read multiplexing bus test diagram;

Figure 3 is a test diagram of the DSP write multiplexing bus.

detailed description

The utility model relates to an interface conversion circuit of a Harvard structure bus (address bus and data bus are independent of each other) and a multiplexing bus (address bus and data bus are time-division multiplexed), which is used for DSP processors based on Harvard structure and adopting multiplexing Use the digital devices of the bus for data interactive transmission.

As shown in Figure 1, the utility model provides an interface conversion circuit between a Harvard structure bus and a multiplexing bus, including: a first buffer BF1, a second buffer BF2, a first AND gate AG1, and a second AND gate AG2 , the third AND gate AG3, the fourth AND gate AG4, the fifth AND gate AG5, the first NOT gate NG1, the second NOT gate NG2, the third NOT gate NG3, the fourth NOT gate NG4, the first OR gate OG1, the Two OR gate OG2, first tri-state buffer TSB1, second tri-state buffer TSB2, third tri-state buffer TSB3, fourth tri-state buffer TSB4 and data selector MUX;

Circuit interface includes DSP external memory interface and multiplexing bus interface.

The external memory interface of DSP includes chip select signal, output enable signal, read signal, write signal, address bus signal and data bus signal;

cpu_aoe is the output enable signal of DSP, which is low level during DSP read operation and high level during write operation, and is valid during the establishment stage of reading and writing from DSP;

cpu_data is the data bus of DSP;

cpu_addr is the address bus of DSP;

cpu_ce is the chip select signal of DSP external storage space, it is low level when DSP is reading and writing, and it is valid in the establishment stage of reading and writing from DSP;

cpu_rd is the read signal of DSP, when DSP is read, it is low level, and the activation phase of reading and writing from DSP is valid (difference from cpu_aoe signal);

cpu_we is the write signal of DSP, which is low level during DSP write operation, and the activation phase of reading and writing from DSP is valid;

The multiplexed bus interface includes chip select signal, address latch signal, read signal, write signal, address and data multiplexed bus signal;

can_data is a multiplexed bus;

can_ale is the address latch signal of the multiplexing bus;

can_cs is the chip select signal of the multiplexing bus;

can_rd is the read signal of the multiplexed bus;

can_wr is the write signal of the multiplexing bus.

The read signal cpu_rd of the DSP is input to the input end of the first buffer BF1, and the output end of the first buffer BF1 is output as the read signal can_rd of the multiplexing bus; the input end of the first buffer BF1 is also connected with the first AND gate AG1 one input connected together;

The write signal cpu_we of the DSP is input to the input end of the second buffer BF2, and the output end of the second buffer BF2 is output as the write signal can_wr of the multiplexing bus; the input end of the second buffer BF2 is also connected with the first AND gate AG1 The other inputs are connected together;

The output signal of the first AND gate AG1 is output as the chip select signal can_cs of the multiplexing bus, that is, the multiplexing bus interface is gated during the DSP read or write operation, and at the same time, the output signal of the first AND gate AG1 is also used as the second AND an input signal of gate AG2;

The chip select signal cpu_ce of the DSP external storage space is connected to the other input end of the second AND gate AG2 after being reversed by the first NOT gate NG1, and the output signal of the second AND gate AG2 is connected to the data selection end of the data selector MUX , at the same time, the output signal of the second AND gate AG2 is also output as the address latch signal can_ale of the multiplexing bus, that is, the address is latched in the establishment stage of DSP reading and writing, and the data is latched in the activation stage. The output of the second AND gate AG2 The signal is connected to an input end of the third AND gate AG3 after being reversed by the second NOT gate NG2;

The address bus cpu_addr of the DSP is connected to an input end of the data selector MUX, the data bus cpu_data of the DSP is connected to the other input end of the data selector MUX through the first tri-state buffer TSB1, and the output signal of the data selector MUX passes through the first three-state buffer TSB1. The three-state buffer TSB3 is connected to the multiplexing bus can_data;

The multiplexing bus can_data is sequentially connected to the data bus cpu_data of the DSP through the fourth tri-state buffer TSB4 and the second tri-state buffer TSB2;

The two input ends of the first OR gate OG1 are respectively connected to the chip select signal cpu_ce of the DSP external storage space and the output enable signal cpu_aoe of the DSP, and the output end of the first OR gate OG1 is connected to the enabling of the first tri-state buffer TSB1 At the same time, the output terminal of the first OR gate OG1 is also connected to the enable terminal of the second tri-state buffer TSB2 through the third NOT gate NG3,

The output end of the third NOT gate NG3 is connected to an input end of the third AND gate AG3 and an input end of the fourth AND gate AG4 at the same time, and the output end of the third AND gate AG3 is connected to the enabler of the fourth tri-state buffer TSB4 Capable end;

The output signal of the second AND gate AG2 is used as an input signal of the fourth AND gate AG4, and the output end of the fourth AND gate AG4 is connected to an input end of the second OR gate OG2;

The output enable signal cpu_aoe of the DSP is connected to one input terminal of the fifth AND gate AG5, and the chip select signal cpu_ce of the DSP external storage space is connected to the other input terminal of the fifth AND gate AG5 after passing through the fourth NOT gate NG4, and the fifth The output terminal of the AND gate AG5 is connected to the other input terminal of the second OR gate OG2; the output terminal of the second OR gate OG2 is connected to the enable terminal of the third tri-state buffer TSB3.

Through the circuit of the utility model, the three stages of the DSP read and write sequence are mapped to two stages of the multiplexing bus sequence, and the time-division multiplexing of the address bus and the data bus of the DSP to the multiplexing bus is completed by the data selector, so as to achieve The data interaction with the multiplexing bus is completed within one read and write cycle of the DSP.

The sequence of read and write operations of the external memory interface of DSP includes three phases, which are the establishment, activation and maintenance phases. In the establishment phase, the DSP enables chip selection, the address is valid, and the output enable signal is valid; in the activation phase, for the read operation, the read signal is pulled low, and the data is required to be valid one clock cycle before the end of the activation phase. For the write operation, the write signal is pulled Low, and the data bus is valid, and lasts until the end of the hold phase; after the hold phase is over, the address bus and data bus are released, the chip select, output enable, and read and write signals return to the disabled state; a read and write operation is completed.

The read and write operation of the multiplexed bus interface includes two stages, which are the write address stage and the read and write data stage. In the address writing stage, the address latch signal is pulled high, and the address signal is written through the multiplexed bus; in the read and write data stage, the address latch signal is pulled low, the chip select signal is pulled low, the read or write signal is pulled low, and the address signal is read from the multiplexed bus. Read data or write data to the multiplexing bus, the read or write signal is pulled high, the chip select signal is pulled high, and the address latch signal is pulled high; a read and write operation is completed.

The utility model adopts the following scheme to realize the timing conversion of the two bus interfaces: according to the time difference between the validity of the DSP chip selection signal and the validity of the read-write signal, that is, the duration of the DSP establishment stage is used as the effective duration of the address latch of the multiplexing bus, that is, multiplexing The write address stage of the bus; the logical relationship of the read and write signals of DSP is used to generate, as the chip selection signal of the multiplexed bus, the read and write signals of the DSP are respectively used as the read and write signals of the multiplexed bus; the data selector is used as the bus switch Design, in the write address stage of the multiplexing bus, connect the address bus of the DSP to the multiplexing bus, and in the stage of reading and writing data of the multiplexing bus, connect the data bus of the DSP to the multiplexing bus; stage, the direction of the tri-state data bus is from the DSP address bus to the multiplexing bus, and in the phase of writing data of the multiplexing bus, the direction of the tri-state data bus is from the DSP data bus to the multiplexing bus, and in the phase of reading data of the multiplexing bus, The direction of the tri-state data bus is from the multiplexing bus to the DSP data bus.

cpu_dout, cpu_to_can_data, and can_to_cpu_data are intermediate variables for data stream transmission on the tri-state bus.

When can_ale is high, connect cpu_addr to cpu_to_can_data, and output the DSP address signal to the multiplexing bus;

When can_ale is low level, connect cpu_dout to cpu_to_can_data, and connect the DSP data signal to the multiplexing bus;

TSB is a tri-state buffer, ENB is an enable terminal, when ENB is logic 1 (high level), the TSB input is connected to the output, when ENB is logic 0 (low level), TSB directly outputs a high-impedance state;

When the ENB of TSB1 is logic 1, it means that when the DSP does not perform a read operation, the data flow defaults to cpu_data to cpu_dout;

When the ENB of TSB2 is logic 1, it means that the DSP chip select is low, and when the DSP output enable is low, it is a DSP read data operation, and the data flow direction is from can_to_cpu_data to cpu_data;

When the ENB of TSB3 is logic 1, it means that the DSP chip select is low, the output enable is high (DSP write operation) or the DSP chip select is low, the output enable is low, and the multiplexed bus latch signal is high (DSP read operation) The establishment phase), the data flow is from cpu_to_can_data to can_data;

When the ENB of TSB4 is logic 1, it means that the DSP chip select is low, the DSP output enable is low, and when the multiplexed bus address latch is low, it is the multiplexed bus data output operation, and the data flow is from can_data to can_to_cpu_data.

Embodiment 1: Implementation using gate circuits and monolithic components

For buffers BF1 and BF2, choose a 2-way buffer SN74LVC2G34 from TI,

And gates AG1, AG2, AG3, AG4, AG5, choose 1 piece of 4-way AND gate SN74LVC08A of TI company, 1 piece of single-way AND gate sn74lvc1g08,

NOT gate NG1, NG2, NG3, NG4, select 2 pieces of 2-way NOT gate SN74LVC2G04

Or gate OG1, OG2, 1 piece of TI company's two-way OR gate SN74LVC2G32,

Three-state buffers TSB1, TSB2, TSB3, TSB4, choose 4 8-channel three-state buffers SN74LVC244A from TI Company,

Data selector MUX, select 2 pieces of TI's 4-bit 2-to-1 multiplexer SN74CB3Q3257

Embodiment 2: Adopt FPGA to realize

The utility model is realized on the FPGA/xc5vlx30t of XILINX Company, and verified by using DSP/TMS320C6701 of TI Company, and the test waveform is shown in Fig. 2 and 3 .

Claims (7)

1. an interface conversion circuit for Harvard structure bus and multiplex bus, is characterized in that comprising: comprise the first impact damper BF1, the second impact damper BF2, first and door AG1, second and door AG2, the 3rd with door AG3, the 4th with door AG4, the 5th with door AG5, the first not gate NG1, the second not gate NG2, the 3rd not gate NG3, the 4th not gate NG4, first or door OG1, second or door OG2, the first three-state buffer TSB1, the second three-state buffer TSB2, the 3rd three-state buffer TSB3, the 4th three-state buffer TSB4 and data selector MUX;

The read signal cpu_rd of DSP is input to the input end of the first impact damper BF1, and the output terminal of the first impact damper BF1 exports as the read signal can_rd of multiplex bus; The input end of the first impact damper BF1 also links together with first and an input end of door AG1;

The write signal cpu_we of DSP is input to the input end of the second impact damper BF2, and the output terminal of the second impact damper BF2 exports as the write signal can_wr of multiplex bus; The input end of the second impact damper BF2 also links together with first and another input end of door AG1;

First exports as the chip selection signal can_cs of multiplex bus with the output signal of door AG1, meanwhile, first with the output signal of door AG1 also as second with the input signal of door AG2;

The chip selection signal cpu_ce of DSP external memory space links together with second and another input end of door AG2 by the first not gate NG1 is oppositely rear, second with the data selection end of the output signal connection data selector switch MUX of door AG2, simultaneously, second also exports as the address latch signal can_ale of multiplex bus with the output signal of door AG2, second with the output signal of door AG2 by the second not gate NG2 oppositely after be connected to the input end of the 3rd and door AG3;

The address bus cpu_addr of DSP is connected to an input end of data selector MUX, the data bus cpu_data of DSP is connected to another input end of data selector MUX by the first three-state buffer TSB1, the output signal of data selector MUX is by connection multiplexing bus can_data after the 3rd three-state buffer TSB3;

Multiplex bus can_data is connected to the data bus cpu_data of DSP successively by the 4th three-state buffer TSB4 and the second three-state buffer TSB2;

First or two input ends of door OG1 connect the output enable signal cpu_aoe of chip selection signal cpu_ce and DSP of DSP external memory space respectively, first or the output terminal of door OG1 be connected to the Enable Pin of the first three-state buffer TSB1, simultaneously, first or the output terminal of door OG1 be also connected to the Enable Pin of the second three-state buffer TSB2 by the 3rd not gate NG3

The output terminal of the 3rd not gate NG3 be connected to simultaneously the 3rd with the input end of door AG3 and the 4th with the input end of door AG4, the 3rd is connected to the Enable Pin of the 4th three-state buffer TSB4 with the output terminal of door AG3;

Second with the output signal of door AG2 as the 4th with the input signal of door AG4, the 4th is connected to an input end of second or door OG2 with the output terminal of door AG4;

The output enable signal cpu_aoe of DSP is connected to an input end of the 5th and door AG5, the chip selection signal cpu_ce of DSP external memory space is by being connected to another input end of the 5th and door AG5 after the 4th not gate NG4, the 5th is connected to another input end of second or door OG2 with the output terminal of door AG5; Second or the output terminal of door OG2 be connected to the Enable Pin of the 3rd three-state buffer TSB3.

2. the interface conversion circuit of a kind of Harvard structure bus according to claim 1 and multiplex bus, is characterized in that: the first impact damper BF1 and the second impact damper BF2 adopts TI company No. 2 impact damper SN74LVC2G34 to realize.

3. the interface conversion circuit of a kind of Harvard structure bus according to claim 1 and multiplex bus, is characterized in that: first adopts 4 tunnels of 1 slice TI company and door SN74LVC08A and 1 slice single channel and door sn74lvc1g08 to realize with door AG3, the 4th with door AG4 and the 5th and door AG5 with door AG2, the 3rd with door AG1, second.

4. the interface conversion circuit of a kind of Harvard structure bus according to claim 1 and multiplex bus, is characterized in that: the first not gate NG1, the second not gate NG2, the 3rd not gate NG3 and the 4th not gate NG4 adopt 22 road not gate SN74LVC2G04 to realize.

5. the interface conversion circuit of a kind of Harvard structure bus according to claim 1 and multiplex bus, is characterized in that: first or door OG1 and second or door OG2 adopt 1 TI company two-way or door SN74LVC2G32 to realize.

6. the interface conversion circuit of a kind of Harvard structure bus according to claim 1 and multiplex bus, is characterized in that: the first three-state buffer TSB1, the second three-state buffer TSB2, the 3rd three-state buffer TSB3 and the 4th three-state buffer TSB4 adopt 4 TI company 8 passage three-state buffer SN74LVC244A to realize.

7. the interface conversion circuit of a kind of Harvard structure bus according to claim 1 and multiplex bus, is characterized in that: data selector MUX adopts 42,2 TI companies to select 1 multiplexer SN74CB3Q3257 to realize.