CN1155103C - Semiconductor device and manufacturing method of the same - Google Patents
Semiconductor device and manufacturing method of the same Download PDFInfo
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- CN1155103C CN1155103C CNB981188214A CN98118821A CN1155103C CN 1155103 C CN1155103 C CN 1155103C CN B981188214 A CNB981188214 A CN B981188214A CN 98118821 A CN98118821 A CN 98118821A CN 1155103 C CN1155103 C CN 1155103C
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 230000005669 field effect Effects 0.000 claims abstract description 78
- 239000000463 material Substances 0.000 claims abstract 5
- 239000010410 layer Substances 0.000 claims description 187
- 238000000034 method Methods 0.000 claims description 36
- 239000012535 impurity Substances 0.000 claims description 29
- 230000004888 barrier function Effects 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 abstract description 5
- 230000006872 improvement Effects 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910010282 TiON Inorganic materials 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 230000009467 reduction Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- -1 boron ion Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
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- Junction Field-Effect Transistors (AREA)
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Abstract
In a semiconductor device by a complex-type bipolar transistor device in which a junction-type field effect transistor is connected to a bipolar transistor, to make it possible to ensure a good and stable characteristic of the bipolar transistor without incurring a larger area in the junction-type field effect transistor J-FET. In a semiconductor device having a bipolar transistor and a junction-type field effect transistor, in which a collector of the bipolar transistor and a source of the junction-type field effect transistor are connected, a gate region of the junction-type field effect transistor, a gate contact conductive layer, and a drain contact conductive layer for a drain region are formed of conductive layers which are formed as respectively different layers with a same conductive material or mutually different materials and an arrangement surface of an edge portion on the drain side of the gate contact conductive layer is positioned below an arrangement surface of an edge portion on the gate side of the drain contact conductive layer.
Description
The present invention relates to semiconductor device, more particularly, relate to the compound bipolar transistor device and the manufacture method thereof that comprise bipolar transistor and junction field effect transistor.
As shown in Figure 1, the following fact is for example disclosed: be cascaded to the high withstand voltage bipolar transistor that constitutes composite construction on the bipolar transistor TR by the junction field effect transistor J-FET that height is withstand voltage in day patent gazette No.53-67368 of the present disclosure.
According to this structure, when the terminal C that is added to collector one side of bipolar transistor TR when high voltage goes up, depletion layer is from the drain junctions expansion of junction field effect transistor J-FET, and generation pinch off (pinch off), and the result just stops the collecting region that high voltage is added to bipolar transistor TR.In other words,, only add voltage, can in low withstand voltage bipolar transistor, realize high withstand voltage thus less than the pinch-off voltage Vp of junction field effect transistor J-FET for the collector of bipolar transistor TR voltage Vce to emitter.
But, under the situation of this structure, controllable maximum current is restricted to the saturation current Idss less than this junction field effect transistor J-FET in bipolar transistor TR, the result, when attempting to increase the saturation current Idss of junction field effect transistor J-FET, grid width (channel width) is broadened, produce the big rough sledding of area change that junction field effect transistor J-FET occupies thus.
On the other hand, a kind of withstand voltage bipolar transistor of compound height that can control the big electric current of the saturation current Idss that is lower than junction field effect transistor J-FET has at least for example been proposed in day patent gazette No.54-89581 of the present disclosure.
According to the proposal in this communique, as shown in Figure 2, the collector of npn type bipolar transistor TR is connected on the source electrode of junction field effect transistor J-FET, the base stage with bipolar transistor TR is connected on the grid G of J-FET simultaneously.In this case, when the terminal C that high voltage is added to collector one side goes up, make junction field effect transistor J-FET be in the pinch off state, only make and to be added on this bipolar transistor TR less than the voltage of the pinch-off voltage Vp of this J-FET that its result can realize high withstand voltage in low withstand voltage bipolar transistor TR.In this case, when this bipolar transistor TR is in saturation condition, the grid of this J-FET is carried out forward bias, may command surpasses the big electric current of the saturation current Idss of this J-FET thus.
In these structures, withstand voltage in order in bipolar transistor TR, to realize low withstand voltage transistorized height, must reduce the pinch-off voltage Vp among the junction field effect transistor J-FET.
In addition, under the situation of this structure, because will be connected in series on the collector of bipolar transistor TR at the source electrode of junction field effect transistor J-FET and the part between the drain electrode, thus require the conducting resistance of this J-FET low as much as possible, so that obtain high-speed response and high frequency characteristics.
But,, must increase the impurity concentration of channel part for conducting resistance that reduces this J-FET and the saturation current Idss that improves this J-FET.When increasing the impurity concentration of channel part, just cause the increase of pinch-off voltage Vp, cause the inconsistent situation of the improvement of the minimizing of the minimizing of pinch-off voltage Vp and conducting resistance and Idss thus.In addition, do not increase pinch-off voltage Vp, grid width will be broadened, but in this case, the area that is occupied by J-FET increases, hinder the high density of device thus and realize less area in order to increase Idss and minimizing conducting resistance.
As mentioned above, the purpose of this invention is to provide a kind of compound bipolar transistor device and manufacture method thereof that junction field effect transistor and bipolar transistor are coupled together, this manufacture method can guarantee the good and stable properties of this bipolar transistor and can not cause the area of junction field effect transistor J-FET to become greatly.
Semiconductor device of the present invention disposes like this, this device comprises bipolar transistor and junction field effect transistor, wherein the collector of bipolar transistor and the source electrode of junction field effect transistor are coupled together, make and to form by following conductive layer with the drain electrode contact conductive layer that contacts with the drain region with grid contact conductive layer that ohmic contact is carried out in the grid region of junction field effect transistor, this conductive layer uses different separately layer conductive layers that constitutes of being made by identical electric conducting material or mutually different electric conducting material to form, be formed on the configuration surface of edge part office of drain electrode one side of grid contact conductive layer like this, be located under the configuration surface of the edge part office of grid one side of drain electrode contact conductive layer.
In addition, the invention provides a kind of manufacture method that comprises the semiconductor device of bipolar transistor and junction field effect transistor, in this device, the collector of bipolar transistor and the source electrode of junction field effect transistor are coupled together to obtain the aimed semiconductor device, in this manufacture method, be used to form the operation of the grid contact conductive layer in the junction field effect transistor, be used to form the operation of the interlayer insulating film on the grid contact conductive layer and be used to form the operation of the drain electrode contact conductive layer in the junction field effect transistor thereafter, be formed on the configuration surface of edge part office of drain electrode one side of grid contact conductive layer like this, be located on the configuration surface of the edge part office of grid one side of drain electrode contact conductive layer.
Simultaneously, in contact conductive layer is sandwich construction, for example be that the configuration surface of the edge part office of contact conductive layer in this manual is the configuration surface of expression lower floor conductive layer edge part office under the situation of the laminated construction that constitutes of the contact conductive layer using the contact conductive layer be made up of semiconductor layer, be made up of metal level etc.
Simultaneously, according to above-mentioned configuration of the present invention, the configuration surface of the edge part office of drain electrode one side of grid contact conductive layer that will be in junction field effect transistor makes and the different surface of configuration surface in the edge part office of grid one side of drain electrode contact conductive layer, these two conductive layers can be configured to lean on enough closely or overlap each other, the necessity and the sufficient area that keep these two conductive layers simultaneously, moreover, because as a result of can be configured to lean on grid part and drain electrode contact portion enough near, so can realize high density, the minimizing of conducting resistance and the improvement of Idss.
In addition, the configuration surface of the edge part office of drain electrode one side of grid contact conductive layer is made different with configuration surface in the edge part office of grid one side of drain electrode contact conductive layer, and make it to become configuration surface under it, so just can make the grid contact conductive layer pass insulating barrier extends on the drain region, the result, because in this extension, form so-called MIS-FET structure, so realized the minimizing of pinch-off voltage Vp owing to this field effect.Thereby, because can avoid the minimizing largely of the impurity concentration in the channel part so that reduce pinch-off voltage Vp, so can avoid conducting resistance to uprise decline with Idss, can reduce pinch-off voltage Vp thus, moreover, can realize the minimizing of conducting resistance, the improvement of Idss, and make bipolar transistor with stable and good characteristic.
In addition,,, will never cause the process number purpose to increase, therefore, can not cause the decline of productivity ratio and the increase of cost according to method of the present invention in order to make this semiconductor device.
Fig. 1 is the circuit diagram according to another example of semiconductor device of the present invention;
Fig. 2 is another circuit diagram according to semiconductor device of the present invention;
Fig. 3 A and 3B are respectively the operation summary sections according to an example of manufacture method of the present invention;
Fig. 4 A and 4B are respectively the operation summary sections according to an example of manufacture method of the present invention;
Fig. 5 is the operation summary section according to an example of manufacture method of the present invention;
Fig. 6 is the operation summary section according to an example of manufacture method of the present invention;
Fig. 7 is the summary section according to another example of semiconductor device of the present invention;
Fig. 8 is the summary section according to another example of semiconductor device of the present invention; And
Fig. 9 is the summary section according to another example of semiconductor device of the present invention;
Below will describe according to device of the present invention with according to the embodiment of manufacture method of the present invention.
As Fig. 1 or illustrated in fig. 2, in the present invention, on the semiconductor of routine, form following structure: will conduct electricity the collector of bipolar transistor TR, the collector of the n type of npn type for example, source electrode with conduction junction field effect transistor J-FET, for example the source electrode of n type is connected to each other.Then, as shown in Figure 1, the emitter of bipolar transistor TR and the grid of junction field effect transistor J-FET are coupled together, or as shown in Figure 2, the base stage of bipolar transistor TR and the grid of junction field effect transistor J-FET are coupled together.
In this structure, constitute by following conductive layer with respect to the grid contact conductive layer in the grid region of this J-FET with respect to the drain electrode contact conductive layer in drain region, this conductive layer is formed the different layer of making by identical electric conducting material or mutually different electric conducting material.
Then, pass insulating barrier is formed on drain electrode one side of grid contact conductive layer on the drain region marginal portion, its configuration surface is located under the configuration surface of edge part office of grid one side of drain electrode contact conductive layer.
The marginal portion of drain electrode one side of grid contact conductive layer is passed on the drain region that insulating barrier extends to above-mentioned junction field effect transistor.
In addition, form grid contact conductive layer and base stage contact conductive layer by same conductive layer being carried out pattern etching.
Then, in above-mentioned configuration, on the drain region, pass the marginal portion that this insulating barrier is formed on drain electrode one side of drain electrode contact conductive layer, because form its configuration surface like this, be located under the configuration surface of edge part office of grid one side of drain electrode contact conductive layer, so compare with the situation that forms these two conductive layers on identical configuration surface, available little area forms this two conductive layers.
In addition, manufacture method according to semiconductor device of the present invention, when making above-mentioned device of the present invention, pass insulating barrier and on the drain region, form the grid contact conductive layer in the grid region of this J-FET, and after forming the grid contact conductive layer, be formed on the interlayer insulating film on the grid contact conductive layer, then, be formed for the contact conductive layer in drain region, obtain above-mentioned aimed semiconductor device of the present invention thus.
Be used to obtain situation hereinafter with reference to example explanation of Fig. 3 to Fig. 6 by manufacture method of the present invention according to an example of semiconductor device of the present invention.In this example, make a kind of like this device, on with semi-conductive substrate, form the bipolar transistor TR of npn type and the junction field effect transistor J-FET of n raceway groove at least, the n type collector of bipolar transistor TR and the n type source electrode of n channel junction field-effect transistors J-FET are coupled together.In this case, though not shown among the figure, formed semiconductor device with the circuit arrangement among Fig. 1 or Fig. 2, wherein the emitter of the grid of junction field effect transistor and bipolar transistor TR or base stage are carried out conductivity and be connected.
In this example, as shown in Fig. 3 A, the semiconductor substrate 2 that preparation is made by for example p type single crystalline Si matrix, and on an one first type surface 1a epitaxial growth semiconductor layer 3, for example resistivity is 0.3～5.0 Ω cm, and thickness is the n type semiconductor layer of 0.5～2.5 μ m, to form Semiconductor substrate 1.
Before the epitaxial growth of this semiconductor layer 3, utilize ion implantation, diffusion method etc. selectively n type impurity to be incorporated into high concentration in the part of the final formation transistor T R on the first type surface 1a of semiconductor substrate 2, the collector that has high impurity concentration with formation is imbedded district 4, carry out the epitaxial growth of semiconductor layer 3 thereafter.At this moment, because heating when the epitaxial growth of semiconductor layer 3, a part that is incorporated into the impurity in the semiconductor substrate 2 diffuses into semiconductor 3, and forms collector like this and imbed district 4, makes it be stretched over semiconductor layer 3 from semiconductor substrate 2.
As shown in Fig. 3 B, between the formation part of each semiconductor element, promptly, in the present example, between the formation part of bipolar transistor TR and junction field effect transistor J-FET and between the formation part at other circuit element, utilize well-known LOCOS (local oxidation of silicon) method to form element and separate insulating barrier 5 with lattice-shaped.
In addition, by introducing n type impurity with high concentration respectively, partly locate to form in the formation of bipolar transistor TR respectively and for example reach collector deeply and imbed the collector electrode extension area 6 in district 4 and partly locate to form high concentration source region 7 and high concentration drain region 8 in two opposite external side of the formation part of junction field effect transistor J-FET.Can inject by ion, for example with 50～100keV with 1 * 10
15/ cm
2～1 * 10
16/ cm
2Dosage inject P (phosphorus) ion and form these districts 6,7 and 8.
Then, become smooth, and be infused in element by ion and separate insulating barrier and form p type raceway groove for 5 times and end district CS by for example applying resist and losing the surface that makes Semiconductor substrate 1 deeply.
For example forming by CVD (chemical vapor deposition) method etc. on the surface of Semiconductor substrate 1, thickness is the SiO of 50～200nm
2Film is to form insulating barrier 9.
As shown in Fig. 4 A, pass the insulating barrier 9 that the operation that is used in shown in Fig. 3 B forms, on bipolar transistor TR forms the part that the final grid region that forms on the part that the base forms part and formed junction field effect transistor J-FET in the part forms part, open impurity respectively and introduce window 9w
1And 9w
2
At first pass impurity and introduce window 9w thereafter,
1And 9w
2, utilize CVD method etc. to form the 1st polycrystal semiconductor layer 10 with the thickness of 80～250nm, for example the Si polycrystal semiconductor layer makes it contact with the whole surface of semiconductor layer 3.Form semiconductor layer 10 like this, make it or as the layer of the p type impurity that when forming this film, comprises high concentration, or after the film that forms this semiconductor layer by injecting for example boron ion B
+, or BF
2 +And the layer of the p type impurity that comprises high concentration that obtains.
Thereafter, by photoetching this polycrystal semiconductor layer 10 is carried out pattern etching, then, it is etched into corresponding to the figure of the profile of the base stage contact conductive layer of the bipolar transistor that finally obtains with corresponding to the figure of the profile of the grid contact conductive layer of the junction field effect transistor J-FET that finally obtains.Then, utilize the CVD method to form, cover and comprise for example SiO as having the film that thickness is about 200～500nm
2The 1st polycrystal semiconductor layer 10 of impurity is to be formed on whole lip-deep interlayer insulating film 19.At this moment, as required,, can realize its low resistance and uniformity thus by heat-treating the growth of quickening the silicon crystal grain in the polycrystal semiconductor layer 10.
As shown in Fig. 4 B, by photoetching and utilize pattern etching etc. to pass interlayer insulating film 19 and the 1st polycrystal semiconductor layer 10 on the formation part of the intrinsic base region of this bipolar transistor, to form impurity and introduce window 11, pass this window 11, introduce p type impurity to form intrinsic base region 12.Can inject for example with 5keV～200keV and with 5.0 * 10 by ion
11～5.0 * 10
14/ cm
2Dosage inject BF
2 +Ion, or for example with 5keV～100keV and with 5.0 * 10
11～5.0 * 10
14/ cm
2Dosage inject B
+Ion is introduced impurity to form this intrinsic base region 12.
In addition, can introduce impurity by benefit of vapor diffusion.
In addition, as required, can pass through for example with 50keV～400keV and with 5.0 * 10
11～1.0 * 10
13/ cm
2Dose ion inject n type foreign ion, for example P
+Ion forms SIC (selecting the collector of injection) (not shown).
Secondly, as shown in Figure 5, on the inner surface of impurity introducing window 11, form sidewall 29.Can be by well-known method, for example with SiO
2Be deposited to the CVD method etc. of the thickness of about 400～1 μ m, and, form this sidewall 29 by on its whole surface, presenting the anisotropic etching of high etching character in the horizontal direction with RIE method (reactive ion etching).
Then, on the whole surface of the inboard that comprises the window 11 that forms sidewall 29, form the 2nd polycrystal semiconductor layer 13 that constitutes by the polysilicon that for example comprises n type impurity.This semiconductor layer 13 can be formed the film that comprises such as the semiconductor layer of the n type impurity of As and P (phosphorus) when forming it into film, or after this polycrystal semiconductor layer 13 is formed film, can the n type impurity of As and P (phosphorus) forms the polycrystal semiconductor layer that comprises impurity by for example injecting therein.
By carry out the pattern etching of for example photoetching, 2nd polycrystal semiconductor layer 13 be etched into the figure of emitter contact conductive layer thereafter.
Secondly, be the SiO of 100nm～500nm with CVD method deposition thickness on whole surface
2The film (not shown), and under about 700 ℃～1200 ℃, carry out 5 seconds～2 hours heat treatment, make p type impurity be diffused into semiconductor layer 3 from the 1st polycrystal semiconductor layer 10, the p type with high concentration that forms on every side of the intrinsic base region 12i of former formation engages base 12 thus
g, therefore, base 12 is made of these parts, and in the formation part of junction field effect transistor J-FET, forms grid region 14.In addition, n type impurity has the emitter region 15 of high impurity concentration simultaneously from 13 diffusions of the 2nd polycrystal semiconductor layer with formation.
By this way, for example imbed the effect that a part of distinguishing the n type semiconductor layer 3 on 4 plays collecting region 16 at collector, form p type base 12 thereon, on this base, form n type emitter region 15, thereby form bipolar transistor TR, on with semi-conductive substrate 1, form junction field effect transistor J-FET simultaneously, wherein the knot of the grid under grid region 14 j
1P-n junction part j with 3 of p N-type semiconductor N matrix 2 and n type semiconductor layer
2Between form channel part 16, the effect in source region and drain region is played in the both sides of this channel part, forms high concentration source region 7 and high concentration drain region 8 respectively at this place.
Then, as shown in Figure 6, pass each insulating barrier 9,19 etc., on collector extension area 6, on high concentration source region 7, on high concentration drain region 8, on grid contact conductive layer 17G, have again, as mentioned above, forming on the whole surface under the situation of insulating barrier, even on emitter contact conductive layer 17E, open contact window respectively, and form the conductive layer with favorable conductive rate, these conductive layers carry out ohmic contact with comprising each zone of the inboard of these windows.These conductive layers can form by making the Ti/TiON/Al structure, in this structure, utilize the metal conducting layer of deposit integrally such as aluminium such as evaporation, sputter etc. for example to arrive Ti layer and TiON layer as barrier metal layer.Then this metal conducting layer is utilized the pattern etching of photoetching.In this embodiment, formation extends on collector electrode extension area 6 and the high concentration source region 7 and is electrically connected both contact conductive layer 18CS, on high concentration drain region 8, form drain electrode contact conductive layer 18D simultaneously, and on grid contact conductive layer 17G and emitter contact conductive layer 17E, form upper strata contact conductive layer 18G and the 18E that respectively has the favorable conductive rate respectively for grid and emitter.
Form semiconductor device by this way, wherein on semi-conductive substrate 1, form bipolar transistor TR and junction field effect transistor J-FET, on the grid region 14 of the joint base 12G of the base 12 of bipolar transistor TR and junction field effect transistor J-FET, by so-called autoregistration, make identical conductive layer, promptly by the 1st polycrystal semiconductor layer 10 constitute base stage contact conductive layer 17B and grid contact conductive layer 17G contact with each other, and in emitter region 15, the 2nd polycrystal semiconductor layer 13 is constituted with emitter contact conductive layer 17E and contacts by autoregistration.
Then, not shown, a kind of semiconductor device with the circuit arrangement that illustrated in Fig. 1 is provided, wherein for example the upper strata contact conductive layer 18G of the upper strata contact conductive layer 18E of emitter and grid is coupled together with electrically conducting manner mutually with the two method of continuous formation such as figure by a kind of.
Perhaps, a kind of semiconductor device with the circuit arrangement that illustrated in Fig. 2 is provided,, and engages base 12g wherein for example simultaneously with the grid region 14 of junction field effect transistor J-FET and the base 12 of bipolar transistor TR, form a row graph, though not shown.
That is, the grid of n channel-type junction field effect transistor J-FET and emitter or the base stage of npn type bipolar transistor TR are coupled together, the source electrode of this J-FET and the collector of this TR are coupled together, make transistor have high withstand voltage semiconductor device with formation.
In according to semiconductor device of the present invention, because grid contact conductive layer 17G is formed the conductive layer of being made by different operations respectively with drain electrode contact conductive layer 18D, that is, form mutually different layer, so will be at the marginal portion 17G of drain electrode one side of grid contact conductive layer 17G
1Configuration surface and at the marginal portion 18D of grid one side of drain electrode contact conductive layer 18D
1Configuration surface on thickness direction, become different configuration surfaces, by doing like this, grid contact conductive layer 17G and drain electrode contact conductive layer 18D be lamination or via interlayer insulating film 19 mutually and then.
In addition, in according to semiconductor device of the present invention, because grid contact conductive layer 17G is formed different layers with drain electrode contact conductive layer 18D, grid contact conductive layer 17G is located at the marginal portion 18D of the side of drain electrode contact conductive layer 18D
1Configuration surface under, that is, and make grid contact conductive layer 17G from the grid region 14 pass insulating barrier 9 extend to the drain electrode one side, form MIS (under this situation, being MOS) structure division thus herein.
As previously discussed, because as begin described, make according to device of the present invention and have for example structure shown in Fig. 1 or 2, so can realize the high withstand voltage of bipolar transistor TR, and owing to the marginal portion 17G that in junction field effect transistor J-FET, makes in drain electrode one side of grid contact conductive layer 17G
1Configuration surface and at the marginal portion 18D of grid one side of drain electrode contact conductive layer 18D
1Configuration surface become different surfaces, so can dispose this two configuration surfaces like this, make both sufficiently near or both are overlapped each other, the area that keeps these two conductive layers simultaneously with state necessity and sufficient, have again, can make the contact portion of grid part and drain electrode close fully, the result can realize the minimizing of high density, conducting resistance and the improvement of Idss.
In addition, because make the marginal portion 17G of drain electrode one side of grid contact conductive layer 17G
1Reach drain electrode one side to present MIS or MOS structure, so because of the knot J1 in grid region 14 and MIS-FET or MOS-FET effect are formed on the depletion layer that just forms when grid added reverse biased, can realize the further reduction of pinch-off voltage Vp of J-FET or the minimizing of leakage current thus.
In addition, as mentioned above, by marginal portion 17G with drain electrode one side of grid contact conductive layer 17G
1Form different layers with drain electrode contact conductive layer 18D, can make distance between both marginal portion on the planar surface direction less than by photoetching and the minimum range that etching limited (gap) under situation about forming by identical layer.Thereby, as the grid upper strata contact conductive layer 18G of gate electrode and drain electrode and drain electrode contact conductive layer 18D under situation about in the above-mentioned example, constituting by identical conductive layer, can make the metal level of Ti/TiON/Al structure, above-mentioned MIS or MOS structure division stretch out (extension) fully, can strengthen above-mentioned MIS or MOSFET effect thus to drain electrode one side.
Because can realize the minimizing of pinch-off voltage Vp by this way, so can avoid the significant reduction of the impurity concentration in channel part, thereby the rough sledding that can avoid increasing conducting resistance and reduce Idss, can reduce pinch-off voltage Vp and conducting resistance thus and improve Idss, so just can make and have bipolar transistor stable and good characteristic.
In addition, above-mentioned according to manufacture method of the present invention in, used a kind of manufacture method that is used for the bipolar transistor of double-layered polycrystal layer type, wherein can be by using the 1st and the 2nd polycrystal semiconductor layer 10 and 13, engage base and emitter region by impurity being incorporated in the Semiconductor substrate to form from this, and, contact conductive layer and each zone are carried out from coupling (autoregistration) by making these semiconductor layers become electrode extension contact conductive layer by engaging base and emitter region.According to the present invention, can constitute such semiconductor device, wherein do not increase under the process number purpose situation comparing, form junction field effect transistor J-FET and bipolar transistor TR by simple method with the manufacture method of the bipolar transistor of the such double-layered polycrystal layer type that is used for common bipolar integrated circuit.
Simultaneously, above-mentioned example is the situation that forms the high concentration source region 7 of the collector electrode extension area 6 of bipolar transistor TR and junction field effect transistor J-FET respectively, so as shown in Fig. 7 to Fig. 9, zone 6 and 7 can be formed common zone 67.
In Fig. 7 to Fig. 9, indicate part with identical reference number corresponding to Fig. 3 to 6, will omit the description of the repetition of the structure that illustrated relevant and manufacture method with Fig. 3 to Fig. 6.But, the example of Fig. 7 illustrates its summary section, this is the situation with structure of the circuit arrangement that illustrated in Fig. 1, a kind of like this configuration wherein is provided, emitter upper strata contact conductive layer 18E among Fig. 4 and grid upper strata contact conductive layer 18G has been coupled together by common contact conductive layer 18EG.In addition, in this case, on base stage contact conductive layer 17B, pass the part of insulating barrier 19 and open contact window, and pass this contact window formation base stage upper strata contact conductive layer 18B, to be used to draw base terminal.
In this case, as mentioned above,, can form contact conductive layer 18B and 18EG simultaneously respectively with the formation of drain electrode contact conductive layer by for example pattern etching of the metal level of Ti/TiON/Al structure.
In addition, example shown in Fig. 8, it is the situation that forms semiconductor device with the circuit arrangement shown in Fig. 2, wherein in the following manner the base stage of bipolar transistor TR is connected to the grid of junction field effect transistor J-FET, with above-mentioned identical, for example, formation with the drain electrode contact conductive layer 18D that has the Ti/TiON/Al structure forms contact conductive layer 18CG, and this contact conductive layer 18CG and each are carried out ohmic contact by base stage contact conductive layer 17B and grid contact conductive layer 17G that the 1st polycrystal semiconductor layer 10 constitutes.
In addition, example shown in Fig. 9 is the situation that forms the semiconductor device with the circuit arrangement shown in Fig. 2, wherein with continuous figure will be 10 that constitute by the 1st polycrystal semiconductor layer, form the common contact conductive layer 17BG that contacts with the 1st polycrystal semiconductor layer 10 as the base stage contact conductive layer 17B that had illustrated at Fig. 3 to 6 with grid contact conductive layer 17G.
Secondly, semiconductor device and manufacture method thereof in each example shown in Fig. 7 to 9, can be in identical mode as having illustrated among Fig. 3 to 6, owing to the configuration shown in Fig. 1 or Fig. 2, realization bipolar transistor TR's is high withstand voltage, simultaneously, owing to above-mentioned identical reason, realized the minimizing of pinch-off voltage Vp, but do not reduce the impurity concentration in the channel part, therefore, can realize the improvement of conducting resistance and the improvement of Idss, under the situation of the number that does not increase the manufacturing process as semiconductor device, form bipolar transistor TR with simple method with stable and good characteristic with junction field effect transistor J-FET and bipolar transistor TR.
Secondly, when the configuration that presents shown in Fig. 7 to 9, because provide the structure that the source electrode of the collector of bipolar transistor TR and junction field effect transistor J-FET is directly coupled together by high concentration region 67, so can realize the minimizing of collector resistance, the reduction of collector saturation voltage and the further reduction of element area.
In addition, under the situation that does not have high concentration region 67, imbed district 4 with the configuration that the source electrode of the collector of bipolar transistor TR and junction field effect transistor J-FET directly couples together, can realize the minimizing of element area by providing by high concentration.
Simultaneously, be not limited to above-mentioned example according to device of the present invention and manufacture method thereof.For example, as bipolar transistor TR, can provide the pnp transistor npn npn, as junction field effect transistor, configurable p raceway groove J-FET has again, can constitute comprising the semiconductor device of the semiconductor element that forms in the ordinary way etc. etc.
As mentioned above, according to device of the present invention and manufacture method of the present invention, comprising bipolar transistor and junction field effect transistor and the collector of bipolar transistor and the source electrode of junction field effect transistor are being coupled together to present in the high withstand voltage semiconductor device, because the configuration surface of marginal portion of drain electrode one side of the grid contact conductive layer in junction field effect transistor is become and the different surface of configuration surface in the marginal portion of grid one side of drain electrode contact conductive layer, event can make these two conductive layers be configured to lean on enough closely or overlap each other, the necessity and the sufficient area that keep these two conductive layers simultaneously, because the contact portion of grid part and drain electrode can be configured to lean on enough closely, so can realize high density, the minimizing of conducting resistance and the improvement of Idss.
In addition, configuration surface in the marginal portion of drain electrode one side of grid contact conductive layer is become and the different surface of configuration surface in the marginal portion of grid one side of drain electrode contact conductive layer, and become configuration surface under the latter, can make the grid contact conductive layer pass insulating barrier like this extends on the drain region, the result, form so-called MIS-FET structure in this extension, the field effect of this structure realizes the minimizing of pinch-off voltage Vp.Thereby, can avoid the significant reduction of the impurity concentration in channel part, thereby can reduce pinch-off voltage Vp, the rough sledding of avoiding increasing conducting resistance and reducing Idss, can reduce pinch-off voltage Vp thus, the minimizing that can realize conducting resistance is arranged again, improve Idss, can make and have bipolar transistor stable and good characteristic.
In addition,,, will never cause the process number purpose to increase, therefore, can not cause the decline of productivity ratio and the increase of cost according to method of the present invention in order to make this semiconductor device.
Thereby, according to the present invention, can realize the large scale integrated circuit that has the semiconductor device of high-performance, high density, high integration and high reliability and have high-performance, high density, high integration and high reliability.
The preferred embodiments of the present invention have been described with reference to the accompanying drawings, but should be appreciated that, the invention is not restricted to the embodiments described, do not departing under the situation of the spirit or scope of the present invention that limits as accompanying Claim, and one of skill in the art can carry out various changes and correction.
Claims (15)
1. semiconductor device that comprises bipolar transistor and junction field effect transistor, wherein the collector of described bipolar transistor and the source electrode of described junction field effect transistor are coupled together, described bipolar transistor and described junction field effect transistor form on same substrate, and described semiconductor device is characterised in that and comprises:
The grid contact conductive layer is passed insulating barrier and is contacted with the grid region of described junction field effect transistor; And the drain electrode contact conductive layer, pass insulating barrier and contact with the drain region, wherein,
The configuration surface of the marginal portion of drain electrode one side of described grid contact conductive layer is located under the configuration surface of marginal portion of described grid one side of described drain electrode contact conductive layer.
2. semiconductor device as claimed in claim 1 is characterized in that:
Described drain electrode contact conductive layer and described grid contact conductive layer are made of kinds of materials.
3. semiconductor device as claimed in claim 1 is characterized in that:
Described drain electrode contact conductive layer and described grid contact conductive layer are made of the material of identical type.
4. semiconductor device as claimed in claim 1 is characterized in that:
The described grid contact conductive layer of the base stage contact conductive layer of described bipolar transistor and described junction field effect transistor is formed by identical conductive layer.
5. semiconductor device as claimed in claim 1 is characterized in that:
The emitter of described bipolar transistor and the grid of described junction field effect transistor are coupled together.
6. semiconductor device as claimed in claim 1 is characterized in that:
The base stage of described bipolar transistor and the grid of described junction field effect transistor are coupled together.
7. semiconductor device that comprises bipolar transistor and junction field effect transistor, wherein the collector of described bipolar transistor and the source electrode of described junction field effect transistor are coupled together, described bipolar transistor and described junction field effect transistor form on same substrate, and described semiconductor device is characterised in that and comprises:
The grid contact conductive layer is passed insulating barrier and is contacted with the grid region of described junction field effect transistor; And the drain electrode contact conductive layer, pass insulating barrier and contact with the drain region, wherein,
The collector of described bipolar transistor and the source electrode of described junction field effect transistor are formed by common semiconductor region,
The configuration surface of the marginal portion of drain electrode one side of described grid contact conductive layer is located under the configuration surface of marginal portion of described grid one side of described drain electrode contact conductive layer.
8. semiconductor device as claimed in claim 7 is characterized in that:
Described drain electrode contact conductive layer and described grid contact conductive layer are made of kinds of materials.
9. semiconductor device as claimed in claim 7 is characterized in that:
Described drain electrode contact conductive layer and described grid contact conductive layer are made of the material of identical type.
10. semiconductor device as claimed in claim 7 is characterized in that:
The described grid contact conductive layer of the base stage contact conductive layer of described bipolar transistor and described junction field effect transistor is formed by identical conductive layer.
11. semiconductor device as claimed in claim 7 is characterized in that:
The emitter of described bipolar transistor and the grid of described junction field effect transistor are coupled together.
12. semiconductor device as claimed in claim 7 is characterized in that:
The base stage of described bipolar transistor and the grid of described junction field effect transistor are coupled together.
13. manufacture method that comprises the semiconductor device of bipolar transistor and junction field effect transistor, wherein the collector of described bipolar transistor and the source electrode of described junction field effect transistor are coupled together, described bipolar transistor and described junction field effect transistor form on same substrate, and the manufacture method of described semiconductor device is characterised in that and comprises the steps:
On same substrate, form insulating barrier;
The opening of described insulating barrier is passed in formation; And
Form the grid contact conductive layer that contacts with the grid region of described junction field effect transistor; And on described grid contact conductive layer, form interlayer insulating film, and thus, form the drain electrode contact conductive layer that contacts with drop ply like this, be located on the configuration surface of marginal portion of drain electrode one side of described grid contact conductive layer.
14. the manufacture method of semiconductor device as claimed in claim 13 is characterized in that:
By same conductive layer is carried out pattern etching, form the base stage contact conductive layer of described bipolar transistor and the grid contact conductive layer of described junction field effect transistor simultaneously.
15. the manufacture method of semiconductor device as claimed in claim 13 is characterized in that: the grid region that forms described junction field effect transistor by diffusion of impurities from the grid contact conductive layer that contacts with described grid region.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23711097A JP3709668B2 (en) | 1997-09-02 | 1997-09-02 | Semiconductor device and manufacturing method thereof |
| JP237110/1997 | 1997-09-02 | ||
| JP237110/97 | 1997-09-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1210371A CN1210371A (en) | 1999-03-10 |
| CN1155103C true CN1155103C (en) | 2004-06-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB981188214A Expired - Lifetime CN1155103C (en) | 1997-09-02 | 1998-09-02 | Semiconductor device and manufacturing method of the same |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6278143B1 (en) |
| JP (1) | JP3709668B2 (en) |
| CN (1) | CN1155103C (en) |
| ID (1) | ID20785A (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ATE459981T1 (en) * | 2000-03-30 | 2010-03-15 | Nxp Bv | SEMICONDUCTOR COMPONENT AND ITS PRODUCTION PROCESS |
| US7598521B2 (en) * | 2004-03-29 | 2009-10-06 | Sanyo Electric Co., Ltd. | Semiconductor device in which the emitter resistance is reduced |
| JP5114824B2 (en) * | 2004-10-15 | 2013-01-09 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| US7560755B2 (en) | 2006-06-09 | 2009-07-14 | Dsm Solutions, Inc. | Self aligned gate JFET structure and method |
| US7772060B2 (en) * | 2006-06-21 | 2010-08-10 | Texas Instruments Deutschland Gmbh | Integrated SiGe NMOS and PMOS transistors |
| JP4751308B2 (en) * | 2006-12-18 | 2011-08-17 | 住友電気工業株式会社 | Horizontal junction field effect transistor |
| NZ597036A (en) * | 2009-06-19 | 2014-01-31 | Power Integrations Inc | Methods of making vertical junction field effect transistors and bipolar junction transistors without ion implantation and devices made therewith |
| SE1150065A1 (en) * | 2011-01-31 | 2012-07-17 | Fairchild Semiconductor | Silicon carbide bipolar transistor with overgrown emitter |
| US9331097B2 (en) | 2014-03-03 | 2016-05-03 | International Business Machines Corporation | High speed bipolar junction transistor for high voltage applications |
| KR101716957B1 (en) * | 2014-07-02 | 2017-03-15 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Junction gate field-effect transistor (jfet), semiconductor device and method of manufacturing |
| US9935628B2 (en) * | 2015-11-10 | 2018-04-03 | Analog Devices Global | FET—bipolar transistor combination, and a switch comprising such a FET—bipolar transistor combination |
| US9653455B1 (en) * | 2015-11-10 | 2017-05-16 | Analog Devices Global | FET—bipolar transistor combination |
| US10218350B2 (en) | 2016-07-20 | 2019-02-26 | Semiconductor Components Industries, Llc | Circuit with transistors having coupled gates |
| US9947654B2 (en) | 2016-09-08 | 2018-04-17 | Semiconductor Components Industries, Llc | Electronic device including a transistor and a field electrode |
| CN108878513B (en) * | 2017-05-09 | 2021-09-03 | 世界先进积体电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN113823678A (en) * | 2021-09-03 | 2021-12-21 | 无锡市晶源微电子有限公司 | High-voltage NPN device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4485392A (en) * | 1981-12-28 | 1984-11-27 | North American Philips Corporation | Lateral junction field effect transistor device |
| US4600932A (en) * | 1984-10-12 | 1986-07-15 | Gte Laboratories Incorporated | Enhanced mobility buried channel transistor structure |
| JPS62289544A (en) * | 1986-06-09 | 1987-12-16 | Daikin Ind Ltd | Fluorine-containing compound |
| JPH04291952A (en) * | 1991-03-20 | 1992-10-16 | Sony Corp | Semiconductor device |
| SE500814C2 (en) * | 1993-01-25 | 1994-09-12 | Ericsson Telefon Ab L M | Semiconductor device in a thin active layer with high breakthrough voltage |
| FR2708144A1 (en) * | 1993-07-22 | 1995-01-27 | Philips Composants | Integrated device associating a bipolar transistor with a field effect transistor. |
-
1997
- 1997-09-02 JP JP23711097A patent/JP3709668B2/en not_active Expired - Lifetime
-
1998
- 1998-08-31 ID IDP981183A patent/ID20785A/en unknown
- 1998-09-01 US US09/145,431 patent/US6278143B1/en not_active Expired - Lifetime
- 1998-09-02 CN CNB981188214A patent/CN1155103C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1210371A (en) | 1999-03-10 |
| JP3709668B2 (en) | 2005-10-26 |
| JPH1187240A (en) | 1999-03-30 |
| ID20785A (en) | 1999-03-04 |
| US6278143B1 (en) | 2001-08-21 |
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