JP3307112B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a vertical MOS transistor (hereinafter referred to as a MOSFET) and a vertical MOS / bipolar composite transistor (hereinafter referred to as a MOSFET) which are suitably used for electric power applications. Hereinafter, IGBT: Insulated Gate B
ipolar Transistor).

[0002]

2. Description of the Related Art FIG. 9 schematically shows the structure of a conventional vertical n-channel MOSFET. In this type of device, a gate electrode 14 is formed on one surface of a substrate 10 with a gate insulating film 12 interposed therebetween, and n ⁺ -type is doped into the silicon substrate 10 so as to be located on both sides of the gate electrode 14. Source regions 16, 16 are formed. Around the n ⁺ -type source region 16, a p ^-- type channel dope region 18 is formed. Further, the silicon substrate 10
A drain electrode 22 is formed on the other surface of the silicon substrate 10.
^{A +} type drain region 20 is formed. In this device, a drain current flows in the thickness direction (vertical direction) of the silicon substrate 10 via a channel formed immediately below the gate electrode 14.

One of the main destruction modes in such a vertical MOSFET is a back electromotive force destruction in an inductance load. This is mainly due to FIG.
Is often caused by current concentration due to turn-on of the parasitic npn transistor shown in FIG. Then, the drain electrode 22
When a high voltage is applied to the resulting depletion layer in a region D indicated by the chain line in FIG. 9, the dielectric breakdown due to current concentration width narrowest part of the depletion layer, i.e., n ⁺ -type source region 1
6 occurs in the area A immediately below. This is because the electric field is stronger as the width of the depletion layer is smaller. Therefore, in order to prevent dielectric breakdown between the source and the drain, it is effective to increase the width of the depletion layer. For that purpose, the distance in the depth direction of the region A of the p ⁻ -type channel doped region 18 is required. It is effective to increase the impurity concentration and increase the impurity concentration.

However, since the p ⁻ -type channel dope region 18 is formed by implanting impurities and thermally diffusing, if the depth is increased and the impurity concentration is increased, the distance in the region B where the channel is formed is increased. In addition, the impurity concentration increases accordingly, and the threshold value increases. As described above, the source-drain breakdown voltage and the threshold have a trade-off relationship, and they cannot be controlled independently.

Such a problem similarly occurs in an IGBT having a built-in MOS portion. That is, IGBT
In this case, the breakdown voltage between the emitter and the collector and the threshold value cannot be controlled independently, and it is difficult to achieve both the breakdown voltage between the emitter and the collector and the threshold characteristics at a high level.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to control the source-drain breakdown voltage and the threshold value independently, and to make the source-drain breakdown voltage sufficiently high.
An object of the present invention is to provide a vertical MOSFET having a structure capable of realizing an appropriate threshold value.

Another object of the present invention is to make it possible to control the emitter-collector breakdown voltage and the threshold value independently, and to realize an appropriate threshold value while sufficiently increasing the emitter-collector breakdown voltage. To provide IGB.

[0008]

As a means for achieving the above object, a MOS type semiconductor device according to the present invention comprises a silicon substrate and a gate insulating film formed on one surface of the silicon substrate via a gate insulating film. A gate electrode, a source region formed on the silicon substrate, and a continuation of the source region;
A channel formation region including a region where a channel can be formed, a drain region formed on the other surface side of the silicon substrate, and a lower end of the source region and the channel formation region in a depth direction, and And an insulating film formed in the silicon substrate along a region in a plane direction of the silicon substrate including at least a part of the source region and the channel formation region.

The above MOS type semiconductor device can be obtained, for example, by a manufacturing method characterized by including the following steps (a) to (f). This manufacturing method includes: (a) forming a second silicon layer having an impurity concentration lower than that of the first silicon layer on the first silicon layer functioning as a drain region; and (b) forming the second silicon layer. Forming an insulating film on the layer, and then forming an insulating film having a predetermined pattern by photolithography and etching; and (c) continuously forming a silicon layer on the insulating film and the exposed surface of the second silicon layer. Forming a third silicon layer continuous with the second silicon layer, (d) forming a gate insulating film and a gate electrode on the third silicon layer by stacking, and (e). step of forming a channel doped region is doped with impurities, and step (f) of the impurity doped to form a source region using the gate electrode as a mask, It includes,
In the step (b), the insulating film includes the source region.
Region and the lower end of the channel dope region in the depth direction.
The source region and the channel dope
Aspect of the silicon substrate, including at least a part of a region
It is characterized in that it is formed along the direction region.

A MOS / bipolar composite semiconductor device according to the present invention comprises a silicon substrate, a gate electrode formed on one surface of the silicon substrate via a gate insulating film, and an emitter region formed on the silicon substrate. A channel forming region that is continuous with the emitter region and includes a region where a channel can be formed; a collector region formed on the other surface side of the silicon substrate; and a depth direction of the emitter region and the channel forming region. At the lower end of the
An insulating film formed in the silicon substrate along a region in a plane direction of the silicon substrate including at least a part of the emitter region and the channel formation region.

The above-mentioned MOS / bipolar composite semiconductor device is obtained by a manufacturing method characterized by including the following steps (a) to (f), for example. The manufacturing method includes: (a) forming a second silicon layer having an impurity concentration lower than that of the first silicon layer on the first silicon layer functioning as a collector region; and (b) forming the second silicon layer. Forming an insulating film on the layer, and then forming an insulating film having a predetermined pattern by photolithography and etching; (c) continuously forming a silicon layer on the surface of the insulating film and the exposed second silicon layer Forming a third silicon layer continuous with the second silicon layer; (d) laminating and forming a gate insulating film and a gate electrode on the third silicon layer; (e) impurities including the step, of forming an emitter region an impurity doped step of forming a channel doped region, and (f) the gate electrode as a mask to dope the
In the step (b), the insulating film is
Under the depth direction of the channel region and the channel-doped region.
Located at the edge and these emitter regions and channels
The silicon-based substrate, including at least a portion of a doped region.
It is characterized by being formed along the area in the plane direction of the plate
I do.

[0012]

The MOS type semiconductor device (MOSFET) of the present invention
In the state described above, the insulating film is located at the lower end in the depth direction of the source and the channel formation region, and extends along the surface direction region of the silicon substrate including at least a part of the source region and the channel formation region. Does not form an npn junction in the silicon substrate. Therefore, for example, dielectric breakdown due to current concentration by the parasitic npn transistor can be prevented.
In addition, by forming the insulating film, insulation is separated, and the source-drain withstand voltage can be sufficiently increased. As a result, it is not necessary to consider the distance in the depth direction of the channel formation region and the impurity concentration, so that the distance and the impurity concentration in the channel formation region can be set independently of the withstand voltage characteristics, and therefore, an appropriate threshold value can be set. Can be realized.

In the MOS / bipolar composite semiconductor device (IGBT) of the present invention, the MOSFET
Similarly, at the lower end of the emitter region and the channel formation region in the depth direction, and along the surface region of the silicon substrate including at least a part of the emitter region and the channel formation region, By forming the insulating film, an npn junction is not formed in the silicon substrate, and dielectric breakdown due to the npn junction can be prevented. In addition, by forming the insulating film, it is not necessary to consider the distance in the depth direction and the impurity concentration of the channel formation region, so that the distance and the impurity concentration of the channel formation region can be controlled to predetermined values. Threshold can be realized.

As described above, according to the semiconductor device of the present invention, it is possible to achieve both a breakdown voltage characteristic and a threshold characteristic, which are conventionally in a trade-off relationship, at a high level.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

First Embodiment An example of a MOSFET according to the present invention will be described with reference to FIG. Illustrated n-channel MOSFET 1
No. 00 has a gate electrode 14 formed on one surface of a silicon substrate 10 with a gate insulating film 12 interposed therebetween. As the gate insulating film 12, for example, a silicon oxide film is used, and as the gate electrode 14, for example, an n ⁺ type polycrystalline silicon film is used.

The silicon substrate 10 on both sides of the gate electrode 14
Are formed with first conductivity type (n ⁺ type) source regions 16, 16. Around these source regions 16, 16, a second conductivity type (p ⁻ type) channel doped region 18, 1 is formed.
8 are formed respectively. The portion immediately below the gate electrode 14 in the channel dope region 18 forms a channel formation region 18a. The length L and the impurity concentration of the channel forming region 18a are set so as to obtain a predetermined threshold.

As a characteristic configuration of the present invention, an insulating film 30 is provided at the lowermost end of the source region 16 and the channel dope region 18 in the depth direction. This insulating film 30 is formed of the source region 16 and the channel dope region 1.
8 is formed so as to cover almost completely the region in the main surface direction of the silicon substrate 10. By providing such an insulating film 30, np is formed in the silicon substrate 10.
Since no n-junction is formed, dielectric breakdown caused by the parasitic npn transistor can be prevented. In other words, the insulating film 30 covers the region immediately below the source region 16 and at least a part of the channel-doped region 18 in order not to form an npn junction that may cause dielectric breakdown, and depletes from the end of the insulating film 30. Channel doped region 18 from layer
Is depleted and no current flows due to punch-through,
It is formed in consideration of the fact that it is formed in a region that does not hinder the flow of the drain current. Then, the insulating film 30
Is different depending on the required source-drain breakdown voltage, and the source-drain breakdown voltage depends on the doping amount of the channel formation region, the channel length, and the like.
Defined by these factors. This insulating film 3
0 is composed of, for example, SiO ₂ , Si ₃ N ₄ or the like.

Since the magnitude of the source-drain breakdown voltage mainly depends on the thickness of the insulating film 30, the source-drain breakdown voltage is set so as to obtain a sufficient source-drain breakdown voltage in accordance with the type, standard, and application of the device. Is done.

An n ⁺ type drain region 20 is formed on the other surface of the silicon substrate 10, and a drain electrode 22 is formed on the surface of the drain region 20.

In the n-channel MOSFET 100, by controlling the voltage applied to the gate electrode 14, an n-channel is formed in the channel forming region 18a, and the source region 16 and the drain region 20 conduct.
Drain current flows.

Then, n ⁺ type source region 16 and p ⁻
Providing insulating film 30 immediately below type channel doped region 18 prevents an npn junction having a low withstand voltage from being formed in silicon substrate 10 and thus reliably prevents dielectric breakdown due to, for example, current concentration due to a parasitic npn transistor. Can be. Further, since the source-drain breakdown voltage can be sufficiently increased by forming the insulating film 30, the source-drain breakdown voltage can be secured by controlling the depth of the channel dope region and the impurity concentration as in the conventional MOSFET. Need to be considered.
As a result, the distance and the impurity concentration of the channel forming region 18a can be set independently, and an appropriate threshold can be realized.

In the above-described MOSFET, an n-channel MOSFET in which the first conductivity type is an n-type and the second conductivity type is a p-type has been described. P-channel MOSF with n-type
It is also possible to apply to ET.

Next, the n-channel MOSFET 100
An example of a method for manufacturing the device will be described. (A) First, as shown in FIG. 2A, an n ⁻ -type single-crystal silicon layer (second silicon layer) 10b is formed on an n ⁺ -type single-crystal silicon substrate (first silicon layer) 10a by epitaxial growth. . Next, as shown in FIG. 2B, a silicon oxide (SiO ₂ ) film 30a is formed on the n ⁻ -type silicon layer 10b by a normal thermal oxidation method or the like, and further, as shown in FIG. Then, a part of the silicon oxide film 30a is removed by ordinary photolithography and reactive ion etching to perform patterning, and the insulating film 3 is formed.
0 is formed.

Next, as shown in FIG. 3D, a normal solid phase epitaxy (SPE) method or the like, that is, for example, on the surface of the insulating film 30 and the surface of the n ⁻ -type single crystal silicon layer 10b,
For example, an amorphous silicon layer is deposited by a vapor deposition method or a CVD method in an ultra-high vacuum, and the single crystal silicon layer (third silicon layer) 10c is formed by performing epitaxial growth by heat treatment at about 600 ° C., for example.

Next, as shown in FIG. 3E, a silicon oxide film is formed on the surface of the single crystal silicon layer 10c by a normal thermal oxidation method or the like, and then a polysilicon film is formed by a normal CVD method or the like. Is formed. This is patterned by ordinary photolithography and reactive ion etching to form the gate insulating film 12 and the gate electrode 1.
4 is formed. The polysilicon film forming the gate electrode 14 is doped with an n-type impurity, for example, phosphorus by, for example, diffusion or ion implantation, and is adjusted to a predetermined sheet resistance.

Next, as shown in FIG. 4 (F), for example, boron (B ⁺ ) is doped as a p-type impurity by ion implantation or the like, followed by thermal diffusion to form a p ⁻ -type channel doped region 18. In this step, the single-crystal silicon layer 10c formed by the solid-phase growth is converted into the n ⁻ -type single-crystal silicon layer 1 by thermal diffusion due to the heat treatment at this time.
0b, the impurity concentration becomes substantially the same as that of the silicon layers 1
Ob and 10c are almost homogeneous. And the first
A stacked body of the silicon layer 10a, the second silicon layer 10b, and the third silicon layer 10c corresponds to the silicon substrate 10.

Next, as shown in FIG. 4G, an n-type impurity such as arsenic (A
s ⁺ ) by ion implantation, the n ⁺
The mold source regions 16, 16 can be formed. Thereafter, BPSG is deposited and heated to form an interlayer insulating film 26, and further, a contact hole for taking out an electrode is formed. After that, a metal layer of aluminum or the like is formed by an ordinary film forming method, and etching is performed except for a necessary portion to form a wiring layer including the source electrode 24 and the drain electrode 22.

By the above steps, n according to the first embodiment is obtained.
The channel MOSFET 100 can be manufactured.
Note that the p-channel MOSFET can also be formed basically by the same process as the n-channel MOSFET.

Second Embodiment An example of an IGBT according to the present invention will be described with reference to FIG. The illustrated n-channel IGBT 200 includes:
A gate electrode 14 is formed on one surface of a silicon substrate 10 with a gate insulating film 12 interposed therebetween. Gate insulating film 1
For example, a silicon oxide film is used as 2, and an n ⁺ -type polycrystalline silicon film is used as the gate electrode 14, for example.

The silicon substrate 10 on both sides of the gate electrode 14
Includes a first conductivity type (n ⁺ type) emitter region 46a, a second conductivity type (n ⁺ type)
A conductive (p ⁺ ) emitter region 46b is formed. Around these emitter regions 46, second conductivity type (p ⁻ type) channel doped regions 48 are formed, respectively. The portion immediately below the gate electrode 14 in the channel dope region 48 forms a channel formation region 48a. The length and impurity concentration of the channel forming region 48a are set so as to obtain a predetermined threshold value.

As a characteristic configuration of the present invention, an insulating film 30 is provided at the lowermost end of the emitter region 46 and the channel dope region 48 in the depth direction. This insulating film 30 is formed so as to almost completely cover the region of the emitter region 46 and the channel dope region 48 in the main surface direction of the silicon substrate 10. By providing such an insulating film 30, an npn junction is not formed in the silicon substrate 10, and dielectric breakdown caused by a parasitic npn transistor can be prevented. In other words, the insulating film 30 covers the region immediately below the emitter region 46 and at least a part of the channel dope region 48 in order not to form an npn junction that may cause dielectric breakdown, and depletes the depletion from the end of the insulating film 30. The channel-doped region 18 is formed in consideration of the fact that the channel-doped region 18 is depleted from the layer so that current due to punch-through does not flow, and that the channel-doped region 18 is formed in a region that does not hinder the flow of drain current. This insulating film 30 is made of, for example, SiO ₂ , Si ₃ N ₄ or the like.

Since the magnitude of the emitter-collector breakdown voltage mainly depends on the thickness of the insulating film 30, the emitter-collector breakdown voltage is set so as to obtain a sufficient emitter-collector breakdown voltage in accordance with the type, standard, and application of the device. Is done.

A p ⁺ -type collector region 50 is formed on the other surface of the silicon substrate 10, and a collector electrode 52 is formed on the surface of the collector region 50.

In the IGBT 200, by controlling the voltage of the gate electrode 14, an n-channel is formed in the channel-doped region 48 immediately below the gate electrode 14, and electrons flow from the emitter region 46 to the collector region 50 through the channel. . Since holes are injected from collector region 50 correspondingly, n-type base region 10b
, Conductivity modulation occurs, and the on-resistance decreases. Therefore, the IGBT can be said to be a device more suitable for high breakdown voltage than the MOSFET.

Since the insulating film 30 is provided immediately below the emitter region 46 and the channel dope region 48, an npn junction having a low withstand voltage is not formed in the silicon substrate 10, and therefore, for example, is caused by current concentration by a parasitic npn transistor. Dielectric breakdown can be reliably prevented. Further, since the emitter-collector breakdown voltage can be sufficiently increased by forming the insulating film 30, the emitter-collector breakdown voltage can be secured by controlling the depth of the channel dope region and the impurity concentration as in the conventional IGBT. Need to be considered. As a result, the distance and the impurity concentration of the channel formation region 48a can be set independently of the breakdown voltage characteristics, and an appropriate threshold can be realized.

In the above-described IGBT, an n-channel I-type transistor in which the first conductivity type is n-type and the second conductivity type is p-type
Although the GBT has been described, the present invention sets the first conductivity type to p.
It is also possible to apply the present invention to a p-channel IGBT having an n-type and a second conductivity type.

Next, an example of a method for manufacturing the n-channel IGBT 200 will be described.

The basic structure of an n-channel IGBT is similar to that of an n-channel MOSFET. The basic difference between the two is that the MOSFET uses an n ⁺ -n ^- substrate while the p ⁺ -n ^- it is to have adopted the board. Therefore, the manufacturing processes after the substrate are basically similar to those of the MOSFET 100 described above. Specifically, it is as follows.

(A) First, as shown in FIG.
^An n ^-- type single-crystal silicon layer (second silicon layer) 10b is formed on a ⁺ -type single-crystal silicon substrate (first silicon layer) 10d by epitaxial growth. Then, FIG.
As shown in (B), a silicon oxide film 30a is formed on the n ⁻ -type silicon layer 10b by a normal thermal oxidation method or the like,
Further, as shown in FIG. 6C, the silicon oxide film 30a
Is removed by ordinary photolithography and reactive ion etching to perform patterning, thereby forming an insulating film 30.

Next, as shown in FIG. 7D, a normal solid phase epitaxy (SPE) method or the like, that is, for example, on the surface of the insulating film 30 and the surface of the n ⁻ -type single crystal silicon layer 10b,
For example, an amorphous silicon layer is deposited by a vapor deposition method or a CVD method in an ultra-high vacuum, and the single crystal silicon layer (third silicon layer) 10c is formed by performing epitaxial growth by heat treatment at about 600 ° C., for example.

Next, as shown in FIG. 7E, a silicon oxide film is formed on the surface of the single-crystal silicon layer 10c by a normal thermal oxidation method or the like, and subsequently, polysilicon is formed by a normal CVD method or the like. A film is formed. This is patterned by ordinary photolithography and reactive ion etching to form a gate insulating film 12 and a gate electrode 14. The polysilicon film forming the gate electrode 14 may include, for example, an n-type impurity by diffusion or ion implantation.
For example, phosphorus is doped and adjusted to a predetermined sheet resistance.

Next, as shown in FIG. 8 (F), for example, boron (B ⁺ ) is doped as a p-type impurity by ion implantation or the like, and then thermal diffusion is performed to form a p ⁻ -type channel doped region 48. In this step, the single-crystal silicon film 10c formed by solid-phase growth is converted into the n ⁻ -type single-crystal silicon
0b, the impurity concentration becomes substantially the same as that of the silicon layers 1
Ob and 10c are almost homogeneous. And the first
The substrate 10 is constituted by a stacked body of the silicon layer 10a, the second silicon layer 10b, and the third silicon layer 10c.

Next, as shown in FIG. 8G, an n-type impurity such as arsenic (A
s ⁺ ) by ion implantation, the n ⁺
The mold emitter region 46a can be formed. Also,
Similarly, the p ⁺ -type emitter region 46b can be formed by doping a p-type impurity, for example, boron (B ⁺ ). Thereafter, BPSG is deposited and heated to form an interlayer insulating film 26, and further, a contact hole for taking out an electrode is formed. After that, a metal layer of aluminum or the like is formed by an ordinary film forming method, and etching is performed except for a necessary portion to form a wiring layer including the emitter electrode 24 and the collector electrode 52.

By the above steps, n according to the second embodiment is obtained.
The channel IGBT 200 can be manufactured. Note that the p-channel IGBT can be formed by the same process as the n-channel IGBT.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications can be made within the scope of the present invention. For example, a layered structure of a substrate including a buffer layer, a portion including a Schottky junction in a part of a drain, a portion including a region of a conductivity type different from a main conductivity type in a portion of a drain, or the like can be used. In the above embodiment, the enhancement type device has been described. However, the present invention can be applied to a depletion type MOSFET and an IGBT by changing impurities in a channel formation region.

[0047]

According to the MOSFET of the present invention, since the insulating film is provided below the source region and the channel formation region, the channel formation region involved in the source-drain breakdown voltage and the threshold characteristics can be controlled independently. can do. Thus, an appropriate threshold value can be realized even when the withstand voltage between the source and the drain is increased.

Further, in the IGBT of the present invention, by providing an insulating film below the emitter region and the channel forming region, the breakdown voltage between the emitter and the collector and the threshold value can be controlled independently. This allows the emitter
Even when the withstand voltage between the collectors is increased, an appropriate threshold value can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically illustrating a structural example of an n-channel MOSFET according to the present invention.

FIGS. 2A to 2C are cross-sectional views schematically showing a manufacturing process of the MOSFET shown in FIG.

3 (D) and 3 (E) are cross-sectional views schematically showing steps of manufacturing a MOSFET performed following the process shown in FIG.

FIGS. 4 (F) and 4 (G) are cross-sectional views schematically showing a MOSFET manufacturing process performed subsequent to the process shown in FIG.

FIG. 5 is a cross-sectional view schematically showing a structural example of an n-channel IGBT according to the present invention.

6A to 6C are cross-sectional views schematically showing a manufacturing process of the IGBT shown in FIG.

7 (D) and 7 (E) are cross-sectional views schematically showing IGBT manufacturing steps performed subsequent to the process shown in FIG.

FIGS. 8F and 8G are cross-sectional views schematically showing a manufacturing process of the IGBT performed following the process shown in FIG. 7;

FIG. 9 is a cross-sectional view schematically showing a general structure of a conventional n-channel MOSFET.

DESCRIPTION OF SYMBOLS 10 silicon substrate 12 gate insulating film 14 gate electrode 16 n ⁺ type source region 18 p ⁻ type channel doping region 18 a channel forming region 20 n ⁺ type drain region 22 drain electrode 24 source electrode 26 interlayer insulating film 30 insulation Film 46a n ⁺ -type emitter region 46b p ⁺ -type emitter region 48 p ^-- type channel dope region 48a Channel formation region 50 p ⁺ -type collector region 52 Collector electrode 100 n-channel MOSFET 200 n-channel IGBT

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Susumu Sugiyama 41-1 Chukumi Yokomichi, Nagakute-cho, Aichi-gun, Aichi Prefecture Inside Toyota Central Research Laboratory Co., Ltd. (56) References (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (4)

(57) [Claims] (A) a first functioning as a drain region;
Forming a second silicon layer having an impurity concentration lower than that of the first silicon layer on the silicon layer; (b) forming an insulating film on the second silicon layer, followed by photolithography and etching (C) forming a silicon layer continuously on the surface of the insulating film and the exposed second silicon layer, and forming a third layer continuous with the second silicon layer. Forming a silicon layer, (d) laminating a gate insulating film and a gate electrode on the third silicon layer, (e) forming a channel-doped region by doping impurities, and It includes the step, forming a source region of impurities by doping f) the gate electrode as a mask, wherein in the step (b), the insulating film, the source Scan territory
Region and the lower end of the channel dope region in the depth direction.
The source region and the channel dope
Aspect of the silicon substrate, including at least a part of a region
Characterized by being formed along the direction of the region
A method for manufacturing an S-type semiconductor device. 2. The semiconductor device according to claim 1, wherein said insulating film is formed in said source region and said channel region.
Cover area in the surface direction of the silicon substrate.
MOS type semiconductor characterized by being formed in a state where
Manufacturing method of body device. 3. (a) a first functioning as a collector region
Forming a second silicon layer having an impurity concentration lower than that of the first silicon layer on the silicon layer; (b) forming an insulating film on the second silicon layer, and then performing photolithography and etching (C) forming a silicon layer continuously on the surface of the insulating film and the exposed second silicon layer, and forming a third silicon layer continuous with the second silicon layer. Forming a layer, (d) laminating a gate insulating film and a gate electrode on the third silicon layer, (e) forming a channel doped region by doping impurities, and (f) ) a step of forming an emitter region an impurity doped with the gate electrode as a mask, wherein in the step (b), the insulating film, the emitter
Region and the lower end of the channel dope region in the depth direction.
Located and the emitter region and channel
Including at least a portion of a loop region of the silicon substrate.
Characterized by being formed along the area in the plane direction
A method for manufacturing a MOS / bipolar composite semiconductor device. 4. The semiconductor device according to claim 3, wherein the insulating film comprises the emitter region and the channel region.
Of the silicon substrate in the plane direction of the silicon substrate.
MOS / bar formed in a state where the MOS / bar
A method for manufacturing an bipolar composite semiconductor device.