CN115440879B - Superconductive silicon wafer and preparation method thereof - Google Patents
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- CN115440879B CN115440879B CN202210685143.5A CN202210685143A CN115440879B CN 115440879 B CN115440879 B CN 115440879B CN 202210685143 A CN202210685143 A CN 202210685143A CN 115440879 B CN115440879 B CN 115440879B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 112
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 112
- 239000010703 silicon Substances 0.000 title claims abstract description 112
- 238000002360 preparation method Methods 0.000 title claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 37
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 238000010884 ion-beam technique Methods 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 89
- 238000005516 engineering process Methods 0.000 description 7
- 230000003287 optical effect Effects 0.000 description 5
- 235000010675 chips/crisps Nutrition 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000012512 characterization method Methods 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000009623 Bosch process Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/52—Controlling or regulating the coating process
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/24—Vacuum evaporation
- C23C14/28—Vacuum evaporation by wave energy or particle radiation
- C23C14/30—Vacuum evaporation by wave energy or particle radiation by electron bombardment
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/54—Controlling or regulating the coating process
- C23C14/541—Heating or cooling of the substrates
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
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Abstract
The invention discloses a superconductive silicon wafer and a preparation method thereof. The preparation method comprises the following steps: providing a silicon wafer with a through hole, wherein the silicon wafer comprises a first surface and a second surface which are oppositely arranged; depositing a superconducting material from the first surface of the silicon wafer at a first temperature to plate a first layer of superconducting film on the first surface of the silicon wafer and the hole wall of the through hole; at a second temperature higher than the first temperature, a superconducting material is deposited from the second surface of the silicon wafer to plate a second layer of superconducting film on the second surface of the silicon wafer, the second layer of superconducting film being continuous with the first layer of superconducting film. The superconductive silicon wafer is obtained by adopting the preparation method. By the mode, the superconductive film can be prevented from being damaged, and the two surfaces of the silicon wafer are reliably connected in a superconductive mode.
Description
Technical Field
The invention relates to the technical field of superconducting circuits, in particular to a superconducting silicon wafer and a preparation method thereof.
Background
Through silicon via (Through Silicon Via, TSV) technology is considered to be the most promising technology for achieving three-dimensional integration. The through silicon via technology realizes direct interconnection between chips by making vertical vias between chips, wafers and wafers. The chip stacking structure can enable the density of chips stacked in the three-dimensional direction to be maximum, the interconnection lines among the chips to be shortest, the overall dimension to be minimum, the chip speed to be obviously improved, and the chip power consumption to be reduced, so that the chip stacking structure becomes the most attractive technology in the current electronic packaging technology.
The superconducting quantum chip is widely used in the through silicon via technology because of high requirements for power consumption. In order to realize the superconducting connection of the upper surface and the lower surface of the silicon wafer, the prior manufacturing process is to place the silicon wafer on a carrying platform and deposit superconducting materials on the upper surface of the silicon wafer once to form a superconducting film, but because the lower surface of the silicon wafer is attached to the carrying platform and the precursor can only grow near the through hole on the lower surface of the silicon wafer, the superconducting film on the lower surface of the silicon wafer is incomplete and discontinuous to be damaged. As shown in fig. 1, a mirror image of the lower surface of a silicon wafer in the existing manufacturing process is shown, a circle of black edges appears at the periphery of a through hole array, and the black edges are caused by damage of a superconducting film, as shown in fig. 2, an SEM characterization image of the lower surface of the silicon wafer in the existing manufacturing process is shown, and it can be seen that the damage of the superconducting film appears at a plurality of places on the lower surface of the silicon wafer (the positions encircled by dotted lines in the drawing). It is difficult to form a superconducting connection by performing only one deposition of superconducting material in the existing manufacturing process.
Disclosure of Invention
The invention aims to provide a superconducting silicon wafer and a preparation method thereof, which are used for solving the problem that superconducting connection is difficult to form in the prior art, and avoiding damage to a superconducting film so as to form reliable superconducting connection on two surfaces of the silicon wafer.
In order to solve the technical problems, the invention provides a preparation method of a superconductive silicon wafer, which comprises the following steps:
providing a silicon wafer with a through hole, wherein the silicon wafer comprises a first surface and a second surface which are oppositely arranged;
depositing a superconducting material from the first surface of the silicon wafer at a first temperature to plate a first layer of superconducting film on the first surface of the silicon wafer and the hole wall of the through hole;
and depositing superconducting material from the second surface of the silicon wafer at a second temperature higher than the first temperature to plate a second layer of superconducting film connected with the first layer of superconducting film on the second surface of the silicon wafer.
Preferably, the thickness of the first layer superconducting film is the same as that of the second layer superconducting film.
Preferably, the first layer superconducting film is obtained by an atomic layer deposition method or a chemical vapor deposition method.
Preferably, the second layer superconducting film is obtained by a magnetron sputtering method or an electron beam evaporation method.
Preferably, the first temperature is lower than 50 ℃, and the second temperature is 300-800 ℃.
Preferably, before the step of depositing superconducting material from the second surface of the silicon wafer at the second temperature, the preparation method further comprises:
and removing the oxide layer on the surface of the first layer superconducting film on the second surface of the silicon wafer.
Preferably, the oxide layer is removed by ion beam etching.
Preferably, the superconducting material includes at least one of aluminum, titanium nitride, indium, niobium nitride, and tantalum.
Preferably, the hole wall of the through hole is vertical or inclined relative to the first surface.
In order to solve the technical problems, the invention also provides a superconductive silicon wafer obtained by the preparation method according to any one of the above.
Compared with the prior art, the preparation method of the superconductive silicon wafer provided by the invention is characterized in that firstly, at a first temperature, a superconductive material is deposited from the first surface of the silicon wafer, so that a first layer of superconductive film is plated on the first surface of the silicon wafer and the hole wall of the through hole, then, at a second temperature higher than the first temperature, a superconductive material is deposited from the second surface of the silicon wafer, so that a second layer of superconductive film connected with the first layer of superconductive film is plated on the second surface of the silicon wafer, the compatibility between the two deposited superconductive films can be improved, and the first layer of superconductive film and the second layer of superconductive film can be fused into a whole, so that the occurrence of damage of the superconductive film can be avoided, and the two surfaces of the silicon wafer form reliable superconductive connection.
The superconductive silicon wafer provided by the invention is prepared according to the preparation method, and belongs to the same inventive concept as the preparation method, so that the superconductive silicon wafer has the same beneficial effects and is not repeated herein.
Drawings
FIG. 1 is a schematic view of a lower surface of a silicon wafer in a conventional fabrication process.
Fig. 2 is an SEM characterization of the lower surface of a silicon wafer in the prior art.
Fig. 3 is a schematic flow chart of a preparation method of a superconductive silicon wafer according to an embodiment of the present invention.
Fig. 4 is a schematic structural view of a silicon wafer having a through hole.
Fig. 5 is a schematic diagram of a process for preparing a superconducting film.
Fig. 6 is a low magnification optical chart of a second surface of a superconductive silicon wafer obtained by the preparation method according to the embodiment of the present invention.
Fig. 7 is a high magnification optical chart of a second surface of a superconductive silicon wafer obtained by the preparation method according to the embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
Referring to fig. 3, an embodiment of the present invention provides a preparation method of a superconductive silicon wafer, which includes the following steps:
s11: a silicon wafer having a through hole is provided, the silicon wafer including oppositely disposed first and second surfaces.
The through silicon via technology directly interconnects the circuit on the upper surface of the silicon chip and the circuit on the lower surface of the silicon chip, so that the wiring length is greatly shortened, and the signal delay and loss are reduced.
The wafers are typically quite thick, with standard thicknesses of through-hole wafers ranging from 100 microns to 300 microns, but for special requirements, some wafers are typically more than 400 microns thick. The through-holes in the silicon wafer may be made using a Bosch process.
As shown in fig. 4, is a silicon wafer having a through hole. The silicon chip 1 is provided with through holes 2 which are arranged in an array. The upwardly facing surface in the figure is the first surface of the silicon wafer 1 and the downwardly facing surface in the figure is the second surface of the silicon wafer 1. The present invention does not limit the shape of the hole wall of the through hole 2, and in this embodiment, the hole wall of the through hole 2 may be perpendicular or inclined with respect to the first surface.
It should be noted that, the first surface and the second surface are relatively, and any surface of the silicon wafer may be selected as the first surface, and then the other surface is the second surface.
S12: at a first temperature, a superconducting material is deposited from a first surface of the silicon wafer to plate a first layer of superconducting film on the first surface of the silicon wafer and the walls of the through holes.
When the superconducting material is deposited on the first surface of the silicon wafer, the superconducting material is deposited on the first surface of the silicon wafer and the hole wall of the through hole, and finally, a film is coated on the first surface of the silicon wafer and the hole wall of the through hole.
S13: at a second temperature higher than the first temperature, a superconducting material is deposited from the second surface of the silicon wafer to plate a second layer of superconducting film on the second surface of the silicon wafer, the second layer of superconducting film being continuous with the first layer of superconducting film.
When the superconducting material is deposited on the second surface of the silicon wafer, the first layer of superconducting film is already present near the through hole and influenced by the first layer of superconducting film, the superconducting material is only deposited on the second surface of the silicon wafer, and the deposited superconducting material and the first layer of superconducting film have strong compatibility, namely, the second layer of superconducting film plated on the second surface of the silicon wafer and the first layer of superconducting film are connected, namely, are integrated.
In order to ensure that the superconducting films formed twice are continuous and have a constant thickness, in this embodiment, the thicknesses of the first layer superconducting film and the second layer superconducting film are the same. The thickness of the first layer of superconducting film is the same as that of the second layer of superconducting film by adjusting the technological parameters of twice deposition of superconducting materials.
Illustratively, in the present embodiment, the first layer superconducting film is obtained by an atomic layer deposition method or a chemical vapor deposition method.
As shown in fig. 5 (base:Sub>A), which isbase:Sub>A schematic cross-sectional view in the directionbase:Sub>A-base:Sub>A shown in fig. 4, the silicon wafer 1 is placed onbase:Sub>A stage with the first surface 1base:Sub>A of the silicon wafer 1 facing upward before the deposition of the superconducting material. As shown in fig. 5 (B), which is a schematic diagram of plating the silicon wafer shown in fig. 5 (a) with the first layer of superconducting film, when the superconducting material is deposited by the atomic layer deposition method or the chemical vapor deposition method at the first temperature, the superconducting material is deposited on the first surface 1A of the silicon wafer 1 and the hole wall of the through hole 2, and grows near the through hole 2 on the second surface 1B of the silicon wafer 1, and finally the first layer of superconducting film is plated near the first surface 1A of the silicon wafer 1, the hole wall of the through hole 2, and the through hole 2 on the second surface 1B of the silicon wafer 1.
Further, in this embodiment, the second layer superconducting film is obtained by a magnetron sputtering method or an electron beam evaporation method. Specifically, the first temperature is lower than 50 ℃, and the second temperature is 300-800 ℃.
When the superconducting material is deposited by a magnetron sputtering method or an electron beam evaporation method, the silicon wafer 1 needs to be turned over first. As shown in fig. 5 (c), which is a schematic diagram of the silicon wafer shown in fig. 5 (B) after being turned over, the turned-over silicon wafer 1 is placed on a carrier, and the second surface 1B of the silicon wafer 1 faces upward. As shown in fig. 5 (d), which is a schematic diagram of plating the second layer of superconducting film on the silicon wafer shown in fig. 5 (c), sputtering the superconducting material on the second surface 1B of the silicon wafer 1 at the second temperature, growing the superconducting material on the second surface 1B of the silicon wafer 1, fusing with the first layer of superconducting film, and finally plating the second layer of superconducting film continuing with the first layer of superconducting film on the second surface 1B of the silicon wafer 1.
In some application scenarios, since the surface of the superconducting film is easily oxidized after formation, an oxide layer is easily generated on the surface of the first layer superconducting film, and this oxide layer may hinder the fusion of the second layer superconducting film and the first layer superconducting film. In this embodiment, the step of depositing superconducting material from the second surface of the silicon wafer at the second temperature, i.e., before step S13, the preparation method further includes:
s131: and removing the oxide layer on the surface of the first layer of superconducting film on the second surface of the silicon wafer.
The second layer of superconducting film is only formed on the second surface of the silicon wafer, so that only the oxide layer on the surface of the first layer of superconducting film on the second surface of the silicon wafer is required to be removed. The oxide layer may be removed using Ion Beam Etching (IBE).
In some embodiments, the superconducting material is a material exhibiting superconducting properties at or below a critical temperature, including at least one of aluminum, titanium nitride, indium, niobium nitride, tantalum, but the present invention is not limited thereto, and other materials exhibiting superconducting properties at or below a critical temperature may be used.
Compared with the prior art that the superconducting material is deposited once, the method comprises the steps of firstly depositing the superconducting material from the first surface of the silicon wafer at a first temperature to plate a first layer of superconducting film on the first surface of the silicon wafer and the hole wall of the through hole, then depositing the superconducting material from the second surface of the silicon wafer at a second temperature higher than the first temperature to plate a second layer of superconducting film connected with the first layer of superconducting film on the second surface of the silicon wafer, and the method can improve the compatibility between the two deposited superconducting films, and the first layer of superconducting film and the second layer of superconducting film can be integrated, so that the damage of the superconducting films can be avoided, and the two surfaces of the silicon wafer form reliable superconducting connection.
The embodiment of the invention also provides a superconducting silicon wafer, which is obtained by adopting the preparation method of the superconducting silicon wafer in the previous embodiment.
The second surface of the superconducting silicon wafer in this embodiment is subjected to optical inspection, and the inspection result is shown in fig. 6 and 7, where the optical magnification of fig. 6 is x30.0, it can be seen that no black edge appears on the periphery of the through hole array, and the optical magnification of fig. 7 is x200.0, it can be seen that the superconducting film on the second surface of the superconducting silicon wafer is complete and continuous, and no damage to the superconducting film appears. Therefore, the two surfaces of the superconducting silicon wafer of the present embodiment can realize reliable superconducting connection.
In the description of the present specification, a description of the terms "one embodiment," "some embodiments," "examples," or "particular examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (10)
1. The preparation method of the superconducting silicon wafer is characterized by comprising the following steps:
providing a silicon wafer with a through hole, wherein the silicon wafer comprises a first surface and a second surface which are oppositely arranged;
depositing a superconducting material from a first surface of the silicon wafer at a first temperature to plate a first layer of superconducting film near the first surface of the silicon wafer, the walls of the through holes and the through holes of the second surface;
and depositing superconducting material from the second surface of the silicon wafer at a second temperature higher than the first temperature to plate a second layer of superconducting film connected with the first layer of superconducting film on the second surface of the silicon wafer.
2. The method of manufacturing according to claim 1, wherein the first layer superconducting film and the second layer superconducting film have the same thickness.
3. The method according to claim 1 or 2, wherein the first layer superconducting film is obtained by an atomic layer deposition method or a chemical vapor deposition method.
4. The method according to claim 3, wherein the second superconducting film is obtained by a magnetron sputtering method or an electron beam evaporation method.
5. The method according to claim 4, wherein the first temperature is lower than 50 ℃ and the second temperature is 300 to 800 ℃.
6. A method of preparing as claimed in claim 3 wherein prior to the step of depositing superconducting material from the second surface of the silicon wafer at the second temperature, the method of preparing further comprises:
and removing the oxide layer on the surface of the first layer superconducting film on the second surface of the silicon wafer.
7. The method of claim 6, wherein the oxide layer is removed by ion beam etching.
8. The method of claim 1, wherein the superconducting material comprises at least one of aluminum, titanium nitride, indium, niobium nitride, tantalum.
9. The method of claim 1, wherein the walls of the through-holes are perpendicular or oblique to the first surface.
10. A superconductive silicon wafer obtainable by the process according to any one of claims 1 to 9.
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| CN202210685143.5A CN115440879B (en) | 2022-06-16 | 2022-06-16 | Superconductive silicon wafer and preparation method thereof |
| PCT/CN2023/085556 WO2023186119A1 (en) | 2022-04-02 | 2023-03-31 | Superconducting silicon wafer and preparation method therefor |
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| JPH079905B2 (en) * | 1987-07-15 | 1995-02-01 | シャープ株式会社 | Wiring method for semiconductor device |
| JP2004259752A (en) * | 2003-02-24 | 2004-09-16 | Fujitsu Ltd | Electronic device and method of manufacturing same |
| CN102270603B (en) * | 2011-08-11 | 2013-12-04 | 北京大学 | Manufacturing method of silicon through hole interconnect structure |
| CN102931339A (en) * | 2012-11-02 | 2013-02-13 | 西南交通大学 | Superconducting switch with two-sided yttrium barium copper oxide (YBCO) thin film structure |
| US10658424B2 (en) * | 2015-07-23 | 2020-05-19 | Massachusetts Institute Of Technology | Superconducting integrated circuit |
| US11617272B2 (en) * | 2016-12-07 | 2023-03-28 | D-Wave Systems Inc. | Superconducting printed circuit board related systems, methods, and apparatus |
| US11276727B1 (en) * | 2017-06-19 | 2022-03-15 | Rigetti & Co, Llc | Superconducting vias for routing electrical signals through substrates and their methods of manufacture |
| US11088310B2 (en) * | 2019-04-29 | 2021-08-10 | International Business Machines Corporation | Through-silicon-via fabrication in planar quantum devices |
| CN214378496U (en) * | 2021-03-09 | 2021-10-08 | 合肥本源量子计算科技有限责任公司 | Quantum chip |
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