JPH079905B2 - Wiring method for semiconductor device - Google Patents
Wiring method for semiconductor deviceInfo
- Publication number
- JPH079905B2 JPH079905B2 JP62176220A JP17622087A JPH079905B2 JP H079905 B2 JPH079905 B2 JP H079905B2 JP 62176220 A JP62176220 A JP 62176220A JP 17622087 A JP17622087 A JP 17622087A JP H079905 B2 JPH079905 B2 JP H079905B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- superconducting material
- semiconductor
- temperature superconducting
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 238000000034 method Methods 0.000 title claims description 17
- 239000000463 material Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 13
- 239000013078 crystal Substances 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 10
- 239000010408 film Substances 0.000 description 8
- 238000000137 annealing Methods 0.000 description 6
- 238000005224 laser annealing Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 229910002367 SrTiO Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910002480 Cu-O Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000012768 molten material Substances 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 239000002887 superconductor Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76891—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by using superconducting materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53285—Conductive materials containing superconducting materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0268—Manufacture or treatment of devices comprising copper oxide
- H10N60/0661—Processes performed after copper oxide formation, e.g. patterning
- H10N60/0688—Etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0884—Treatment of superconductor layers by irradiation, e.g. ion-beam, electron-beam, laser beam or X-rays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Optics & Photonics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】 ＜産業上の利用分野＞ 本発明は、半導体装置の配線方法の改良に関するもので
ある。The present invention relates to an improvement in a wiring method for a semiconductor device.
＜従来の技術＞ 最近の半導体技術の進展はめざましく、特にシリコン
（Si）LSI技術を先導するDRAMでは間もなく4M DRAMが
実用化されようとしている。これら超LSIはMOSデバイス
を基礎とし、微細加工技術のレベルとしても２μｍから
１μｍ近傍の技術を用いており、すでにサブミクロン領
域の議論も盛んである。微細化は、高集積化，高密度化
を実現する手段として追求されてきたが、必然的にMOS
デバイスの高性能化，高速化をもたらし、従来バイポー
ラデバイスの領域と考えられた1ns以下のゲート遅延時
間も実用化の段階にある。しかしMOSデバイスの遅延時
間としてはゲート遅延時間以外にも入出力部での遅延，
内部配線での遅延などがあげられるが、特に内部配線で
の遅延は高集積化に伴うチップ寸法の増大とともに増加
し、MOSデバイスの実効的な高速化を妨げることにな
る。<Prior art> Recent progress in semiconductor technology is remarkable, and 4M DRAM is about to be put to practical use soon in DRAM, which leads silicon (Si) LSI technology in particular. These VLSIs are based on MOS devices and use technologies in the range of 2 μm to 1 μm as the level of microfabrication technology, and discussions in the submicron region are already active. Miniaturization has been pursued as a means of achieving high integration and high density, but inevitably MOS
The device has achieved higher performance and higher speed, and the gate delay time of 1 ns or less, which was previously considered to be the area of bipolar devices, is in the stage of practical application. However, the delay time of the MOS device is not only the gate delay time but also the delay at the input / output unit.
There are delays in the internal wiring. Especially, the delay in the internal wiring increases with an increase in the chip size accompanying the high integration, which hinders the effective speedup of the MOS device.
同様の問題はSi LSI以上の高速動作を期待されているG
aAS LSIにも存在する。またGaAsのばあいにはSiにくら
べて低電圧，大電流駆動であるため、配線抵抗による配
線（特に電源線などの大きな電流がながれる配線）の電
位上昇（降下）が生じやすく、特性の低下をまねく。A similar problem is expected to operate at higher speeds than Si LSI.
It also exists in aAS LSI. Also, in the case of GaAs, since it is driven at a lower voltage and a larger current than Si, the potential of the wiring (especially the wiring through which a large current such as the power supply line can flow) is likely to rise (fall) due to wiring resistance, and the characteristics deteriorate. Imitate.
そこで、配線材料を金属からある条件のもとで電気抵抗
が０になる超伝導物質に代えることが検討されはじめて
いる。Therefore, it is beginning to be considered to replace the wiring material with a superconducting material which has an electric resistance of 0 under certain conditions.
＜発明が解決しようとする問題点＞ 現在、半導体の配線材料に検討されているのは電気抵抗
が０になる臨界温度が液体窒素温度（77K）付近あるい
はそれ以上の高温領域にある高温超伝導材料（例えばＹ
−Ba−Cu−Ｏ系など）である。<Problems to be Solved by the Invention> Currently, a semiconductor wiring material is being investigated, which is a high-temperature superconducting material whose critical temperature at which electric resistance becomes zero is in a high temperature region near liquid nitrogen temperature (77K) or higher. Material (eg Y
-Ba-Cu-O system).
しかしこの高温超伝導材料は、一般に1000℃近い高温で
数時間の焼結を行わなければ超伝導の特性を示さない。
しかし、半導体基板にはすでにトランジスタが形成され
ているため、このような熱処理を行うことはできない。
熱によりトランジスタが劣化したり破壊されたりするか
らである。However, this high-temperature superconducting material generally does not exhibit superconducting properties unless it is sintered at a high temperature close to 1000 ° C. for several hours.
However, such a heat treatment cannot be performed because the transistor is already formed on the semiconductor substrate.
This is because the transistor is deteriorated or destroyed by heat.
すなわち、高温超伝導材料により半導体の配線を形成
し、配線抵抗を０にするためには材料の蒸着時またはそ
の後の熱処理温度を低温化（半導体基板の種類により異
なるが、400℃程度が望ましい）することが必要であ
る。That is, in order to form a semiconductor wiring with a high-temperature superconducting material and to reduce the wiring resistance to zero, the heat treatment temperature during or after the vapor deposition of the material is lowered (depending on the type of semiconductor substrate, about 400 ° C is desirable). It is necessary to.
半導体基板上へ高温超伝導材料を薄膜状に形成する方法
として有望視されていたスパッタリング法やMBE法は、
結晶方向をそろえることに関しては極めて優れた技術で
あるが、いずれも800℃程度に基板を加熱しながら蒸着
を行うため、低温化の点では充分ではなく、トランジス
タが劣化・破壊される恐れがある。The sputtering method and MBE method, which have been promising as a method for forming a high-temperature superconducting material in a thin film on a semiconductor substrate, are
It is an extremely excellent technique for aligning the crystal directions, but in both cases, evaporation is performed while heating the substrate to about 800 ° C, so it is not sufficient in terms of lowering the temperature, and there is a risk that the transistor will deteriorate or be destroyed. .
本発明は、上記の点に鑑みて創案されたものであり、層
間絶縁膜上に超伝導材料よりなる配線を行なうに際し
て、下層のトランジスタ等に劣化・破壊を生じさせない
新規な半導体装置の配線方法を提供することを目的とし
ている。The present invention was devised in view of the above points, and when a wiring made of a superconducting material is formed on an interlayer insulating film, a novel wiring method for a semiconductor device that does not cause deterioration or destruction of a transistor or the like in the lower layer. Is intended to provide.
＜問題点を解決するための手段及び作用＞ 上記の目的を達成するため、本発明の半導体装置の配線
方法は、半導体基板上に形成された層間絶縁膜上に高温
超伝導材料を被着してエネルギービームを照射して超伝
導特性を持たせると同時に結晶方向を揃えるような熱処
理を行い所望の配線に加工する工程と、上記配線の所定
部位を除去してコンタクトホールを形成する工程と、上
記コンタクトホール内に電流経路となる金属を形成する
工程とを含んでなるように構成している。<Means and Actions for Solving Problems> In order to achieve the above object, a wiring method for a semiconductor device according to the present invention is a method of depositing a high temperature superconducting material on an interlayer insulating film formed on a semiconductor substrate. A step of irradiating an energy beam to give a superconducting property and at the same time heat-treating so as to align the crystal direction to form a desired wiring; and a step of removing a predetermined portion of the wiring to form a contact hole, And a step of forming a metal serving as a current path in the contact hole.
即ち、本発明になる高温超伝導材料による半導体配線の
形成方法では、低温で蒸着された高温超伝導材料をレー
ザ，電子線等の照射によってアニールすることにより超
伝導特性を持たせると同時に結晶方向をそろえ、かつレ
ーザー，電子線等の照射によるアニールの性質上トラン
ジスタ等を劣化・破壊しないこと、及び高温超伝導体材
料からなる配線に有効に電流を流すことができることに
着目して上記の問題点を解決している。That is, in the method for forming a semiconductor wiring using a high-temperature superconducting material according to the present invention, the high-temperature superconducting material deposited at a low temperature is annealed by irradiation with a laser, an electron beam, or the like so as to have superconducting properties and at the same time have a crystallographic The above problems, focusing on the fact that transistors, etc. are not deteriorated or destroyed due to the nature of annealing by irradiation with laser, electron beam, etc. and that current can be effectively passed through wiring made of high temperature superconductor material. The point is solved.
＜実施例＞ 以下、本発明の実施例について図面を用いて詳細に説明
する。<Example> Hereinafter, an example of the present invention is described in detail using a drawing.
なお、簡単化のため２本の第１層配線を高温超伝導材料
により配線する場合を例とし、必要以外のものは図示し
ないことにする。For simplification, the case where two first layer wirings are made of a high-temperature superconducting material will be taken as an example, and elements other than necessary are not shown.
第１図(a)乃至(f)は、それぞれ本発明の一実施例として
の半導体装置の配線方法の各工程を示す図である。FIGS. 1 (a) to 1 (f) are diagrams showing respective steps of a wiring method for a semiconductor device as an embodiment of the present invention.
第１図(a)において、11は半導体基板であり、この半導
体基板11上には従来公知の方法により第１層配線12,13
が形成されており、また半導体層にトランジスタ等の能
動素子（図示せず）が形成されている。次にこのような
構造の基板上に層間絶縁膜14（CVD法によるSiO2など）
を適当な厚さ被着し、第１層配線と第２層配線を接続す
るためのスルー・ホールを開口する（第１図(b)）。こ
の層間絶縁膜14の厚さは、後で述べるレーザー・アニー
ル時に高温超伝導材料に充分な熱を供給し、かつ下層の
トランジスタには劣化，破壊を起こさせない程度の熱し
か伝えない厚さに設定する。（従って最適膜厚の範囲
は、アニール条件≪波長・照射強度・照射時間など≫に
より変化する。）なお、本実施例ではこのスルー・ホー
ルは金属16で埋め込むようにしているが、プロセスの組
み立てによっては開口するだけでも良い。In FIG. 1 (a), 11 is a semiconductor substrate, and on this semiconductor substrate 11, first-layer wirings 12, 13 are formed by a conventionally known method.
And an active element (not shown) such as a transistor is formed in the semiconductor layer. Next, the interlayer insulating film 14 (such as SiO 2 by the CVD method) is formed on the substrate having such a structure.
To a suitable thickness, and a through hole for connecting the first layer wiring and the second layer wiring is opened (FIG. 1 (b)). The thickness of the interlayer insulating film 14 is such that it can supply sufficient heat to the high-temperature superconducting material during laser annealing described later, and can transfer heat only to the extent that it does not cause deterioration or destruction to the underlying transistor. Set. (Therefore, the range of the optimum film thickness changes depending on the annealing conditions << wavelength / irradiation intensity / irradiation time >>.) In this embodiment, the through holes are filled with metal 16, but the process is assembled. Depending on the case, it may be just opened.
次に、第１図(c)に示すように、高温超伝導材料15をス
パッタ法,EB蒸着法，抵抗加熱蒸着法など任意の方法に
より半導体基板11の全面に被着する。このとき基板11を
加熱する必要は無い。ただし、レーザー・アニール後に
超伝導特性がえられるような組成比で蒸着しておく。
（この比率もアニール条件により変化する。） 続いてレーザー・アニールにより半導体基板11の前面に
被着した高温超伝導材料15を熱処理し、超伝導特性を持
たせると同時に結晶方向を揃える。これはレーザー照射
等のアニールの特性を利用した方法である。すなわち、
レーザー・アニールではns単位の短時間照射が容易であ
り、過熱冷却の全工程をμｓ単位の時間内で終えること
ができ、固体材料中での不純物原子の拡散などの遅い現
象はおこさせずに熔融材料中での不純物原子の拡散，偏
析，結晶成長などの速い現象は充分に追随させることが
できる。この時、熔融層の結晶化，結晶軸方向は一般に
アニール条件のみにより決めることができ、下地の結晶
性に依存しない。さらに、層間絶縁膜14の膜厚をアニー
ル条件に対して最適化することにより、下層のトランジ
スタ等を劣化・破壊することなく以上の結晶化を行う事
ができる。Next, as shown in FIG. 1 (c), a high temperature superconducting material 15 is deposited on the entire surface of the semiconductor substrate 11 by an arbitrary method such as a sputtering method, an EB evaporation method, a resistance heating evaporation method. At this time, it is not necessary to heat the substrate 11. However, vapor deposition is performed after the laser annealing at a composition ratio so that superconducting properties can be obtained.
(This ratio also changes depending on the annealing conditions.) Subsequently, the high temperature superconducting material 15 deposited on the front surface of the semiconductor substrate 11 is heat-treated by laser annealing so as to have superconducting properties and at the same time align the crystal directions. This is a method utilizing the characteristics of annealing such as laser irradiation. That is,
In laser annealing, short-time irradiation of ns unit is easy, and the whole process of superheat cooling can be completed within μs unit time, without causing slow phenomenon such as diffusion of impurity atoms in solid material. Fast phenomena such as impurity atom diffusion, segregation, and crystal growth in the molten material can be sufficiently followed. At this time, the crystallization of the molten layer and the crystal axis direction can generally be determined only by the annealing conditions, and do not depend on the crystallinity of the base. Further, by optimizing the film thickness of the interlayer insulating film 14 with respect to the annealing conditions, the above crystallization can be performed without degrading or destroying the underlying transistor or the like.
最後に第１図(d)に示すように不要な高温超伝導材料15
をエッチングにより除去し、半導体配線を完成する。Finally, as shown in Fig. 1 (d), unnecessary high-temperature superconducting material 15
Are removed by etching to complete the semiconductor wiring.
上記の工程により超伝導材料により電気抵抗がある条件
の下で０になる半導体配線を形成することができる。Through the above steps, a semiconductor wiring can be formed of a superconducting material which has an electric resistance of 0 under certain conditions.
上記の実施例に次のような工夫を行うと、本発明は更に
有効になる。The present invention will be more effective if the following device is applied to the above-described embodiment.
高温超伝導材料は例えば第２図に示すような結晶構
造を有しており、このような結晶構造上の理由によりａ
軸方向の伝導が支配的であるため、半導体配線も第３図
に示すように電流の流れる方向Ａをａ軸方向にしておく
ことが望ましい。したがって本発明のより好ましい実施
例においては、第１図(e)に示すように超伝導材料によ
る配線15の形成後、スルーホール上の配線を一部分エッ
チングし金属17を蒸着することによりコンタクトを水平
方向（ａ軸方向）から形成する。このように構成するこ
とにより超伝導は主としてａ軸方向に起こるので、電流
をより有効に配線15へ流すことができる。The high temperature superconducting material has, for example, a crystal structure as shown in FIG. 2, and because of such a crystal structure, a
Since the conduction in the axial direction is dominant, it is desirable that the semiconductor wiring also has the current flowing direction A in the a-axis direction as shown in FIG. Therefore, in a more preferred embodiment of the present invention, as shown in FIG. 1 (e), after forming the wiring 15 made of a superconducting material, the wiring on the through hole is partially etched and metal 17 is vapor-deposited to make the contact horizontal. It is formed from the direction (a-axis direction). With this structure, superconductivity mainly occurs in the a-axis direction, so that the current can be more effectively supplied to the wiring 15.
第１図(f)に示すように超伝導材料15の蒸着時に、
まずSrTiO3などべつのペロブスカイト系の物質18を蒸着
しておくことにより、レーザーアニール時の結晶化など
を容易にする。なお、SrTiO3は超伝導物質であるが臨界
温度が低い（〜30K）ため液体窒素温度（〜77K）で用い
るときには抵抗が高くなるため、の方法と併用するこ
とが望ましい。As shown in FIG. 1 (f), when depositing the superconducting material 15,
First, another perovskite-based substance 18 such as SrTiO 3 is vapor-deposited to facilitate crystallization during laser annealing. Although SrTiO 3 is a superconducting substance, it has a low critical temperature (up to 30 K) and therefore has a high resistance when used at liquid nitrogen temperature (up to 77 K).
＜発明の効果＞ 以上詳述したように本発明によれば、下層のトランジス
タなどの劣化，破壊を起こすことなく超伝導材料により
ある条件下で電気抵抗が０になる半導体配線を形成する
ことができ、電気抵抗が原因となって半導体の特性を低
下させている現象（配線遅延など）を解消することがで
きる。<Effects of the Invention> As described in detail above, according to the present invention, it is possible to form a semiconductor wiring having an electric resistance of 0 under a certain condition by a superconducting material without causing deterioration or destruction of a transistor in a lower layer. Therefore, it is possible to eliminate the phenomenon (wiring delay, etc.) that deteriorates the characteristics of the semiconductor due to the electric resistance.
さらに、結晶方向が揃った高温超伝導材料からなる配線
へのコンタクトを水平方向から形成したので、電流を有
効に配線に流すことができる。Further, since the contact to the wiring made of the high temperature superconducting material having the uniform crystallographic direction is formed from the horizontal direction, the current can be effectively passed through the wiring.
第１図(a)乃至(f)はそれぞれ本発明の一実施例としての
半導体装置の配線方法の各工程を示す図、第２図は高温
超伝導材料の結晶構造の一例を模式的に示す図、第３図
は高温超伝導材料の結晶方位と半導体装置の配線方位と
の関係を説明するための図である。 11……半導体基板、12,13……第１層配線、14……層間
絶縁膜、15……高温超伝導材料、16……金属（スルーホ
ール埋め込み用）、17……金属（コンタクト形成用）、
18……ペロブスカイト系物質よりなる薄層。1 (a) to 1 (f) are views showing respective steps of a wiring method of a semiconductor device as one embodiment of the present invention, and FIG. 2 is a schematic view showing an example of a crystal structure of a high temperature superconducting material. FIG. 3 and FIG. 3 are views for explaining the relationship between the crystal orientation of the high temperature superconducting material and the wiring orientation of the semiconductor device. 11 …… Semiconductor substrate, 12,13 …… First layer wiring, 14 …… Interlayer insulating film, 15 …… High temperature superconducting material, 16 …… Metal (for filling through holes), 17 …… Metal (for forming contact) ),
18 ... A thin layer made of perovskite-based material.
Claims (1)
高温超伝導材料を被着してエネルギービームを照射して
超伝導特性を持たせると同時に結晶方向を揃えるような
熱処理を行い所望の配線に加工する工程と、 上記配線の所定部位を除去してコンタクトホールを形成
する工程と、 上記コンタクトホール内に電流経路となる金属を形成す
る工程とを含んでなることを特徴とする半導体装置の配
線方法。1. A high-temperature superconducting material is deposited on an interlayer insulating film formed on a semiconductor substrate and irradiated with an energy beam so as to have superconducting characteristics and at the same time, a heat treatment for aligning crystal directions is desired. Of the wiring, a step of removing a predetermined portion of the wiring to form a contact hole, and a step of forming a metal serving as a current path in the contact hole. Wiring method of equipment.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62176220A JPH079905B2 (en) | 1987-07-15 | 1987-07-15 | Wiring method for semiconductor device |
| DE88107375T DE3886286T2 (en) | 1987-07-15 | 1988-05-07 | Connection method for semiconductor device. |
| EP88107375A EP0299163B1 (en) | 1987-07-15 | 1988-05-07 | Interconnection method for semiconductor device |
| US07/711,716 US5183800A (en) | 1987-07-15 | 1991-06-07 | Interconnection method for semiconductor device comprising a high-temperature superconductive material |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62176220A JPH079905B2 (en) | 1987-07-15 | 1987-07-15 | Wiring method for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6420638A JPS6420638A (en) | 1989-01-24 |
| JPH079905B2 true JPH079905B2 (en) | 1995-02-01 |
Family
ID=16009726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62176220A Expired - Fee Related JPH079905B2 (en) | 1987-07-15 | 1987-07-15 | Wiring method for semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0299163B1 (en) |
| JP (1) | JPH079905B2 (en) |
| DE (1) | DE3886286T2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0282012A3 (en) * | 1987-03-09 | 1989-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Superconducting semiconductor device |
| JPS63314850A (en) * | 1987-06-18 | 1988-12-22 | Fujitsu Ltd | Semiconductor device |
| CN1017110B (en) * | 1987-08-13 | 1992-06-17 | 株式会社半导体能源研究所 | Superconducting devices |
| JP2553101B2 (en) * | 1987-09-04 | 1996-11-13 | 株式会社東芝 | Semiconductor device |
| GB2215548B (en) * | 1988-02-26 | 1991-10-23 | Gen Electric Co Plc | A method of fabricating superconducting electronic devices |
| CA2054597C (en) * | 1990-10-31 | 1997-08-19 | Hiroshi Inada | Superconducting circuit and a process for fabricating the same |
| DE4038894C1 (en) * | 1990-12-06 | 1992-06-25 | Dornier Gmbh, 7990 Friedrichshafen, De | |
| CN116322279B (en) * | 2021-12-17 | 2024-10-22 | 腾讯科技（深圳）有限公司 | Silicon wafer and filling method of silicon holes thereof |
| CN115440879B (en) * | 2022-06-16 | 2023-04-25 | 合肥本源量子计算科技有限责任公司 | Superconductive silicon wafer and preparation method thereof |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4507852A (en) * | 1983-09-12 | 1985-04-02 | Rockwell International Corporation | Method for making a reliable ohmic contact between two layers of integrated circuit metallizations |
| JPH0648733B2 (en) * | 1984-01-25 | 1994-06-22 | 株式会社日立製作所 | Cryogenic semiconductor device |
| JP2855614B2 (en) * | 1987-03-30 | 1999-02-10 | 住友電気工業株式会社 | Method of forming superconducting circuit |
| US5096882A (en) * | 1987-04-08 | 1992-03-17 | Hitachi, Ltd. | Process for controlling oxygen content of superconductive oxide, superconductive device and process for production thereof |
| JPS63276822A (en) * | 1987-05-06 | 1988-11-15 | Furukawa Electric Co Ltd:The | Patterning method for superconductive thin film |
| EP0365533A1 (en) * | 1987-06-12 | 1990-05-02 | Siemens Aktiengesellschaft | Process for manufacturing conductive regions from an oxide-ceramic superconducting material having a high conductivity-change temperature |
| JPS63314850A (en) * | 1987-06-18 | 1988-12-22 | Fujitsu Ltd | Semiconductor device |
-
1987
- 1987-07-15 JP JP62176220A patent/JPH079905B2/en not_active Expired - Fee Related
-
1988
- 1988-05-07 DE DE88107375T patent/DE3886286T2/en not_active Expired - Fee Related
- 1988-05-07 EP EP88107375A patent/EP0299163B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6420638A (en) | 1989-01-24 |
| DE3886286D1 (en) | 1994-01-27 |
| EP0299163B1 (en) | 1993-12-15 |
| DE3886286T2 (en) | 1994-03-31 |
| EP0299163A2 (en) | 1989-01-18 |
| EP0299163A3 (en) | 1989-09-06 |
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