CN114883192A - Monolithic heterogeneous integrated structure of silicon and III-V group device on insulating substrate and preparation method - Google Patents

Abstract

The invention provides a monolithic heterogeneous integrated structure of silicon and III-V group devices on an insulating substrate and a preparation method thereof, wherein the preparation method can adopt the insulating substrate based on Si to carry out heterogeneous integration, and the Si substrate has the advantages of price and cost; by utilizing the lateral growth of the GaN layer from the side surface of the silicon film, the stress accumulation caused by lattice mismatch and thermal mismatch between the GaN epitaxial layer and the substrate can be reduced by reducing the contact area between the growth substrate and the GaN layer, thereby reducing the probability of generating threading dislocation and being beneficial to obtaining the high-quality epitaxial layer. The monolithic heterogeneous integrated structure of silicon and III-V family devices on the insulating substrate obtained by the preparation method can be used for preparing a cascade GaN-based device, and is beneficial to miniaturization of the device and exertion of the advantages of the GaN cascade device in the aspects of power gain and stability.

Description

Monolithic hetero-integrated structure and fabrication method of silicon and III-V devices on insulating substrates

technical field

The invention belongs to the technical field of semiconductors, and relates to a monolithic hetero-integrated structure of silicon and III-V group devices and a preparation method.

Background technique

With the development of semiconductor technology, more and more attention has been paid to miniaturized and higher integrated chips. Among them, various functional devices are integrated on a single chip to make the entire package module smaller, higher performance, and economical. The cost of the back-end process is getting more and more attention.

As a representative of the third generation semiconductor materials, gallium nitride (GaN) has many excellent properties such as high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration and good high temperature working ability. Therefore, based on GaN The third generation of semiconductor devices, such as high electron mobility transistors (HEMTs), heterojunction field effect transistors (HFETs), etc., have been applied, especially in the fields of radio frequency, microwave and other fields that require high power and high frequency, showing obvious advantages . Power electronic devices require more normally off-state enhancement mode gallium nitride power devices, but due to the formation of two-dimensional electron gas in the heterojunction, general gallium nitride devices are mainly depletion mode. A feasible solution is to cascade an enhancement mode silicon transistor and a depletion mode gallium nitride transistor to form a cascode enhancement mode gallium nitride device. This structure has a stable positive threshold voltage and is compatible with existing compatible with gate drive circuits. In addition, due to the introduction of the silicon-based metal oxide field effect transistor (MOSFET) structure, the cascode gallium nitride device has a larger gate voltage swing compatible with the driving circuit.

On the other hand, a semiconductor substrate material with heterogeneous integration of III-V materials and Si materials on an insulating substrate can also be a monolithic integrated optoelectronic integrated chip, MEMS and other functional chips. Integration provides high performance substrate materials. At present, from the perspective of raw material sources and cost saving, Si substrates are still more widely used, and a variety of devices can be integrated to a large extent on the existing size substrates. However, due to the differences in lattice constants and thermal conductivity of different materials, large-scale heterogeneous integration of multiple materials on the same Si substrate has the problem of complex process and difficulty in ensuring product uniformity and yield.

Therefore, it is necessary to provide a wafer-level monolithic hetero-integrated structure of silicon devices and III-V devices and a preparation method thereof.

SUMMARY OF THE INVENTION

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a monolithic hetero-integrated structure of silicon and III-V devices on an insulating substrate and a preparation method thereof, which are used to solve the problems of GaN devices in the prior art. Hetero-integrated structures with Si devices and/or III-V devices are difficult to ensure the uniformity and yield of materials.

In order to achieve the above object and other related objects, the present invention provides a preparation method of a monolithic hetero-integrated structure of silicon and III-V devices on an insulating substrate, comprising the following steps:

A silicon-on-insulator substrate structure is provided, and the top silicon of the silicon-on-insulator substrate structure is patterned to form at least one silicon step, and the buried oxide layer of the silicon-on-insulator substrate structure is exposed below the four sides of the silicon step:

Covering the dielectric layer on the silicon step, patterning the top surface of the dielectric layer to form an opening exposing a part of the surface of the silicon step;

The silicon step is anisotropically etched through the opening to remove the silicon step directly below the opening, and further laterally removes part of the silicon step below the opening side to form a lateral cavity, the lateral cavity One end away from the opening retains the silicon film;

selectively laterally growing a GaN layer from the sides of the silicon film within the lateral cavity;

removing the dielectric layer to reveal the silicon film and the GaN layer;

selectively forming an AlGaN barrier layer on the GaN layer;

A source electrode, a drain electrode and a gate electrode are formed on the AlGaN barrier layer to obtain a GaN device.

Optionally, the silicon steps include silicon islands or silicon nanowires and have a length L ₁ , the openings have a width L ₂ in the length direction of the silicon steps, and L ₂ ≤ 0.1×L ₁ .

Optionally, in the length direction of the silicon step, the opening has a first distance L ₃ from one end of the silicon step and a second distance L ₄ from the other end of the silicon step, where L ₃ <L ₄ , and 0≤L ₃ ≤L ₂ .

Optionally, use TMAH etching solution to anisotropically etch the silicon steps to expose the Si(111) surface on the side of the silicon film, and then selectively grow a GaN layer laterally from the side of the silicon film. step, the GaN layer has the following length in the lateral direction: the length does not exceed the distance between the silicon film and the opening, so that the GaN layer maintains a lateral growth mode.

Optionally, the preparation method further includes: forming on the insulating substrate a single layer or multiple layers of a III-V compound semiconductor material different from a GaN-based III-V compound semiconductor material, the III-V compound semiconductor material. Group compound semiconductor materials include InP, InAs, InSb, GaAs, AlAs, GaSb, or a combination of the above compounds.

Optionally, forming a single layer or multiple layers of the III-V compound semiconductor material on the insulating substrate includes:

forming a plurality of silicon steps on the insulating substrate, and correspondingly forming a plurality of lateral cavities based on the plurality of silicon steps;

Before or after selectively laterally epitaxially growing the GaN layer from the side of the silicon film in at least one lateral cavity of the plurality of lateral cavities, in at least one other lateral cavity of the plurality of lateral cavities The III-V group compound semiconductor material layer is laterally epitaxially grown in the lateral cavity, wherein the III-V group compound semiconductor material layer includes an InGaAs layer or an InAlAs layer.

optionally, laterally growing the GaN layer from the side of the silicon film at a first temperature, epitaxially growing the AlGaN barrier layer at a second temperature; and epitaxially growing the III-V at a third temperature A group compound semiconductor material layer, wherein the first temperature, the second temperature and the third temperature have a temperature gradient from high to low in sequence.

Optionally, the step of providing the silicon-on-insulator substrate structure includes: the step of providing the silicon-on-insulator substrate structure includes: providing a silicon substrate; performing an ion implantation process at a predetermined depth of the silicon substrate A buried oxide layer is formed, wherein the surface of the silicon substrate has a Si(100) plane.

Optionally, the preparation method further comprises the following steps:

If the dielectric layer is a SiO ₂ layer, the dielectric layer is removed by a dry etching process; or

When the dielectric layer is a SiN layer, the dielectric layer is selectively removed by a wet etching process.

Optionally, the preparation method further includes the following steps: preparing a Si-based MOSFET device based on the silicon film, wherein the GaN device is a GaN-based HEMT device, and forming interconnect electrodes so that the source region of the Si-based MOSFET device is connected to the source region of the Si-based MOSFET device. The source of the GaN-based HEMT device is electrically connected, so that the gate of the Si-based MOSFET device is electrically connected to the gate of the GaN-based HEMT device, so as to form a cascode cascaded GaN-based HEMT device.

The present invention also provides a monolithic hetero-integrated structure of silicon and III-V group devices on an insulating substrate, the monolithic hetero-integrated structure comprising:

an insulating substrate, including a buried oxide layer as a mesa;

at least one silicon film on the mesa;

GaN devices, including:

a GaN layer laterally grown from the silicon film, the GaN layer and the silicon film are coplanar, and the thickness of the GaN layer is consistent with the height of the silicon film;

An AlGaN barrier layer located on the GaN layer, the AlGaN barrier layer is provided in the thickness direction of the GaN layer and is perpendicular to the growth direction of the GaN layer.

Optionally, the insulating substrate is further provided with a single layer or multiple layers of III-V compound semiconductor materials different from GaN-based III-V compound semiconductor materials, and the single layer or multiple layers of the III-V compound semiconductor material. The layer or layers are disposed coplanar with the silicon film and include InP, InAs, InSb, GaAs, AlAs, GaSb, or combinations thereof.

The present invention provides a cascode cascaded GaN-based HEMT device, which is based on the aforementioned monolithic heterogeneous integration of silicon-on-insulator and III-V devices Structure preparation.

As mentioned above, the monolithic hetero-integrated structure of silicon on insulating substrate and III-V device and the preparation method thereof of the present invention have the following beneficial effects:

The method for preparing a monolithic hetero-integrated structure of silicon and III-V devices on an insulating substrate provided by the present invention utilizes the lateral growth of the GaN layer from the side of the silicon film, and reduces the contact area between the growth substrate and the GaN layer, thereby reducing the The stress accumulation caused by the lattice mismatch and thermal mismatch between the GaN epitaxial layer and the substrate, thereby reducing the probability of threading dislocations, is conducive to obtaining high-quality epitaxial layers;

In the preparation method provided by the present invention, a Si-based insulating substrate can be used for heterogeneous integration. The Si substrate has advantages in price and cost, and can be applied to different lattice constants through a multi-step epitaxy process with a temperature ranging from high temperature to low temperature. and thermal conductivity of various materials, the preparation method has a wide range of application value;

The monolithic hetero-integrated structure of silicon and III-V devices on an insulating substrate provided by the present invention can realize devices with multiple functions on the same substrate, wherein the GaN layer grows in the lateral direction and has half of the vertical direction. The polar plane can generate a higher concentration of two-dimensional electron gas (GaN) in the GaN/AlGaN heterojunction, and at the same time can reduce the leakage channel; further, based on the heterointegrated structure, a cascode cascading type GaN can be prepared The device can take advantage of the power gain and stability of the GaN cascode device, which is conducive to the miniaturization of the device.

Description of drawings

FIG. 1 is a schematic diagram of a process flow diagram of preparing a hetero-integrated structure of silicon and GaN devices on an insulating substrate according to an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating a process flow of preparing a hetero-integrated structure of silicon-on-insulator and III-V devices according to an embodiment of the present invention.

3A and 3B are schematic diagrams showing the structure of forming a silicon step on an insulating substrate according to an embodiment of the present invention, wherein FIG. 3B is a top view of the structure shown in FIG. 3A .

4A and 4B are schematic views of the structure after forming an opening to expose a part of the surface of the silicon step according to an embodiment of the present invention, wherein FIG. 4B is a top view of the structure shown in FIG. 4A .

5A and 5B are schematic diagrams showing the structure of the silicon step after anisotropic etching through the opening in an embodiment of the present invention, wherein FIG. 5B is a top view of the structure shown in FIG. 5A .

FIG. 6 is a schematic diagram illustrating a structure after selectively forming an AlGaN barrier layer on the GaN layer according to an embodiment of the present invention.

FIG. 7 is a top view of the structure after the isolation spacers surrounding the silicon film and the GaN device are formed according to an embodiment of the present invention.

FIG. 8 is a schematic diagram illustrating a structure after forming a source electrode, a drain electrode and a gate electrode on the AlGaN barrier layer according to an embodiment of the present invention.

FIG. 9 is a schematic diagram illustrating a monolithic hetero-integrated structure of a Si-based MOSFET device and a GaN-based HEMT device according to an embodiment of the present invention.

Component label description

100-insulating substrate; 102-underlying silicon; 106-silicon step; 108-silicon film; 110-buried oxide layer; 200-dielectric layer; 202-opening; 210-lateral cavity; 310-GaN layer; 320-AlGaN potential barrier layer; 410-isolation spacer; 511-source; 512-drain; 520-gate; A-Si-based device; B-GaN device.

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional views showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present invention. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual production.

For convenience of description, spatially relative terms such as "below," "below," "below," "below," "above," "on," etc. may be used herein to describe an element shown in the figures or The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other directions of the device in use or operation than those depicted in the figures. In addition, when a layer is referred to as being 'between' two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between" means including both endpoints.

In the context of this application, descriptions of structures where a first feature is "on" a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include further features formed over the first and second features. Embodiments between the second features such that the first and second features may not be in direct contact.

The term "gallium nitride-based III-V compound semiconductor material" in this application refers to nitride semiconductor materials of group III elements of the periodic table including gallium, such as GaN, GaAlN, InGaN, InAlGaN.

It should be noted that the embodiments provided in the present invention in conjunction with the accompanying drawings are only used to illustrate the basic concept of the present invention in a schematic way, and the accompanying drawings only show the components related to the present invention rather than the components according to the actual implementation. The number, shape and size are drawn, and the type, number and ratio of each component can be arbitrarily changed in actual implementation, and the component layout may also be more complicated.

In the drawings used to describe embodiments of the present disclosure, the thickness of layers or regions may be exaggerated or reduced for clarity, ie, the drawings are not drawn to scale. Where not conflicting, the embodiments of the present disclosure and features within the embodiments may be combined with each other to yield new embodiments.

In order to realize wafer-level monolithic hetero-integrated silicon devices and III-V devices and their multifunctionality, the present invention provides a preparation method of a hetero-integrated structure of silicon and III-V devices on an insulating substrate ,include:

A silicon-on-insulator substrate structure is provided, and the top silicon of the silicon-on-insulator substrate structure is patterned to form at least one silicon step, and the buried oxide layer of the silicon-on-insulator substrate structure is exposed below the four sides of the silicon step:

Covering the dielectric layer on the silicon step, patterning the top surface of the dielectric layer to form an opening exposing a part of the surface of the silicon step;

The silicon step is anisotropically etched through the opening to remove the silicon step directly below the opening, and further laterally removes part of the silicon step below the opening side to form a lateral cavity, the lateral cavity One end away from the opening retains the silicon film;

selectively laterally growing a GaN layer from the sides of the silicon film within the lateral cavity;

removing the dielectric layer to reveal the silicon film and the GaN layer;

selectively forming an AlGaN barrier layer on the GaN layer;

A source electrode, a drain electrode and a gate electrode are formed on the AlGaN barrier layer to obtain a GaN device.

The hetero-integrated structure of silicon-on-insulator and group III-V devices of the present invention and the preparation method thereof will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 1 , this embodiment provides a method for fabricating a coplanar hetero-integrated structure of silicon and III-V devices on an insulating substrate.

First, at step S1, a silicon-on-insulator substrate structure is provided, and the top silicon of the silicon-on-insulator substrate structure is patterned to form at least one silicon step. In this embodiment, the silicon-on-insulator substrate structure includes a bottom layer of silicon 102, a buried oxide layer 110 and a top layer of silicon (not shown); preferably, the top layer of silicon has a (100) plane. In some examples, the silicon-on-insulator substrate structure 100 may be a commercially available SOI substrate. In other examples, the silicon-on-insulator substrate structure 100 may be obtained by implanting oxygen ions into the Si substrate through, for example, but not limited to, an ion implantation process to form the buried oxide layer 110 at a predetermined depth of the Si substrate. Specifically, the depth of formation of the buried oxide layer in the Si substrate can be controlled by adjusting the implantation energy of the ion implantation process. Then, referring to FIGS. 3A-3B , patterning the top layer silicon of the silicon-on-insulator substrate structure includes: defining a first pattern area corresponding to the subsequent epitaxial growth substrate on the top layer silicon by a photolithography process, and according to the first pattern area The top layer of silicon is etched to form at least one silicon step 106 , and the buried oxide layer 110 of the silicon-on-insulator substrate structure is exposed under the periphery of the silicon step 106 . For the sake of clarity, only a schematic diagram of the structure of forming a silicon step on an insulating substrate is shown in the figure. According to the actual required device type, the silicon step is used as the growth substrate for the subsequent epitaxy process, and the morphology of the silicon step can be appropriately changed. and/or size, eg, silicon steps may have larger area silicon islands, or multiple small size silicon nanowires. In this embodiment, due to the protection of the developed photoresist, the top surface of the formed silicon step 106 is still in the (100) crystal orientation.

Specifically, the etching process may be dry etching, such as an inductively coupled plasma (ICP) etching process; or, a wet etching process may be performed using tetramethylammonium hydroxide (TMAH).

Next, in step S2, a dielectric layer is covered on the silicon step, and the top surface of the dielectric layer is patterned. Specifically, the dielectric layer 200 can be formed by a deposition process with good step coverage, and the dielectric layer 200 is conformally deposited on the silicon steps 106 and covers the side and top surfaces of the silicon steps 106 . As an example, the dielectric layer 200 may be selected from any of a SiO ₂ layer or a SiN layer, and the process for forming the dielectric layer includes, but is not limited to, chemical vapor deposition (CVD), plasma CVD, atomic layer deposition, and the like The conventional deposition process and other similar deposition processes; preferably, the dielectric layer can be formed by a CVD process.

Continue to perform step S2, patterning the top surface of the dielectric layer 200, including the following steps: defining a second pattern area on the top surface of the dielectric layer 200 by a photolithography process; etching the dielectric layer according to the second pattern area to form a An opening 202, which exposes a portion of the surface of the silicon step 106, serves as a window for the subsequent etching process. As an example, referring to FIGS. 3A and 4A , the silicon step 106 may have a length L ₁ , the opening 202 may have a width L ₂ along the length L ₁ , and L ₂ ≦0.1×L ₂ . The size of the opening 202 may be appropriately determined according to the morphology and/or size of the silicon step to ensure the etching rate of the silicon step in subsequent processes. In addition, the opening 202 may be disposed along the width direction of the silicon step 106 and disposed close to one end of the dielectric layer and spaced apart from the end so that the opening 202 has a proximal end along the length direction of the silicon step 106 . The position of the opening 202 can be appropriately determined as required. As shown in FIGS. 4A-4B, the opening 202 has a first distance L ₃ from one end of the silicon step and a second distance L ₄ from the other end of the silicon step, where L ₃ <L ₄ , and 0≦L ₃ ≦L ₂ .

Referring to FIG. 1 and FIGS. 5A-5B, at step S3: anisotropically etching the silicon step through the opening to form a lateral cavity, the end of the lateral cavity away from the opening retains a silicon film . As an example, a wet etching process can be used to allow a chemical etching solution to enter and etch the silicon steps 106 through the openings 202 , and in particular, TMAH etching solution can be used to etch the silicon material to remove the silicon steps 106 directly below the openings 202 , and further Part of the silicon step below the opening side is removed laterally to form a lateral cavity 210 , and the silicon film 108 remains at an end of the lateral cavity 210 away from the opening. Since the TMAH etching solution has crystal orientation selectivity for the etching process of silicon materials, especially the etching rate of this etching solution to the Si(100) surface is higher than that of the Si(111) surface, and it has a high selectivity ratio. , so the side surface of the silicon film 108 after the wet etching process is the Si(111) surface. In this embodiment, the thickness of the silicon film remaining in the lateral cavity 210 may be 0.1×L ₁ .

At step S4: selectively growing a GaN layer laterally from the side of the silicon film in the lateral cavity. Preferably, a GaN layer can be selectively epitaxially grown laterally from the side of the silicon film 108 in the lateral cavity 210 by a metal organic compound chemical vapor deposition (MOCVD) process or a molecular beam epitaxy (MBE) process. In the lateral epitaxy process, the silicon film serves as a growth substrate, and the side surface of the silicon film 108 has a (111) crystallographic orientation, and GaN nucleation selectively occurs in the crystallographic plane with this orientation. The lateral cavity 210 can be used to define the direction of the epitaxial growth of the GaN layer, and the setting range of the GaN layer can be limited between the silicon film 108 and the opening 202, so that the GaN layer can maintain the lateral growth mode, which is compared with that in the lateral growth mode. The large-scale heterogeneous integration on the large-size Si substrate reduces the difficulty of the process, and also ensures the overall uniformity and crystal quality of the epitaxially grown GaN layer, which is conducive to reducing the leakage of the material and improving the reliability of the device. In this embodiment, the GaN layer can be selectively epitaxially grown at a temperature between 1000°C and 1250°C.

Next, at step S5: removing the dielectric layer to expose the silicon film and the GaN layer. The etching process can be appropriately selected according to the material of the dielectric layer. Specifically, in the example in which the dielectric layer 200 is a SiO ₂ layer, the dielectric layer defining the lateral cavity can be selectively removed by a dry etching process. Since the dry etching process is an anisotropic etching process, The top surface of the lateral cavity is opened to leave the dielectric spacer 410, as shown in FIG. 7, so as to avoid damage to the buried oxide layer 110 serving as the mesa. The dry etching process may include, for example, reactive ion etching, ion beam etching, plasma etching, or laser etching/etching. Alternatively, in the example in which the dielectric layer 200 is a SiN layer, the dielectric layer may be selectively removed by using a chemical etchant through a wet etching process, as shown in FIG. 6 , since the wet etching process has high selectivity to the SiN layer Therefore, it will not affect the buried oxide layer 110 as a mesa and cause damage.

After removing the dielectric layer in step S5 to expose the silicon film and the GaN layer, step S6 is subsequently performed: selectively forming an AlGaN barrier layer on the GaN layer. Since the surface of the exposed silicon film is not etched and has a (100) crystal orientation, AlGaN will preferentially nucleate and grow on the GaN layer 310, so an AlGaN barrier layer 320 can be selectively formed on the GaN layer 310, as shown in FIG. 6 . Show. Similarly, the AlGaN barrier layer can be selectively epitaxially grown by a MOCVD process or an MBE process. In this embodiment, the AlGaN barrier layer 320 may be selectively epitaxially grown on the GaN layer 310 by an MOCVD process at a second temperature between 1000°C and 1250°C. According to requirements, a plurality of silicon steps can be formed on the insulating substrate, and at the same time, a plurality of groups of spaced GaN-based III-V compound semiconductor material layers can be epitaxially grown.

In addition, the preparation method described in this embodiment further includes: forming a III-type III-V compound semiconductor material different from a GaN-based III-V compound semiconductor material in a desired region on the insulating substrate with process steps similar to steps S2 to S6 A single layer or multiple layers (not shown) of group V compound semiconductor material, wherein a plurality of desired regions can be defined on the insulating substrate; that is, a plurality of silicon steps are formed to integrate a variety of Epitaxial materials, thereby realizing a variety of functionalized devices. Specifically, the group III-V compound semiconductor material includes InP, InAs, InSb, GaAs, AlAs, GaSb or a combination of the above compounds. Here, with reference to Steps S12 to S15 shown in FIG. 2 , the preparation method for forming a single layer or a multi-layer of the group III-V compound semiconductor material on an insulating substrate will be described in detail.

In step S11, a silicon-on-insulator substrate structure is provided, the top silicon of the silicon-on-insulator substrate structure is patterned to form a plurality of silicon steps, and the bottom of the silicon-on-insulator substrate structure is exposed below the peripheries of the silicon steps. Buried Oxygen Layer:

In step S12, covering each silicon step with a dielectric layer, and patterning the top surface of the dielectric layer to form an opening exposing a part of the surface of the silicon step;

In step S13, each silicon step is anisotropically etched through the opening to remove the silicon step directly below the opening, and further laterally removes part of the silicon step below the opening side, thereby forming the insulating substrate on the insulating substrate. A plurality of lateral cavities are formed, and one end of each lateral cavity away from the opening retains the silicon film.

In step S14, in the plurality of lateral cavities before or after selectively laterally epitaxially growing the GaN layer from the side of the silicon film in at least one of the plurality of lateral cavities A layer of III-V compound semiconductor material is laterally epitaxially grown in at least one additional lateral cavity.

In step S15, the dielectric layer is removed to expose the silicon film and the III-V compound semiconductor material layer.

Optionally, after step S15, epitaxial growth is selectively performed on the III-V group compound semiconductor material layer to obtain a multilayer of III-V group compound semiconductor material.

Specifically, the III-V group compound semiconductor material layer includes an InGaAs layer or an InAlAs layer; correspondingly, the III-V group compound semiconductor material layer may include, for example, InP/InAlAs, InP/InAlAs/InP, InGaAs/ A combination of GaAs/InGaAs or other III-V compound semiconductor materials.

The step sequence of the epitaxial process can be appropriately adjusted according to the epitaxial temperature of the compound semiconductor material, and the epitaxial growth of the III-V semiconductor material layer can be sequentially performed with a temperature gradient from high to low, so that a variety of different hetero-integrated structures can be realized. , to improve the performance of the overall hetero-integrated structure. For example, the III-V compound semiconductor material layer includes any one of an InGaAs layer and an InAlAs layer. As an example, the InGaAs layer and the InAlAs layer may be epitaxially grown at a third temperature between 500°C-600°C. In this embodiment, the GaN layer is laterally grown from the side of the silicon film at a first temperature, the AlGaN barrier layer is epitaxially grown at a second temperature; and the III is epitaxially grown at a third temperature - Group V compound semiconductor material layer, wherein the first temperature, the second temperature, and the third temperature have a temperature gradient from high to low in sequence. The required epitaxial layers may be grown in step S16 to obtain a hetero-integrated structure of silicon on an insulating substrate and group III-V devices. It should be noted that although the steps for preparing the InGaAs and InAlAs compound semiconductor material layers are described herein, other suitable III-V semiconductor materials, such as InP, InAs, can be selected without departing from the technical concept of the present invention. , GaAs, GaSb or a combination of the above compounds.

Referring to FIG. 7, in step S7, a source electrode, a drain electrode and a gate electrode are formed on the AlGaN barrier layer to obtain a GaN device. The GaN device may be a GaN-based HEMT device, a heterojunction field effect transistor (HFET) device, or a MOSFET device. Here, the preparation method is further described in conjunction with the specific structure of the GaN-based HEMT device. At step S7: the step of forming the source electrode 511 and the drain electrode 512 includes: performing a photolithography process through a mask to define the pattern regions of the metal source electrode and the metal drain electrode; depositing metal Ti/Al/Ni/Au, and performing The mask is peeled off; an annealing process is performed, so that the metal source electrode and the metal drain electrode form an ohmic contact on the surface of the AlGaN barrier layer. Optionally, after the source electrode 511 and the drain electrode 512 are formed, a first passivation layer can be grown for surface passivation by, for example, a plasma chemical vapor deposition (PECVD) process, which is beneficial to suppress the crystals on the surface of the heterojunction material. For interface defects caused by defects, the first passivation layer includes SiN _X or SiO ₂ .

In addition, the step of forming the gate 520 includes: performing a photolithography process through a mask, defining a gate trench in the first passivation layer; depositing multiple layers of metal in the gate trench to form a metal gate, for example, In other words, the multi-layer metal can be Ni/Au. It can be understood that the method for forming the source electrode 511 , the drain electrode 512 and the gate electrode 520 is not limited to this, and the specific steps and sequence of preparing the corresponding structures can be appropriately adjusted as required.

Optionally, after step S7, a Si-based MOSFET device may be prepared based on the silicon film 108 as required; and a cascode cascading type GaN-based HEMT device may be formed.

Specifically, after the source region and the drain region are formed in the silicon film 108 by, for example, an ion implantation process, the gate electrode 620 can be formed on the surface of the silicon film. Subsequently, a second passivation layer may be formed on the surface of the GaN-based HEMT device and a third passivation layer may be formed on the surface of the Si-based MOSFET device for passivation protection of the device surface. Then, the contact holes corresponding to the source, drain and gate of the GaN-based HEMT device are defined in the second passivation layer by a photolithography process, and the source region, the source region, the source region and the gate of the Si-based MOSFET device are defined in the third passivation layer. Contact holes corresponding to the drain region and gate; depositing metal in the contact holes to achieve electrical extraction; stripping the residual photoresist while removing the metal covering the surface of the photoresist. By forming interconnect electrodes, the source region of the Si-based MOSFET device is electrically connected to the source of the GaN-based HEMT device, and the gate of the Si-based MOSFET device is electrically connected to the gate of the GaN-based HEMT device, thereby forming a common source Common-gate cascaded GaN-based HEMT devices. By heterogeneously integrating Si-based MOSFET devices and GaN devices on the same substrate, and controlling the on and off of GaN devices through Si-based MOSFET devices, the advantages of GaN cascode devices in terms of power gain and stability are brought into play.

Referring to FIG. 8 , the present embodiment further provides a monolithic hetero-integrated structure of silicon and III-V devices on an insulating substrate. The monolithic hetero-integrated structure can be prepared by the above preparation method, but is not limited thereto. The materials and preparation methods of the monolithic hetero-integrated structure will not be repeated here.

The monolithic hetero-integrated structure of silicon and III-V devices on an insulating substrate includes: an insulating substrate, including a buried oxide layer 110 serving as a mesa; at least one silicon film 108 on the mesa; a GaN device, Including: a GaN layer 310 grown laterally from the silicon film 108, the GaN layer and the silicon film 108 are coplanar, and the thickness of the GaN layer is consistent with the height of the silicon film; located on the GaN layer The AlGaN barrier layer 320 is provided in the thickness direction of the GaN layer and is perpendicular to the growth direction of the GaN layer.

As an example, the monolithic hetero-integrated structure further includes a single layer or multiple layers of a III-V compound semiconductor material other than a GaN-based III-V compound semiconductor material, the III-V compound semiconductor material being disposed on the insulating substrate. A single layer or multiple layers of compound semiconductor materials are coplanar with the silicon film, so as to heterogeneously integrate various materials on the insulating substrate, thereby realizing various functional devices of wafer-level monolithic heterogeneous integration. Specifically, the single or multiple layers of the III-V compound semiconductor material include InP, InAs, InSb, GaAs, AlAs, GaSb, or a combination of the above compounds. For example, monolithic hetero-integrated III-V HEMT devices and Si-based CMOS devices for mmWave communications, as well as III-V lasers and CMOS process-based devices can be fabricated based on the monolithic hetero-integrated structure. Hybrid integration of silicon-based photonic devices. In addition, as shown in Fig. 9, cascode cascading GaN-based HEMT devices, including GaN-based HEMT devices A and Si-based MOSFET device B, the source region of the Si-based MOSFET device is electrically connected to the source of the GaN-based HEMT device through interconnect electrodes, and the gate of the Si-based MOSFET device is electrically connected to the gate of the GaN-based HEMT device , such an arrangement can be applied to microwave and millimeter wave power amplifiers such as monolithic microwave integrated circuits (MMICs) for communications, instrumentation, military applications, etc.

To sum up, the hetero-integrated structure with coplanar silicon and III-V devices on an insulating substrate of the present invention and a preparation method thereof can use a Si-based insulating substrate for hetero-integration, and utilize lateral growth from the side of the silicon film. For the GaN layer, by reducing the contact area between the growth substrate and the GaN layer, the stress accumulation caused by the lattice mismatch and thermal mismatch between the GaN epitaxial layer and the substrate can be reduced, thereby reducing the probability of threading dislocations. Conducive to obtaining high-quality epitaxial layers; devices with multiple functions can be realized on the same substrate, in which the GaN layer grows laterally and has semipolar planes in the vertical direction, which can produce higher concentrations in GaN/AlGaN heterojunctions The two-dimensional electron gas (GaN) can also reduce leakage channels.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (13)

1. A method for preparing a monolithic heterogeneous integrated structure of silicon and III-V devices on an insulating substrate is characterized by comprising the following steps:

providing an insulator silicon-on-substrate structure, patterning top silicon of the insulator silicon-on-substrate structure to form at least one silicon step, and exposing a buried oxide layer of the insulator silicon-on-substrate structure below the periphery of the silicon step:

covering the silicon step with a dielectric layer, and patterning the top surface of the dielectric layer to form an opening exposing a part of the surface of the silicon step;

anisotropically etching the silicon step by the opening to remove the silicon step right below the opening, and further transversely removing part of the silicon step below the opening side to form a transverse cavity, wherein a silicon film is reserved at one end of the transverse cavity, which is far away from the opening;

selectively laterally growing a GaN layer from a side of the silicon film in the lateral cavity;

removing the dielectric layer to expose the silicon film and the GaN layer;

selectively forming an AlGaN barrier layer on the GaN layer;

and forming a source electrode, a drain electrode and a grid electrode on the AlGaN barrier layer to obtain the GaN device.

2. The method of claim 1, wherein: the silicon steps comprise silicon islands or silicon nanowires and have a length L ₁ The opening has a width L in the length direction of the silicon step ₂ And L is ₂ ≤0.1×L ₁ 。

3. The method of claim 2, wherein: the opening has a first distance L from one end of the silicon step in the length direction of the silicon step ₃ And a second distance L from the other end of the silicon step ₄ Wherein L is ₃ <L ₄ And 0 is equal to or less than L ₃ ≤L ₂ 。

4. The production method according to claim 1, characterized in that: anisotropically etching the silicon step with a TMAH etchant to expose a Si (111) plane on the side surface of the silicon film, and then performing a step of laterally growing a GaN layer selectively from the side surface of the silicon film, the GaN layer having the following length in the lateral direction: the length does not exceed the spacing between the silicon film and the opening to maintain the GaN layer in a laterally grown manner.

5. The method of manufacturing according to claim 1, further comprising: forming a single layer or multiple layers of III-V compound semiconductor materials different from GaN series III-V compound semiconductor materials on the insulating substrate, wherein the III-V compound semiconductor materials comprise InP, InAs, InSb, GaAs, AlAs, GaSb or combination of the above compounds.

6. The method of claim 5, wherein forming the one or more layers of III-V compound semiconductor material on the insulating substrate comprises:

forming a plurality of silicon steps on the insulating substrate, and correspondingly forming a plurality of transverse cavities on the basis of the plurality of silicon steps;

selectively laterally epitaxially growing a layer of a III-V compound semiconductor material from a side of a silicon film within at least one other lateral cavity of the plurality of lateral cavities, either before or after selectively laterally epitaxially growing the GaN layer within at least one of the plurality of lateral cavities, wherein the layer of III-V compound semiconductor material comprises an InGaAs layer or an InAlAs layer.

7. The method of manufacturing according to claim 6, further comprising: laterally growing the GaN layer from a side of the silicon film at a first temperature, epitaxially growing the AlGaN barrier layer at a second temperature; and epitaxially growing the III-V compound semiconductor material layer at a third temperature, wherein the first temperature, the second temperature and the third temperature have a temperature gradient from high to low in this order.

8. The method of claim 1, wherein the step of providing the silicon-on-insulator substrate structure comprises: providing a silicon substrate; and forming a buried oxide layer at a predetermined depth of the silicon substrate through an ion implantation process, wherein the surface of the silicon substrate has a Si (100) plane.

9. The method of claim 1, further comprising the steps of:

the dielectric layer is SiO ₂ The dielectric layer is removed through a dry etching process; or

And selectively removing the dielectric layer by a wet etching process, wherein the dielectric layer is an SiN layer.

10. The method of claim 1, further comprising the steps of: and preparing a Si-based MOSFET device based on the silicon film, wherein the GaN device is a GaN-based HEMT device, and the source region of the Si-based MOSFET device is electrically connected with the source electrode of the GaN-based HEMT device by forming an interconnection electrode, and the grid electrode of the Si-based MOSFET device is electrically connected with the grid electrode of the GaN-based HEMT device so as to form the cascade-connected GaN-based HEMT device.

11. A monolithic hetero-integrated structure of silicon and III-V devices on an insulating substrate, the monolithic hetero-integrated structure comprising:

an insulating substrate including a buried oxide layer as a mesa;

at least one silicon film on the mesa;

a GaN device, comprising:

a GaN layer laterally grown from the silicon film, the GaN layer being disposed coplanar with the silicon film and having a thickness that is consistent with a height of the silicon film;

an AlGaN barrier layer on the GaN layer, the AlGaN barrier layer being disposed in a thickness direction of the GaN layer and perpendicular to a growth direction of the GaN layer.

12. The monolithic heterogeneous integrated structure of claim 10, wherein: the insulating substrate is further provided with a single layer or multiple layers of III-V compound semiconductor materials different from GaN-based III-V compound semiconductor materials, wherein the single layer or multiple layers of III-V compound semiconductor materials are arranged coplanar with the silicon film and comprise InP, InAs, InSb, GaAs, AlAs, GaSb or the combination of the compounds.

13. A cascode-type GaN-based HEMT device prepared based on the monolithic heterogeneous integrated structure of silicon and III-V devices on an insulating substrate according to claim 11.

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