CN114883192A - Monolithic heterogeneous integrated structure of silicon and III-V group device on insulating substrate and preparation method - Google Patents
Monolithic heterogeneous integrated structure of silicon and III-V group device on insulating substrate and preparation method Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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Abstract
The invention provides a monolithic heterogeneous integrated structure of silicon and III-V group devices on an insulating substrate and a preparation method thereof, wherein the preparation method can adopt the insulating substrate based on Si to carry out heterogeneous integration, and the Si substrate has the advantages of price and cost; by utilizing the lateral growth of the GaN layer from the side surface of the silicon film, the stress accumulation caused by lattice mismatch and thermal mismatch between the GaN epitaxial layer and the substrate can be reduced by reducing the contact area between the growth substrate and the GaN layer, thereby reducing the probability of generating threading dislocation and being beneficial to obtaining the high-quality epitaxial layer. The monolithic heterogeneous integrated structure of silicon and III-V family devices on the insulating substrate obtained by the preparation method can be used for preparing a cascade GaN-based device, and is beneficial to miniaturization of the device and exertion of the advantages of the GaN cascade device in the aspects of power gain and stability.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a monolithic heterogeneous integrated structure of silicon and III-V devices and a preparation method thereof.
Background
With the development of semiconductor technology, a miniaturized chip with higher integration level receives more and more attention, wherein various functional devices are monolithically integrated, so that the whole packaging module has smaller volume and higher performance, and the subsequent process cost is saved, and the packaging module is more and more concerned by people.
As a representative of third-generation semiconductor materials, gallium nitride (GaN) has many excellent characteristics such as high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration, and good high-temperature operation capability, and thus, third-generation GaN-based semiconductor devices such as High Electron Mobility Transistors (HEMTs), Heterojunction Field Effect Transistors (HFETs), and the like have been used, and particularly, show significant advantages in fields requiring high power and high frequency, such as radio frequency, microwave, and the like. The power electronic device needs a normally-off enhanced gallium nitride power device more, but the general gallium nitride device is mainly depletion type due to the formation of heterojunction two-dimensional electron gas. One possible solution is to cascade an enhancement-mode silicon transistor and a depletion-mode gallium nitride transistor to form a cascode-type enhancement-mode gallium nitride device, which has a stable positive threshold voltage and is compatible with the existing gate driving circuit. In addition, the introduction of a silicon-based metal oxide field effect transistor (MOSFET) structure enables the cascode gallium nitride device to have larger grid voltage swing compatible with a driving circuit.
On the other hand, the semiconductor substrate material with heterogeneous integration high mobility of III-V group materials and Si materials on the insulating substrate can also provide a high-performance substrate material for the integration of a plurality of functional chips such as a monolithically integrated photoelectric integrated chip and MEMS. At present, from the viewpoint of raw material sources and cost saving, the Si substrate is still more widely applied, and various devices can be integrated on the substrate with the existing size to a greater extent. However, due to the difference between the lattice constant and the thermal conductivity of different materials, the large-scale heterogeneous integration of multiple materials on the same Si substrate has the problems of complex process and difficulty in ensuring the uniformity and yield of products.
Therefore, it is necessary to provide a wafer-level monolithic heterogeneous integrated structure of silicon device and III-V group device and a method for preparing the same.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a monolithic hetero-integrated structure of silicon and III-V devices on an insulating substrate and a method for preparing the same, which is used to solve the problem that the hetero-integrated structure of GaN devices and Si devices and/or III-V devices in the prior art is difficult to ensure the uniformity and yield of materials.
To achieve the above and other related objects, the present invention provides a method for fabricating a monolithic heterogeneous integrated structure of silicon and III-V devices on an insulating substrate, comprising the steps of:
providing an insulator silicon-on-substrate structure, patterning top silicon of the insulator silicon-on-substrate structure to form at least one silicon step, and exposing a buried oxide layer of the insulator silicon-on-substrate structure below the periphery of the silicon step:
covering the dielectric layer on the silicon step, and patterning the top surface of the dielectric layer to form an opening exposing a part of the surface of the silicon step;
anisotropically etching the silicon step by the opening to remove the silicon step right below the opening, and further transversely removing part of the silicon step below the opening side to form a transverse cavity, wherein a silicon film is reserved at one end of the transverse cavity, which is far away from the opening;
selectively laterally growing a GaN layer from a side of the silicon film in the lateral cavity;
removing the dielectric layer to expose the silicon film and the GaN layer;
selectively forming an AlGaN barrier layer on the GaN layer;
and forming a source electrode, a drain electrode and a grid electrode on the AlGaN barrier layer to obtain the GaN device.
Optionally, the silicon steps comprise silicon islands or silicon nanowires and have a length L 1 SaidThe opening has a width L in the length direction of the silicon step 2 And L is 2 ≤0.1×L 1 。
Optionally, the opening has a first distance L from one end of the silicon step in the length direction of the silicon step 3 And a second distance L from the other end of the silicon step 4 Wherein L is 3 <L 4 And 0 is equal to or less than L 3 ≤L 2 。
Optionally, anisotropically etching the silicon step with TMAH etchant to expose a Si (111) plane on the side surface of the silicon film, and then performing a step of selectively laterally growing a GaN layer from the side surface of the silicon film, the GaN layer having the following length in the lateral direction: the length does not exceed the spacing between the silicon film and the opening to maintain the GaN layer in a laterally grown manner.
Optionally, the preparation method further comprises: forming a single layer or multiple layers of a III-V compound semiconductor material different from a GaN-based III-V compound semiconductor material on the insulating substrate, the III-V compound semiconductor material including InP, InAs, InSb, GaAs, AlAs, GaSb, or a combination thereof.
Optionally, forming the single or multiple layers of III-V compound semiconductor material on the insulating substrate comprises:
forming a plurality of silicon steps on the insulating substrate, and correspondingly forming a plurality of transverse cavities on the basis of the plurality of silicon steps;
laterally epitaxially growing a layer of a III-V compound semiconductor material in at least one other of the plurality of lateral cavities, before or after selectively laterally epitaxially growing the GaN layer from the side of the silicon film in at least one of the plurality of lateral cavities, wherein the layer of III-V compound semiconductor material comprises an InGaAs layer or an InAlAs layer.
Optionally, laterally growing the GaN layer from a side of the silicon film at a first temperature, epitaxially growing the AlGaN barrier layer at a second temperature; and epitaxially growing the III-V compound semiconductor material layer at a third temperature, wherein the first temperature, the second temperature and the third temperature have a temperature gradient from high to low in this order.
Optionally, the step of providing the silicon-on-insulator substrate structure comprises: the step of providing the silicon-on-insulator substrate structure comprises: providing a silicon substrate; forming a buried oxide layer at a predetermined depth of the silicon substrate by an ion implantation process, wherein the silicon substrate surface has a Si (100) plane.
Optionally, the preparation method further comprises the following steps:
the dielectric layer is SiO 2 The dielectric layer is removed through a dry etching process; or
And selectively removing the dielectric layer by a wet etching process, wherein the dielectric layer is an SiN layer.
Optionally, the preparation method further comprises the following steps: and preparing a Si-based MOSFET device based on the silicon film, wherein the GaN device is a GaN-based HEMT device, and the source region of the Si-based MOSFET device is electrically connected with the source electrode of the GaN-based HEMT device by forming an interconnection electrode, and the grid electrode of the Si-based MOSFET device is electrically connected with the grid electrode of the GaN-based HEMT device so as to form the cascade-connected GaN-based HEMT device.
The present invention also provides a monolithic heterogeneous integrated structure of silicon and III-V devices on an insulating substrate, the monolithic heterogeneous integrated structure comprising:
an insulating substrate including a buried oxide layer as a mesa;
at least one silicon film on the mesa;
a GaN device, comprising:
a GaN layer laterally grown from the silicon film, the GaN layer being disposed coplanar with the silicon film and having a thickness that is consistent with a height of the silicon film;
an AlGaN barrier layer on the GaN layer, the AlGaN barrier layer being disposed in a thickness direction of the GaN layer and perpendicular to a growth direction of the GaN layer.
Optionally, a single layer or multiple layers of a III-V compound semiconductor material different from the GaN-based III-V compound semiconductor material, disposed coplanar with the silicon film and comprising InP, InAs, InSb, GaAs, AlAs, GaSb, or a combination thereof, are also disposed on the insulating substrate.
The invention provides a cascode cascade GaN-based HEMT device which is prepared based on the monolithic heterogeneous integrated structure of silicon and III-V group devices on an insulating substrate.
As mentioned above, the monolithic heterogeneous integrated structure of silicon and III-V devices on the insulating substrate and the preparation method thereof have the following beneficial effects:
according to the preparation method of the monolithic heterogeneous integrated structure of the silicon and the III-V group device on the insulating substrate, the GaN layer is transversely grown from the side surface of the silicon film, and the stress accumulation caused by lattice mismatch and thermal mismatch between the GaN epitaxial layer and the substrate can be reduced by reducing the contact area between the growth substrate and the GaN layer, so that the probability of generating threading dislocation is reduced, and the high-quality epitaxial layer is favorably obtained;
in the preparation method provided by the invention, the Si-based insulating substrate can be adopted for heterogeneous integration, the Si substrate has the advantages of price and cost, and the preparation method can be suitable for various materials with different lattice constants and thermal conductivities by a multi-step epitaxial process from high temperature to low temperature, and has wide application value;
the monolithic heterogeneous integrated structure of silicon and III-V group devices on the insulating substrate can realize devices with multiple functions on the same substrate, wherein the GaN layer grows along the transverse direction and has a semipolar surface in the vertical direction, two-dimensional electron gas (GaN) with higher concentration can be generated at a GaN/AlGaN heterojunction, and a leakage channel can be reduced; furthermore, the cascode-type GaN device is prepared based on the heterogeneous integrated structure, so that the advantages of the GaN cascode device in the aspects of power gain and stability can be exerted, and the miniaturization of the device is facilitated.
Drawings
FIG. 1 is a schematic process flow diagram of the fabrication of a hetero-integrated structure of silicon and GaN devices on an insulating substrate according to an embodiment of the invention.
FIG. 2 is a schematic process flow diagram of the fabrication of a hetero-integrated structure of silicon and III-V devices on an insulating substrate according to an embodiment of the present invention.
Fig. 3A and 3B are schematic views illustrating a structure of forming a silicon step on an insulating substrate according to an embodiment of the present invention, wherein fig. 3B is a top view of the structure shown in fig. 3A.
Fig. 4A and 4B are schematic structural diagrams illustrating a structure after an opening exposing a portion of the surface of the silicon step is formed according to an embodiment of the invention, wherein fig. 4B is a top view of the structure shown in fig. 4A.
Fig. 5A and 5B are schematic structural views illustrating the silicon step after anisotropically etching the silicon step through the opening according to an embodiment of the present invention, wherein fig. 5B is a top view of the structure shown in fig. 5A.
Fig. 6 is a schematic structural view illustrating an AlGaN barrier layer selectively formed on a GaN layer according to an embodiment of the present invention.
Fig. 7 is a top view of the structure after forming the isolation spacers surrounding the silicon film and the GaN device in the embodiment of the invention.
Fig. 8 is a schematic structural view of an AlGaN barrier layer according to an embodiment of the present invention after source, drain, and gate electrodes are formed thereon.
Fig. 9 is a schematic diagram showing a monolithic heterogeneous integrated structure of a Si-based MOSFET device and a GaN-based HEMT device in an embodiment of the present invention.
Description of the element reference numerals
100-an insulating substrate; 102-bottom silicon; 106 silicon steps; 108-silicon film; 110-buried oxide layer; 200-a dielectric layer; 202-opening; 210-a lateral cavity; 310-a GaN layer; 320-AlGaN barrier layer; 410-isolation side walls; 511-source; 512-drain electrode; 520-a gate; an A-Si based device; and B-GaN devices.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
The term "gallium nitride-based group III-v compound semiconductor material" in the present application refers to a nitride semiconductor material of a group III element of the periodic table including gallium, such as GaN, GaAlN, InGaN, InAlGaN.
It should be noted that the embodiments provided in the present invention and the attached drawings only illustrate the basic idea of the invention in a schematic manner, and the components related to the invention are not drawn according to the number, shape and size of the components in actual implementation, and the type, number and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.
For purposes of clarity, the thickness of layers or regions in the figures used to describe embodiments of the present disclosure are exaggerated or reduced, i.e., the figures are not drawn on a true scale. Without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
In order to realize wafer-level monolithic hetero-integrated silicon device and III-V group device and multi-functionalization thereof, the invention provides a preparation method of a hetero-integrated structure of silicon and III-V group device on an insulating substrate, which comprises the following steps:
providing an insulator silicon-on-substrate structure, patterning top silicon of the insulator silicon-on-substrate structure to form at least one silicon step, and exposing a buried oxide layer of the insulator silicon-on-substrate structure below the periphery of the silicon step:
covering the dielectric layer on the silicon step, and patterning the top surface of the dielectric layer to form an opening exposing a part of the surface of the silicon step;
anisotropically etching the silicon step by the opening to remove the silicon step right below the opening, and further transversely removing part of the silicon step below the opening side to form a transverse cavity, wherein a silicon film is reserved at one end of the transverse cavity, which is far away from the opening;
selectively laterally growing a GaN layer from a side of the silicon film in the lateral cavity;
removing the dielectric layer to expose the silicon film and the GaN layer;
selectively forming an AlGaN barrier layer on the GaN layer;
and forming a source electrode, a drain electrode and a grid electrode on the AlGaN barrier layer to obtain the GaN device.
The hetero-integrated structure of silicon on insulator and III-V devices and the method for fabricating the same according to the present invention will be described in detail with reference to the accompanying drawings.
Referring to fig. 1, the present embodiment provides a method for preparing a coplanar hetero-integrated structure of silicon and III-V devices on an insulating substrate.
First, in step S1, a silicon-on-insulator substrate structure is provided, and the top silicon of the silicon-on-insulator substrate structure is patterned to form at least one silicon step. In the present embodiment, the soi substrate structure includes a bottom layer of silicon 102, a buried oxide layer 110, and a top layer of silicon (not shown); preferably, the top silicon has a (100) plane. In some examples, the silicon-on-insulator substrate structure 100 may be a commercially available SOI substrate. In other examples, oxygen ions may be implanted into a Si substrate by, for example, but not limited to, an ion implantation process to form a buried oxide layer 110 at a predetermined depth of the Si substrate, thereby resulting in a silicon-on-insulator substrate structure 100. Specifically, the depth of formation of the buried oxide layer in the Si substrate can be controlled by adjusting the implantation energy of the ion implantation process. Subsequently, referring to fig. 3A-3B, the top silicon of the silicon-on-insulator substrate structure is patterned, including: and defining a first pattern region corresponding to a subsequent epitaxial growth substrate on the top silicon by a photoetching process, etching the top silicon according to the first pattern region to form at least one silicon step 106, and exposing the buried oxide layer 110 of the silicon-on-insulator substrate structure below the periphery of the silicon step 106. For clarity, the figure only shows a schematic structural diagram of forming a silicon step on an insulating substrate, and the shape and/or size of the silicon step can be appropriately changed by using the silicon step as a growth base for a subsequent epitaxial process according to a practically required device type, for example, the silicon step may have a silicon island with a larger area, or a plurality of silicon nanowires with small sizes. In this embodiment, the top surface of the silicon step 106 is still formed with a (100) crystal orientation due to the protection of the developed photoresist.
Specifically, the etching process may be dry etching, for example, an Inductively Coupled Plasma (ICP) etching process; alternatively, the wet etching process may be performed using tetramethylammonium hydroxide (TMAH).
Next, in step S2, a dielectric layer is covered on the silicon step, and the top surface of the dielectric layer is patterned. In particular, a good step coverage deposition process may be employed to form the dielectric layer 200, the dielectric layer 200 conformally depositing on the silicon steps 106 and covering the sides and top surface of the silicon steps 106. By way of example, the dielectric layer 200 may be selected from SiO 2 Either a layer or a SiN layer,processes for forming the dielectric layer include, but are not limited to: conventional deposition processes such as Chemical Vapor Deposition (CVD), plasma CVD, atomic layer deposition, and other similar deposition processes; preferably, the dielectric layer may be formed using a CVD process.
Continuing to step S2, the top surface of the dielectric layer 200 is patterned, including the steps of: defining a second pattern region on the top surface of the dielectric layer 200 by a photolithography process; the dielectric layer is etched according to the second pattern region to form an opening 202 exposing a portion of the surface of the silicon step 106 for a window for a subsequent etching process. By way of example, referring to fig. 3A and 4A, the silicon step 106 may have a length L 1 The opening 202 may have a length L 1 Width L of direction 2 And L is 2 ≤0.1×L 2 . The size of the opening 202 may be appropriately determined according to the profile and/or size of the silicon step to ensure the etching rate of the silicon step in the subsequent process. In addition, the opening 202 may be disposed along the width of the silicon step 106 and disposed near one end of the dielectric layer and spaced apart from the end portion by a distance such that the opening 202 has a proximal end along the length of the silicon step 106. The position of the opening 202 can be appropriately determined as desired, and as shown in fig. 4A-4B, the opening 202 has a first spacing L from one end of the silicon step 3 And a second spacing L from the other end of the silicon step 4 Wherein L is 3 <L 4 And 0 is equal to or less than L 3 ≤L 2 。
Referring to fig. 1 and 5A-5B, at step S3: and anisotropically etching the silicon step through the opening to form a transverse cavity, wherein a silicon film is reserved at one end of the transverse cavity, which is far away from the opening. As an example, a wet etching process may be used to enter a chemical etchant through the opening 202 and etch the silicon step 106, and particularly, TMAH etchant may be used to etch the silicon material to remove the silicon step 106 directly below the opening 202 and further laterally remove a portion of the silicon step below the opening to form a lateral cavity 210, where an end of the lateral cavity 210 away from the opening remains the silicon film 108. The TMAH corrosion liquid has crystal orientation selectivity to the etching process of the silicon material, especially the etching processThe etching rate of the etching solution to the Si (100) plane is higher than that to the Si (111) plane, and has a high selectivity, so that the side surface of the silicon film 108 after the wet etching process is the Si (111) plane. In the present embodiment, the thickness of the silicon film remaining in the lateral cavity 210 may be 0.1 × L 1 。
At step S4: and selectively and laterally growing a GaN layer from the side surface of the silicon film in the lateral cavity. Preferably, a GaN layer can be laterally epitaxially grown laterally from the side of the silicon film 108 within the lateral cavity 210 selectively by a Metal Organic Chemical Vapor Deposition (MOCVD) process or a Molecular Beam Epitaxy (MBE) process. In the lateral epitaxy process, the silicon film serves as a growth substrate, and the side surface of the silicon film 108 has a (111) crystal orientation, and nucleation of GaN occurs selectively in a crystal plane of such orientation. The lateral cavity 210 may be used to define the direction of the epitaxially grown GaN layer, and may limit the setting range of the GaN layer between the silicon film 108 and the opening 202, so as to maintain the lateral growth mode of the GaN layer, which reduces the process difficulty, and also ensures the overall uniformity and crystal quality of the epitaxially grown GaN layer, which is beneficial to reducing the leakage of materials and improving the reliability of devices, compared to large-scale heterogeneous integration on a large-sized Si substrate. In this embodiment, the GaN layer may be selectively epitaxially grown at a temperature between 1000 ℃ and 1250 ℃.
Then, in step S5: and removing the dielectric layer to expose the silicon film and the GaN layer. The etching process may be appropriately selected according to the material of the dielectric layer. Specifically, the dielectric layer 200 is SiO 2 In an example of a layer, the dielectric layer defining the lateral cavity may be selectively removed by a dry etching process, which is an anisotropic etching process, such that the top surface of the lateral cavity is opened to leave the dielectric sidewall 410, as shown in fig. 7, so as to avoid damaging the buried oxide layer 110 as the mesa. The dry etching process may include, for example, reactive ion etching, ion beam etching, plasma etching, or laser etching/etching. Alternatively, in the example where the dielectric layer 200 is a SiN layer, the dielectric layer may be selectively removed by a wet etching process using a chemical etchant, as shown in fig. 6, due to the wet etching processThe SiN layer has high selectivity and thus does not affect the buried oxide layer 110 as a mesa to cause damage.
After removing the dielectric layer to reveal the silicon film and the GaN layer at step S5, step S6 is then performed: an AlGaN barrier layer is selectively formed on the GaN layer. Since the exposed silicon film surface is not etched and has a (100) crystal orientation, AlGaN preferentially nucleates on the GaN layer 310, and therefore an AlGaN barrier layer 320 may be selectively formed on the GaN layer 310, as shown in fig. 6. Similarly, the AlGaN barrier layer may be selectively epitaxially grown by an MOCVD process or an MBE process. In the present embodiment, the AlGaN barrier layer 320 may be selectively epitaxially grown on the GaN layer 310 by the MOCVD process at a second temperature between 1000 ℃ and 1250 ℃. Multiple silicon steps can be formed on the insulating substrate according to requirements, and multiple groups of spaced GaN-based III-V compound semiconductor material layers can be epitaxially grown at the same time.
Additionally, the preparation method described in this embodiment further includes: forming a single layer or multiple layers (not shown) of a group III-V compound semiconductor material different from the GaN-based group III-V compound semiconductor material in desired regions on an insulating substrate, wherein a plurality of desired regions may be defined on the insulating substrate, in process steps similar to steps S2 to S6; namely, a plurality of silicon steps are formed to integrate a plurality of epitaxial materials on the same insulating substrate, thereby realizing a plurality of functionalized devices. In particular, the III-V compound semiconductor material comprises InP, InAs, InSb, GaAs, AlAs, GaSb or a combination of the above compounds. Here, a method of manufacturing a single layer or a plurality of layers of the III-V compound semiconductor material formed on an insulating substrate will be specifically described with reference to steps S12 to S15 shown in fig. 2.
In step S11, a soi substrate structure is provided, the top silicon of the soi substrate structure is patterned to form a plurality of silicon steps, and the buried oxide layer of the soi substrate structure is exposed under the periphery of the silicon steps:
in step S12, covering the dielectric layer on each silicon step, and patterning the top surface of the dielectric layer to form an opening exposing a portion of the surface of the silicon step;
in step S13, each silicon step is anisotropically etched through the opening to remove the silicon step right under the opening, and further laterally remove a portion of the silicon step under the opening, thereby forming a plurality of lateral cavities on the insulating substrate, wherein a silicon film is retained at one end of each lateral cavity away from the opening.
In step S14, a layer of III-V compound semiconductor material is epitaxially grown laterally in at least one other of the plurality of lateral cavities, either before or after selectively epitaxially growing the GaN layer laterally from the side of the silicon film laterally in at least one of the plurality of lateral cavities.
In step S15, the dielectric layer is removed to expose the silicon film and the III-V compound semiconductor material layer.
Optionally, after step S15, selectively epitaxially growing on the III-V compound semiconductor material layer to obtain a multilayer of III-V compound semiconductor material.
Specifically, the III-V compound semiconductor material layer comprises an InGaAs layer or an InAlAs layer; accordingly, the multiple layers of III-V compound semiconductor materials may include, for example, InP/InAlAs/InP, InGaAs/GaAs/InGaAs, or other III-V compound semiconductor material combinations.
The order of steps of the epitaxial process can be properly adjusted according to the epitaxial temperature of the compound semiconductor material, so that the epitaxial growth of the III-V group semiconductor material layers is sequentially carried out from high to low temperature gradients, and therefore, various different heterogeneous integrated structures can be realized, and the performance of the whole heterogeneous integrated structure is improved. For example, the layer of III-V compound semiconductor material includes any one of an InGaAs layer and an InAlAs layer. As an example, the InGaAs and InAlAs layers may be epitaxially grown at a third temperature between 500 ℃ -600 ℃. In this embodiment, the GaN layer is laterally grown from the side of the silicon film at a first temperature, and the AlGaN barrier layer is epitaxially grown at a second temperature; and epitaxially growing the III-V compound semiconductor material layer at a third temperature, wherein the first temperature, the second temperature and the third temperature have a temperature gradient from high to low in sequence. The growth of the desired epitaxial layer may be continued at step S16 to obtain a hetero-integrated structure of silicon and III-V devices on the insulating substrate. It should be noted that: although described herein in connection with the steps of fabricating layers of InGaAs and InAlAs compound semiconductor materials, other suitable III-V semiconductor materials, such as InP, InAs, GaAs, GaSb, or combinations thereof, may be used without departing from the spirit of the present invention.
Referring to fig. 7, in step S7, a source, a drain, and a gate are formed on the AlGaN barrier layer to obtain a GaN device. The GaN device may be a GaN-based HEMT device, a Heterojunction Field Effect Transistor (HFET) device, or a MOSFET device. Here, the manufacturing method is further described in conjunction with a specific structure of the GaN-based HEMT device. At step S7: the steps of forming the source 511 and the drain 512 include: performing a photoetching process through a mask to define pattern areas of the metal source electrode and the metal drain electrode; depositing metal Ti/Al/Ni/Au, and stripping a mask; and performing an annealing process to enable the metal source and the metal drain to form ohmic contact on the surface of the AlGaN barrier layer. Alternatively, after the source and drain electrodes 511 and 512 are formed, a first passivation layer including SiN may be grown for surface passivation by, for example, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, which is advantageous in suppressing an interface defect caused by a crystal defect of the surface of the heterojunction material X Or SiO 2 。
In addition, the step of forming the gate electrode 520 includes: performing a photolithography process through a mask to define a gate trench in the first passivation layer; multiple layers of metal, such as Ni/Au, are deposited in the gate trench to form a metal gate. It is to be understood that the method for forming the source 511, the drain 512 and the gate 520 is not limited thereto, and the specific steps and the sequence of the steps for preparing the corresponding structures may be appropriately adjusted according to the needs.
Alternatively, after step S7, a Si-based MOSFET device can be prepared based on the silicon film 108 as desired; and forming a cascode cascade GaN-based HEMT device.
Specifically, after forming source and drain regions in the silicon film 108 by, for example, an ion implantation process, a gate electrode 620 may be formed on the surface of the silicon film. Subsequently, a second passivation layer can be formed on the surface of the GaN-based HEMT device and a third passivation layer can be formed on the surface of the Si-based MOSFET device for passivation protection of the device surface. Then, defining contact holes corresponding to a source electrode, a drain electrode and a grid electrode of the GaN-based HEMT device in the second passivation layer through a photoetching process, and defining contact holes corresponding to a source region, a drain region and a grid electrode of the Si-based MOSFET device in the third passivation layer; depositing metal in the contact hole to realize electrical leading-out; the remaining photoresist is stripped while the metal covering the photoresist surface is removed. And forming an interconnection electrode to electrically connect the source region of the Si-based MOSFET device with the source electrode of the GaN-based HEMT device and electrically connect the grid electrode of the Si-based MOSFET device with the grid electrode of the GaN-based HEMT device, thereby forming the cascade-connected GaN-based HEMT device. By heterologously integrating the Si-based MOSFET device and the GaN device on the same substrate and controlling the on-off of the GaN device through the Si-based MOSFET device, the advantages of the GaN cascode device in the aspects of power gain and stability are exerted.
Referring to fig. 8, the present embodiment further provides a monolithic heterogeneous integrated structure of silicon and III-V devices on an insulating substrate, which can be prepared by the above preparation method, but is not limited thereto, and details regarding the material and preparation method of the monolithic heterogeneous integrated structure are not described herein.
The monolithic heterogeneous integrated structure of silicon and III-V devices on the insulating substrate comprises: an insulating substrate including a buried oxide layer 110 as a mesa; at least one silicon film 108 on the mesa; a GaN device, comprising: a GaN layer 310 grown laterally from the silicon film 108, the GaN layer being disposed coplanar with the silicon film 108 and having a thickness corresponding to a height of the silicon film; an AlGaN barrier layer 320 on the GaN layer, the AlGaN barrier layer being disposed in a thickness direction of the GaN layer and perpendicular to a growth direction of the GaN layer.
As an example, the monolithic hetero-integrated structure further includes a single layer or multiple layers of III-V compound semiconductor material different from GaN-based III-V compound semiconductor material disposed on the insulating substrate, the single layer or multiple layers of III-V compound semiconductor material disposed coplanar with the silicon film to hetero-integrate a plurality of materials on the insulating substrate, thereby realizing wafer-level monolithic hetero-integrated multi-function devices. In particular, the layer or layers of III-V compound semiconductor material comprise InP, InAs, InSb, GaAs, AlAs, GaSb, or combinations thereof. For example, monolithically heterointegrated III-V HEMT devices and Si-based CMOS devices can be fabricated for millimeter wave communication based on the monolithic heterointegrated structures, as well as hybrid integration of III-V lasers with silicon-based photonic devices based on CMOS processes. In addition, as shown in fig. 9, a cascode-type GaN-based HEMT device may be prepared based on a monolithic heterogeneous integrated structure of silicon and III-V devices on an insulating substrate, which includes a GaN-based HEMT device a and a Si-based MOSFET device B, a source region of the Si-based MOSFET device is electrically connected to a source of the GaN-based HEMT device through an interconnection electrode, and a gate of the Si-based MOSFET device is electrically connected to a gate of the GaN-based HEMT device, and this arrangement may be applied to microwave and millimeter wave power amplifiers for communications, instruments, military applications, etc., such as Monolithic Microwave Integrated Circuits (MMICs).
In summary, the hetero-integrated structure with coplanar silicon and III-V devices on the insulating substrate and the preparation method thereof can adopt the Si-based insulating substrate to carry out hetero-integration, utilize the lateral growth of the GaN layer from the side surface of the silicon film, and reduce the stress accumulation caused by lattice mismatch and thermal mismatch between the GaN epitaxial layer and the substrate by reducing the contact area of the growth substrate and the GaN layer, thereby reducing the probability of generating threading dislocation and being beneficial to obtaining the high-quality epitaxial layer; the device can realize multiple functions on the same substrate, wherein the GaN layer grows along the transverse direction and has a semipolar surface in the vertical direction, two-dimensional electron gas (GaN) with higher concentration can be generated at the GaN/AlGaN heterojunction, and meanwhile, a leakage channel can be reduced.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (13)
1. A method for preparing a monolithic heterogeneous integrated structure of silicon and III-V devices on an insulating substrate is characterized by comprising the following steps:
providing an insulator silicon-on-substrate structure, patterning top silicon of the insulator silicon-on-substrate structure to form at least one silicon step, and exposing a buried oxide layer of the insulator silicon-on-substrate structure below the periphery of the silicon step:
covering the silicon step with a dielectric layer, and patterning the top surface of the dielectric layer to form an opening exposing a part of the surface of the silicon step;
anisotropically etching the silicon step by the opening to remove the silicon step right below the opening, and further transversely removing part of the silicon step below the opening side to form a transverse cavity, wherein a silicon film is reserved at one end of the transverse cavity, which is far away from the opening;
selectively laterally growing a GaN layer from a side of the silicon film in the lateral cavity;
removing the dielectric layer to expose the silicon film and the GaN layer;
selectively forming an AlGaN barrier layer on the GaN layer;
and forming a source electrode, a drain electrode and a grid electrode on the AlGaN barrier layer to obtain the GaN device.
2. The method of claim 1, wherein: the silicon steps comprise silicon islands or silicon nanowires and have a length L 1 The opening has a width L in the length direction of the silicon step 2 And L is 2 ≤0.1×L 1 。
3. The method of claim 2, wherein: the opening has a first distance L from one end of the silicon step in the length direction of the silicon step 3 And a second distance L from the other end of the silicon step 4 Wherein L is 3 <L 4 And 0 is equal to or less than L 3 ≤L 2 。
4. The production method according to claim 1, characterized in that: anisotropically etching the silicon step with a TMAH etchant to expose a Si (111) plane on the side surface of the silicon film, and then performing a step of laterally growing a GaN layer selectively from the side surface of the silicon film, the GaN layer having the following length in the lateral direction: the length does not exceed the spacing between the silicon film and the opening to maintain the GaN layer in a laterally grown manner.
5. The method of manufacturing according to claim 1, further comprising: forming a single layer or multiple layers of III-V compound semiconductor materials different from GaN series III-V compound semiconductor materials on the insulating substrate, wherein the III-V compound semiconductor materials comprise InP, InAs, InSb, GaAs, AlAs, GaSb or combination of the above compounds.
6. The method of claim 5, wherein forming the one or more layers of III-V compound semiconductor material on the insulating substrate comprises:
forming a plurality of silicon steps on the insulating substrate, and correspondingly forming a plurality of transverse cavities on the basis of the plurality of silicon steps;
selectively laterally epitaxially growing a layer of a III-V compound semiconductor material from a side of a silicon film within at least one other lateral cavity of the plurality of lateral cavities, either before or after selectively laterally epitaxially growing the GaN layer within at least one of the plurality of lateral cavities, wherein the layer of III-V compound semiconductor material comprises an InGaAs layer or an InAlAs layer.
7. The method of manufacturing according to claim 6, further comprising: laterally growing the GaN layer from a side of the silicon film at a first temperature, epitaxially growing the AlGaN barrier layer at a second temperature; and epitaxially growing the III-V compound semiconductor material layer at a third temperature, wherein the first temperature, the second temperature and the third temperature have a temperature gradient from high to low in this order.
8. The method of claim 1, wherein the step of providing the silicon-on-insulator substrate structure comprises: providing a silicon substrate; and forming a buried oxide layer at a predetermined depth of the silicon substrate through an ion implantation process, wherein the surface of the silicon substrate has a Si (100) plane.
9. The method of claim 1, further comprising the steps of:
the dielectric layer is SiO 2 The dielectric layer is removed through a dry etching process; or
And selectively removing the dielectric layer by a wet etching process, wherein the dielectric layer is an SiN layer.
10. The method of claim 1, further comprising the steps of: and preparing a Si-based MOSFET device based on the silicon film, wherein the GaN device is a GaN-based HEMT device, and the source region of the Si-based MOSFET device is electrically connected with the source electrode of the GaN-based HEMT device by forming an interconnection electrode, and the grid electrode of the Si-based MOSFET device is electrically connected with the grid electrode of the GaN-based HEMT device so as to form the cascade-connected GaN-based HEMT device.
11. A monolithic hetero-integrated structure of silicon and III-V devices on an insulating substrate, the monolithic hetero-integrated structure comprising:
an insulating substrate including a buried oxide layer as a mesa;
at least one silicon film on the mesa;
a GaN device, comprising:
a GaN layer laterally grown from the silicon film, the GaN layer being disposed coplanar with the silicon film and having a thickness that is consistent with a height of the silicon film;
an AlGaN barrier layer on the GaN layer, the AlGaN barrier layer being disposed in a thickness direction of the GaN layer and perpendicular to a growth direction of the GaN layer.
12. The monolithic heterogeneous integrated structure of claim 10, wherein: the insulating substrate is further provided with a single layer or multiple layers of III-V compound semiconductor materials different from GaN-based III-V compound semiconductor materials, wherein the single layer or multiple layers of III-V compound semiconductor materials are arranged coplanar with the silicon film and comprise InP, InAs, InSb, GaAs, AlAs, GaSb or the combination of the compounds.
13. A cascode-type GaN-based HEMT device prepared based on the monolithic heterogeneous integrated structure of silicon and III-V devices on an insulating substrate according to claim 11.
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