CN114695525A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

The embodiment of the invention provides a semiconductor device and a preparation method of the semiconductor device, and relates to the technical field of microelectronics, the semiconductor device comprises a substrate, a semiconductor layer, a metal electrode and a metal connecting layer, the semiconductor layer is positioned on one side of the substrate, the metal electrode is positioned on one side of the semiconductor layer away from the substrate, the metal electrode comprises a source electrode, the metal connecting layer is positioned on one side of the source electrode away from the substrate and is connected with the source electrode, the metal connecting layer is divided into at least two metal connecting blocks by an isolation structure, so that in the process of depositing and forming the metal connecting layer, redundant metal positioned on one side of the metal connecting layer can be connected with corresponding metal deposits at the isolation structure, the area of the metal deposits to be stripped is larger, the stripping of the redundant metal is easier, the stripping process of a field plate is safer, the structure and the metal connecting layer can not be damaged, the manufacturing process difficulty of the metal connecting layer and the field plate structure is reduced, and the manufacturing efficiency is improved.

Description

Semiconductor device and preparation method of semiconductor device

technical field

The present invention relates to the technical field of microelectronics, and in particular, to a semiconductor device and a method for preparing the semiconductor device.

Background technique

The semiconductor material gallium nitride has become a research hotspot due to its large band gap, high electron saturation drift velocity, high breakdown field strength, and good thermal conductivity. In terms of electronic devices, gallium nitride materials are more suitable for manufacturing high temperature, high frequency, high voltage and high power devices than silicon and gallium arsenide, so gallium nitride-based electronic devices have good application prospects.

Generally in semiconductor devices, a conductive interconnect metal layer is usually provided on the source metal electrode to connect other external structures, such as connecting the field plate structure. The field plate structure is often used to adjust the electric field. How to design the process during manufacturing The relationship with the layout of the conductive metal layer, the field plate and the surrounding structure will closely affect the reliability and stability of the device, as well as the difficulty of process manufacturing.

SUMMARY OF THE INVENTION

The objects of the present invention include, for example, to provide a semiconductor device and a method for fabricating the semiconductor device, which can match the field plate structure, reduce the difficulty of the process, and improve the fabrication efficiency.

Embodiments of the present invention can be implemented as follows:

In a first aspect, the present invention provides a semiconductor device, comprising:

substrate;

a semiconductor layer on one side of the substrate;

a metal electrode located on the side of the semiconductor layer away from the substrate, the metal electrode comprising a source electrode;

and a metal connection layer located on the side of the source away from the substrate and connected to the source;

Wherein, an isolation structure is provided on the metal connection layer, and the isolation structure separates the metal connection layer into at least two metal connection blocks.

In an optional embodiment, the isolation structure is hollow or filled with a dielectric material.

In an optional embodiment, the isolation structure includes at least two separation line portions, at least two of the separation line portions intersect, and separate the metal connection layer into at least two metal connection blocks.

In an alternative embodiment, each of the separation line portions extends to the edge of the metal connection layer.

In an optional embodiment, the width of each of the dividing line portions is greater than or equal to 2 microns.

In an optional embodiment, the semiconductor device further includes a dielectric layer, the dielectric layer is located on a side of the semiconductor layer away from the substrate, and at least two of the metal connection blocks are connected to the dielectric layer.

In an optional embodiment, the projected area S1 of the metal connection layer on the substrate is 0.4-1.6 times the projected area S2 of the source electrode on the substrate.

In a second aspect, the present invention provides a method for preparing a semiconductor device, comprising:

making a semiconductor layer on one side of the substrate;

forming a source electrode, a gate electrode and a drain electrode on the side of the semiconductor layer away from the substrate;

forming a metal connection layer on the side of the source electrode away from the substrate;

Wherein, the metal connection layer is connected to the source electrode, and an isolation structure is disposed on the metal connection layer, and the isolation structure separates the metal connection layer into at least two metal connection blocks.

In an optional implementation manner, before the step of forming a metal connection layer on the side of the source electrode away from the substrate, the method further includes:

A dielectric layer is formed on the side of the semiconductor layer away from the substrate.

In an optional implementation manner, the step of forming a metal connection layer on the side of the source electrode away from the substrate includes:

Coating a first photoresist layer on the side of the dielectric layer away from the substrate, and developing the shape of the source electrode;

etching and removing the dielectric layer on the side of the source electrode away from the substrate;

Coating a second photoresist layer on the side of the source electrode away from the substrate, and developing the shape of the metal connection layer;

performing metal deposition on the side of the second photoresist layer away from the substrate;

The metal deposition corresponding to the isolation structure is stripped, and the metal connection layer is formed.

The beneficial effects of the embodiments of the present invention include, for example:

The semiconductor device and its preparation method provided by the present invention realize the connection with the field plate structure by arranging a metal connection layer on the source electrode, and meanwhile, an isolation structure is arranged on the metal connection layer, and the isolation structure separates the metal connection layer into at least two a metal connection block, so that in the process of depositing to form a metal connection layer, the excess metal on one side of the metal connection layer can be connected with the corresponding metal deposit at the isolation structure, and the area of the metal deposit to be peeled off increases, so that the peeling off It is easier, the peeling metal is not easy to break, and the peeling process is safer, the field plate structure and the metal connection layer are not damaged, the manufacturing process difficulty of the metal connection layer and the field plate structure is reduced, and the manufacturing efficiency is improved.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of a semiconductor device provided by a first embodiment of the present invention from a first viewing angle;

FIG. 2 is a schematic structural diagram of the semiconductor device provided by the first embodiment of the present invention from a second viewing angle;

FIG. 3 is a schematic diagram of the connection structure between the semiconductor device and the field plate structure provided by the first embodiment of the present invention;

4 is a schematic structural diagram of a semiconductor device provided by a second embodiment of the present invention;

FIG. 5 is a schematic diagram of the connection structure between the semiconductor device and the field plate structure provided by the second embodiment of the present invention;

FIG. 6 is a block diagram of steps of a method for fabricating a semiconductor device according to a third embodiment of the present invention.

Icon: 100-semiconductor device; 110-substrate; 130-semiconductor layer; 131-nucleation layer; 133-buffer layer; 135-channel layer; 137-barrier layer; 150-metal electrode; 151-source electrode; 153-gate; 155-drain; 170-metal connection layer; 171-isolation structure; 173-metal connection block; 175-separation line part; 190-dielectric layer;

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. The components of the embodiments of the invention generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

Thus, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings, or It is the orientation or positional relationship that the product of the invention is usually placed in use, only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation , so it should not be construed as a limitation of the present invention.

In addition, where the terms "first", "second" and the like appear, they are only used to differentiate the description, and should not be construed as indicating or implying relative importance.

As disclosed in the Background Art, in existing semiconductor devices, such as high electron mobility transistors, the connection to the source field plate is achieved through a conductive interconnect metal layer disposed on the source electrode, and the conductive interconnect metal layer is integrally deposited. structure, which mainly plays the role of connecting the source field plate and the source electrode. In the preparation process, the conductive metal interconnection layer and the source field plate need to be formed by a metal deposition process. After the metal deposition, it needs to be peeled off. The excess metal around the source field plate connected to the external passive area and the conductive interconnection metal layer and the source field need to be peeled off. The extra steps between the plates need to be peeled off, and the peeling process is very troublesome, and it is easy to damage the structure of the source field plate, which makes the fabrication process of the device abruptly difficult and reduces the fabrication efficiency.

In order to solve the above problems, the present invention provides a semiconductor device. It should be noted that the features of the embodiments of the present invention can be combined with each other without conflict.

first embodiment

Referring to FIGS. 1 to 3 , the present embodiment provides a semiconductor device 100 that can match the field plate structure 200 , making the metal stripping process simpler, safer, and more reliable, reducing process difficulty and improving manufacturing efficiency.

The semiconductor device 100 provided in this embodiment includes a substrate 110 , a semiconductor layer 130 , a metal electrode 150 and a metal connection layer 170 . One side, wherein the metal electrode 150 includes the source electrode 151, the metal connection layer 170 is located on the side of the source electrode 151 away from the substrate 110, and is connected to the source electrode 151, wherein the metal connection layer 170 is provided with an isolation structure 171, the isolation structure 171 separates the metal connection layer 170 into at least two metal connection blocks 173 .

In this embodiment, the isolation structure 171 is used to separate the metal connection layer 170 into at least two metal connection blocks 173 , and the metal connection layer 170 can be used to connect electrical components such as the field plate structure 200 . In this embodiment, metal connection is used. The layer 170 is used to connect the field plate structure 200 as an example for illustration. In other preferred embodiments, the metal connection layer 170 may also be connected to other electrical components. By arranging the isolation structure 171, in the process of depositing and forming the metal connection layer 170, the excess metal adjacent to the field plate structure 200 and connected to the external passive region can be connected with the corresponding metal deposition at the isolation structure 171, so that In the process of depositing to form the metal connection layer, the excess metal on the side of the metal connection layer 170 can be connected with the corresponding metal deposit at the isolation structure 171, and the area of the metal deposit to be peeled off increases, thereby making the peeling easier and peeling off. The metal is not easily broken, and the peeling process is safer, and the field plate structure 200 and the metal connection layer 170 will not be damaged, which reduces the manufacturing process difficulty of the metal connection layer 170 and the field plate structure 200 and improves the manufacturing efficiency.

In this embodiment, the substrate 110 plays the role of supporting the semiconductor layer 130, and the substrate 110 may be gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, or silicon carbide , a combination of one or more of diamond, sapphire, germanium, silicon, or any other material capable of growing Group III nitrides. The deposition method of the substrate 110 may adopt CVD (Chemical Vapor Deposition, chemical vapor deposition), VPE (Vapour Phase Epitaxy, vapor phase epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition), LPCVD (Low Pressure Chemical Vapor Deposition, Low Pressure Chemical Vapor Deposition), PECVD (PlasmaEnhanced Chemical Vapor Deposition, Plasma Enhanced Chemical Vapor Deposition), PLD (Pulsed Laser Deposition, Pulsed Laser Deposition), Atomic Layer Epitaxy, MBE (Molecular Beam Epitaxy, Molecular Beam Epitaxy) , sputtering, evaporation, etc.

In this embodiment, a semiconductor layer 130 is formed on the substrate 110, and the preparation method of the semiconductor layer 130 may be MOCVD, MBE, atomic layer epitaxy, or the like. The semiconductor layer 130 may include a nucleation layer 131, a buffer layer 133, a channel layer 135, and a barrier layer 137 stacked in sequence, wherein the nucleation layer 131 is located on one side of the substrate 110, and the buffer layer 133 is located on the nucleation layer 131 away from the substrate. On the side of the bottom 110 , the channel layer 135 is located on the side of the buffer layer 133 away from the substrate 110 , the barrier layer 137 is located on the side of the channel layer 135 away from the substrate 110 , and the barrier layer 137 and the channel layer 135 are formed. Heterojunction. The buffer layer 133 plays the role of bonding other semiconductor layers 130 to grow next, specifically bonding the substrate 110 and the channel layer 135, and can also protect the substrate 110 from being invaded by some metal ions. The buffer layer 133 is made of aluminum. Content-controlled AlGaN. The channel layer 135 is deposited and grown on the buffer layer 133, and the channel layer 135 is used to provide a channel for two-dimensional electron gas (2DEG) movement. The channel layer 135 may be one or more of undoped, n-type doped or n-type partially doped GaN, AlGaN, InAlN or AlN. The barrier layer 137 is deposited and grown on the buffer layer 133, and its deposition material can be any semiconductor material that can form a heterojunction structure with the channel layer 135, including gallium-based compound semiconductor materials or III-nitride semiconductor materials, such as InAlGaN . Specifically, AlGaN is used in this embodiment, and the Al content is controllable, 0<Al%<1. The AlGaN barrier layer 137 forms a heterojunction structure together with the underlying channel layer 135, and forms a two-dimensional electron gas (2DEG) near the channel layer 135 at the heterojunction interface.

It should be noted that the semiconductor device 100 mentioned in this embodiment includes but is not limited to: a high-power gallium nitride high electron mobility transistor (High Electron Mobility Transistor, HEMT for short) operating in a high-voltage and high-current environment, Silicon-On-Insulator (SOI) structure transistors, gallium arsenide (GaAs)-based transistors, and metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, abbreviated as SOI) on the insulating substrate 110 MOSFET), Metal-Semiconductor Field-Effect Transistor (MISFET), Double Heterojunction Field-Effect Transistor (DHFET), Junction Field Effect Transistor (Junction Field Effect Transistor) -Effect Transistor (JFET for short), Metal-Semiconductor Field-Effect Transistor (MESFET), Metal-Semiconductor Heterojunction Field-Effect Transistor (MISHFET) or other field effect transistors.

In this embodiment, the metal electrode 150 may further include a drain electrode 155 and a gate electrode 153, wherein the source electrode 151 and the drain electrode 155 are both located on the barrier layer 137, and the gate electrode 153 is located between the source electrode 151 and the drain electrode 155, And located on the barrier layer 137 , the gate 153 may be a T-shaped gate, and is used to correspond to the field plate structure 200 , so as to realize the function of adjusting the electric field through the field plate structure 200 . Specifically, there is a dielectric space between the gate electrode 153 and the field plate structure 200 , the dielectric layer 190 may be filled in the dielectric space, and the isolation structure 171 extends to the dielectric space. The source electrode 151 and the drain electrode 155 are electrically connected to the 2DEG in the semiconductor layer 130 .

In this embodiment, the isolation structure 171 may be filled with a dielectric material, air, or a combination of the two. When the isolation structure 171 is filled with air, the isolation structure 171 is hollow. When the isolation structure 171 is filled with a dielectric material, it means that the isolation structure 171 is filled with an insulating material, such as SiN or resin. By filling the insulating material, the structure of the metal connection layer 170 can be made more stable, and the device performance can be more reliable.

In this embodiment, the isolation structure 171 includes at least two dividing line parts 175 , at least two dividing line parts 175 intersect, and separate the metal connection layer 170 into at least two metal connection blocks 173 . Specifically, the dividing line portion 175 in this embodiment is linear, and in other preferred embodiments, the dividing line portion 175 may also be partially or entirely curvilinear. When applied to a single device, the plurality of dividing line portions 175 can be spliced into a T-shaped structure or an L-shaped structure, and when applied to at least two devices, the plurality of dividing line portions 175 can also be spliced into a cross-shaped structure or a rice-shaped structure. structure. Preferably, in this embodiment, the isolation structure 171 includes two dividing line parts 175, and the two dividing line parts 175 intersect in the middle to form a cross-shaped structure, and the metal connection layer 170 is divided into four metal connection blocks 173, each of which is The metal connection blocks 173 are all used for connection with the field plate structure 200 .

It should be noted that in this embodiment, the metal connection layer 170 is formed on the source electrode 151 by metal deposition. Specifically, after the surface of the source electrode 151 is coated with photoresist, the isolation structure 171 is used as a mask. The shape of the metal connection layer 170 is developed, then metal deposition is performed, and finally the excess metal is peeled off. During the peeling process, due to the existence of the isolation structure 171, the surrounding excess metal deposition is made with the metal corresponding to the isolation structure 171. The deposits can be connected, which increases the area of the metal to be stripped, thereby making the stripping of excess metal easier, and the stripping process is safer without damaging the metal connection layer 170 . Of course, the field plate structure 200 can also be formed simultaneously here. The field plate structure 200 can be integrally formed with the metal connection layer 170 , and the separation process of the field plate structure 200 is made easier and safer through the isolation structure 171 .

In this embodiment, each dividing line portion 175 extends to the edge of the metal connection layer 170 , and at least one dividing line portion 175 extends to the edge of the medium space and communicates with the medium space, so that the isolation structure 171 is connected to the medium space. It is connected to the passive region, that is, the dielectric space between the source electrode 151 and the gate electrode 153 is connected to the passive region through the isolation structure 171 .

In this embodiment, the width of each separation line portion 175 is greater than or equal to 2 microns, and the width of the separation line portion 175 is smaller than the width of the metal connection layer 170 . Preferably, the width of each dividing line part 175 is the same, so that the stability of the device can be improved. It should be noted that the width of the dividing line portion 175 in this embodiment refers to the distance between two adjacent metal connection blocks 173 .

In this embodiment, the edge of each metal connection block 173 is further provided with a connection bridge structure (not marked in the figure), through which the connection with the field plate can be realized, and the connection between the two adjacent connection bridge structures can be realized. There is at least one dividing line 175 therebetween, so that each connecting bridge structure can be connected to each independent metal connecting block 173 . The number of connection bridge structures is less than or equal to the number of metal connection blocks 173 .

In this embodiment, the projected area S1 of the metal connection layer 170 on the substrate 110 is 0.4-1.6 times the projected area S2 of the source electrode 151 on the substrate 110 . Specifically, in this embodiment, the metal connection layer 170 covers the top of the source electrode 151 . In this embodiment, the surface of the substrate 110 is used as the projection surface, and the projected area S1 of the metal connection layer 170 is different from the projection surface S2 of the source electrode 151 . It is not large, so that the preparation process is simpler and the structure is more stable, and the area difference between S1 and S2 is less than or equal to 3/5 of that of S2. Of course, the projected area of the metal connection layer 170 here includes the projected area of the metal connection block 173 and the projected area of the isolation structure 171 . When the projected area of the metal connection layer 170 above the source electrode 151 is larger than the projected area of the source electrode 151 , the metal connection layer 170 above the source electrode 151 strips off the excess metal, and after the isolation structure 171 is formed, the remaining metals are connected The projected area of the block 173 may be larger or smaller than the projected area of the source electrode 151 , which is not specifically limited herein.

To sum up, the present embodiment provides a semiconductor device 100 , which is connected to the field plate structure 200 by disposing the metal connection layer 170 on the source electrode 151 , and meanwhile, the isolation structure 171 is disposed on the metal connection layer 170 . The isolation structure 171 separates the metal connection layer 170 into at least two metal connection blocks 173, so that in the process of depositing to form the metal connection layer 170, the excess metal to be stripped can be connected with the corresponding metal deposit at the isolation structure 171, and makes The area of the metal to be peeled is increased, so that the peeling of the excess metal is easier, the peeling metal is not easy to break, and the peeling process is safer, the field plate structure 200 and the metal connection layer 170 are not damaged, and the metal connection layer 170 and the field plate structure are reduced. 200 production process difficulty, improve production efficiency.

Second Embodiment

Please refer to FIG. 4 and FIG. 5 , this embodiment provides another semiconductor device 100 , the basic structure, principle and technical effect of which are the same as those in the first embodiment. For the sake of brief description, the parts not mentioned in this embodiment are described. Please refer to the corresponding content in the first embodiment.

The semiconductor device 100 provided in this embodiment includes a substrate 110 , a semiconductor layer 130 , a metal electrode 150 , a metal connection layer 170 and a dielectric layer 190 . The semiconductor layer 130 is located on one side of the substrate 110 , and the metal electrode 150 is located away from the semiconductor layer 130 One side of the substrate 110, wherein the metal electrode 150 includes a source electrode 151, a drain electrode 155 and a gate electrode 153, the metal connection layer 170 is located on the side of the source electrode 151 away from the substrate 110, and is connected to the source electrode 151, wherein the metal An isolation structure 171 is disposed on the connection layer 170 , and the isolation structure 171 separates the metal connection layer 170 into at least two metal connection blocks 173 . The dielectric layer 190 is located on the side of the semiconductor layer 130 away from the substrate 110 , and at least two metal connection blocks 173 are connected to the dielectric layer 190 .

In this embodiment, the gate electrode 153 is located between the source electrode 151 and the drain electrode 155 , and the dielectric layer 190 covers at least the gate electrode 153 and is used to fill the dielectric space between the gate electrode 153 and the field plate. Preferably, the dielectric layer 190 covers the drain electrode 155 and the gate electrode 153 , and is provided with a trench for the field plate structure 200 to extend into. The field plate structure 200 is used to be disposed on the surface of the dielectric layer 190 on the side away from the substrate 110 . , and extend into the trenches on the dielectric layer 190 . By arranging the dielectric layer 190 , the field plate structure 200 can be better supported, and the dielectric space can be filled, so that the field plate structure 200 can adjust the electric field. The dielectric layer 190 may be a crystalline material deposited during growth or process, such as GaN or AlN, or an amorphous material deposited during growth or process, such as SiN.

In other preferred embodiments of the present invention, the dielectric layer 190 can also only cover the gate 153 and be self-aligned with the gate 153, and the rest of the dielectric space is an air dielectric, which can also ensure the field plate structure 200 effect.

In the present embodiment, the isolation structure 171 includes at least two dividing line parts 175, at least two dividing line parts 175 intersect, and divides the metal connection layer 170 into at least three metal connection blocks 173, and at least one dividing line part 175 is connected with The dielectric layer 190 is connected. Therefore, the isolation structure 171 is connected to the dielectric layer 190 and to the passive region, that is, the dielectric layer 190 between the source electrode 151 and the gate electrode 153 is connected to the passive region through the isolation structure 171 .

In the semiconductor device 100 provided in this embodiment, by additionally disposing the dielectric layer 190 , the field plate structure 200 can be better supported, and the dielectric space can be filled, so that the field plate structure 200 can adjust the electric field.

Third Embodiment

Referring to FIG. 6 , this embodiment provides a method for fabricating a semiconductor device 100 for fabricating the semiconductor device 100 as provided in the first embodiment or the second embodiment. The fabrication method for the semiconductor device 100 includes the following steps:

S1: The semiconductor layer 130 is formed on one side of the substrate 110 .

Specifically, a substrate 110 is provided, and a semiconductor layer 130 is formed on the substrate 110 . Specifically, a nucleation layer 131 , a buffer layer 133 , a channel layer 135 and a barrier layer 137 are sequentially prepared on the upper surface of the substrate 110 . The substrate 110 may be one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon. combination, or any other material capable of growing III-nitrides. The buffer layer 133 plays the role of bonding other semiconductor layers 130 to grow next, specifically bonding the substrate 110 and the channel layer 135, and can also protect the substrate 110 from being invaded by some metal ions. The buffer layer 133 is made of aluminum. Content-controlled AlGaN. The channel layer 135 is deposited and grown on the buffer layer 133, and the channel layer 135 is used to provide a channel for two-dimensional electron gas (2DEG) movement. The channel layer 135 may be one or more of undoped, n-type doped or n-type partially doped GaN, AlGaN, InAlN or AlN. The barrier layer 137 is deposited and grown on the buffer layer 133, and its deposition material can be any semiconductor material that can form a heterojunction structure with the channel layer 135, including gallium-based compound semiconductor materials or III-nitride semiconductor materials, such as InAlGaN . Specifically, AlGaN is used in this embodiment, and the Al content is controllable, 0<Al%<1. The AlGaN barrier layer 137 forms a heterojunction structure together with the underlying channel layer 135, and forms a two-dimensional electron gas (2DEG) near the channel layer 135 at the heterojunction interface.

The deposition method of the substrate 110 may adopt CVD (Chemical Vapor Deposition, chemical vapor deposition), VPE (Vapour Phase Epitaxy, vapor phase epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition), LPCVD (Low Pressure Chemical VaporDeposition, low pressure chemical vapor deposition), PECVD (Plasma Enhanced Chemical VaporDeposition, plasma enhanced chemical vapor deposition), PLD (Pulsed Laser Deposition, pulsed laser deposition), atomic layer epitaxy, MBE (Molecular Beam Epitaxy, molecular beam epitaxy), Sputtering, evaporation, etc. The preparation method of the semiconductor layer 130 may be MOCVD, MBE, atomic layer epitaxy, or the like.

S2 : forming the metal electrode 150 on the side of the semiconductor layer 130 away from the substrate 110 .

Specifically, the metal electrode 150 includes a source electrode 151, and may further include a drain electrode 155 and a gate electrode 153. The source electrode 151 and the drain electrode 155 are electrically connected to the two-dimensional electron gas (2DEG) in the semiconductor layer 130, which forms an electrical connection The methods include but are not limited to high temperature annealing, ion implantation and heavy doping. After the source electrode 151 and the drain electrode 155 are formed, a gate trench is formed on the surface of the semiconductor layer 130 through an etching process, and then metal is deposited in the exposed area of the gate electrode 153 to form the gate electrode 153, which may be a T-shaped gate.

S3 : forming a metal connection layer 170 on the side of the source electrode 151 away from the substrate 110 .

Specifically, when preparing the semiconductor device 100 as provided in the first embodiment, a photoresist layer can be directly coated on the side of the source electrode 151 away from the substrate 110 , and the metal connection can be developed using the isolation structure 171 as a mask. The shape of the layer 170 is determined, and metal deposition is performed on the side of the photoresist layer away from the substrate 110 , and the metal deposition corresponding to the isolation structure 171 and other excess metal deposition are stripped to form the metal connection layer 170 . The metal connection layer 170 is connected to the source electrode 151 , and an isolation structure 171 is disposed on the metal connection layer 170 . The isolation structure 171 separates the metal connection layer 170 into at least two metal connection blocks 173 .

It should be noted that, after the isolation structure 171 is formed, it may be filled with a dielectric material, air, or a combination of the two. The boundary of the isolation structure 171 should pass through the metal connection layer 170 above the source electrode 151 to form an opening, that is, each separation line portion 175 extends to the edge of the metal connection layer 170 .

It is worth noting that, when preparing the semiconductor device 100 provided in the second embodiment, before performing step S3, the method further includes the following steps:

A dielectric layer 190 is formed on the side of the semiconductor layer 130 away from the substrate 110 , wherein the dielectric layer 190 covers the drain electrode 155 and the gate electrode 153 . Specifically, a crystalline material (such as GaN or AlN, etc.) or an amorphous material (such as SiN, etc.) is deposited on the semiconductor layer 130 to form a dielectric layer 190 covering the source electrode 151, the drain electrode 155 and the gate electrode 153, and then a dielectric layer 190 is formed on the semiconductor layer 130. The upper surface of the dielectric layer 190 is coated with photoresist, the source electrode 151 area is exposed to light, and the shape of the source electrode 151 is developed, and then the dielectric layer 190 located above the source electrode 151 is removed by an etching process, which is convenient for subsequent source electrode 151. A metal connection layer 170 is formed above 151 . Here, the dielectric layer 190 above the source electrode 151 may be completely removed, or the dielectric layer 190 above the source electrode 151 may be partially removed, for example, 65% of the area of the dielectric layer 190 on the source electrode 151 may be removed. Here, it is only necessary to expose the source electrode 151 so that the subsequent metal connection layer 170 can be formed.

When preparing the semiconductor device 100 as provided in the second embodiment, a dielectric layer 190 is grown on the barrier layer 137, then a layer of photoresist is coated on the dielectric, and then photolithography and etching are performed on the source electrode 151, so that the The dielectric layer 190 above the source electrode 151 is completely etched away, and then a layer of photoresist is applied. The isolation structure 171 is used as a mask to develop the shape of the metal connection layer 170 on the photoresist, and then metal deposition is performed. Finally, the excess metal deposits are stripped off. The stripped portion above the source electrode 151 is the isolation structure 171 .

In this embodiment, the metal connection layer 170 is used to connect the field plate structure 200, wherein the field plate structure 200 can be integrally formed with the metal connection layer 170, and the excess metal adjacent to the field plate structure 200 and connected to the external passive region It can be connected with the corresponding metal deposit at the isolation structure 171, thereby reducing the difficulty of stripping and making the stripping process simpler and safer. Specifically, after all the dielectric layer 190 above the source electrode 151 is etched away, a layer of photoresist is coated on the upper surface of the source electrode 151 and the upper surface of the dielectric layer 190, and the metal connection is developed on the photoresist The shape of the layer 170 and the field plate structure 200, then metal deposition is performed, and the metal connection layer 170 and the field plate structure 200 are integrally formed and the excess metal deposition is stripped.

In the preparation method of the semiconductor device 100 provided by the present invention, the connection with the field plate structure 200 is realized by disposing a metal connection layer 170 on the source electrode 151 , and meanwhile an isolation structure 171 is disposed on the metal connection layer 170 , and the isolation structure 171 connects the metal The connection layer 170 is separated into at least two metal connection blocks 173, so that in the process of depositing to form the metal connection layer 170, excess metal can be connected with the corresponding metal deposits at the isolation structure 171, and the area of the metal deposits to be stripped is larger , thereby making it easier to peel off the excess metal, reducing the manufacturing process difficulty of the metal connection layer 170 and the field plate structure 200 , and improving the manufacturing efficiency.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (10)

1. A semiconductor device, comprising:

a substrate;

a semiconductor layer on one side of the substrate;

the metal electrode is positioned on one side of the semiconductor layer, which is far away from the substrate, and comprises a source electrode;

the metal connecting layer is positioned on one side of the source electrode, which is far away from the substrate, and is connected with the source electrode;

the metal connecting layer is provided with an isolation structure, and the isolation structure divides the metal connecting layer into at least two metal connecting blocks.

2. The semiconductor device of claim 1, wherein the isolation structure is hollowed out or filled with a dielectric material.

3. The semiconductor device according to claim 1, wherein the isolation structure comprises at least two dividing line portions, at least two of the dividing line portions intersecting and dividing the metal connection layer into at least two of the metal connection blocks.

4. The semiconductor device of claim 3, wherein each of the dividing line portions extends to an edge of the metal connection layer.

5. The semiconductor device according to claim 3, wherein a width of each of the dividing line portions is greater than or equal to 2 μm.

6. The semiconductor device according to claim 1, further comprising a dielectric layer on a side of the semiconductor layer away from the substrate, wherein at least two of the metal connection blocks are connected to the dielectric layer.

7. The semiconductor device according to any one of claims 1 to 6, wherein a projected area S1 of the metal connection layer on the substrate is 0.4 to 1.6 times a projected area S2 of the source electrode on the substrate.

8. A method of manufacturing a semiconductor device, comprising:

manufacturing a semiconductor layer on one side of a substrate;

manufacturing a metal electrode on one side of the semiconductor layer far away from the substrate, wherein the metal electrode comprises a source electrode;

manufacturing a metal connecting layer on one side of the source electrode, which is far away from the substrate;

the metal connecting layer is connected with the source electrode, an isolating structure is arranged on the metal connecting layer, and the isolating structure divides the metal connecting layer into at least two metal connecting blocks.

9. The method for manufacturing a semiconductor device according to claim 8, wherein before the step of forming a metal connection layer on a side of the source electrode away from the substrate, the method further comprises:

and manufacturing a dielectric layer on one side of the semiconductor layer far away from the substrate.

10. A method for manufacturing a semiconductor device according to claim 8 or 9, wherein the step of forming a metal connection layer on the side of the source electrode away from the substrate comprises:

coating a photoresist layer on one side of the source electrode, which is far away from the substrate, and developing the shape of the metal connecting layer;

performing metal deposition on one side of the photoresist layer far away from the substrate;

and stripping the metal deposit corresponding to the isolation structure and forming the metal connecting layer.

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