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CN103378017B - 高密度3d封装 - Google Patents

高密度3d封装 Download PDF

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Publication number
CN103378017B
CN103378017B CN201310146041.7A CN201310146041A CN103378017B CN 103378017 B CN103378017 B CN 103378017B CN 201310146041 A CN201310146041 A CN 201310146041A CN 103378017 B CN103378017 B CN 103378017B
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power
low
insert
chip
die
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CN103378017A (zh
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姜泽圭
翟军
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Nvidia Corp
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Nvidia Corp
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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

本发明的实施例提供集成电路系统，其包括具有穿过插入件的多个导电过孔的插入件，安装在插入件的第一表面上的一个或多个高功率芯片，其中一个或多个高功率芯片在正常运行期间生成至少10W的热量，安装在插入件的第二表面上的一个或多个低功率芯片，其中一个或多个低功率芯片在正常运行期间生成小于5W的热量，并且第一和第二表面彼此相对并且大体平行，以及在一个或多个高功率芯片和一个或多个低功率芯片上形成的并配置为包封一个或多个高功率芯片和一个或多个低功率芯片的包封材料。由于低功率芯片和高功率芯片分别安装在插入件的正面和背面，所以插入件的占地面积和与其相关联的制造成本得到减少。

Description

高密度3D封装
技术领域
本发明的实施例总地涉及集成电路芯片封装，并且，更具体地，涉及具有高功率芯片和低功率芯片的三维系统级封装。
背景技术
现有技术电子设备的尺寸日益减小。为减少电子设备的尺寸，将微处理器、存储器设备和其他半导体设备封装并与电路板装配在一起的结构必须更加紧凑。
在集成电路芯片的封装中，已开发出大量装配技术来减少集成电路和电路板的装配的整体大小。例如，倒装芯片焊接（flip-chipbonding）技术是用来提供具有改进的集成密度的集成电路封装系统的装配方法之一。图1示出常规倒装芯片封装结构100的示意性截面视图。倒装芯片结构100一般包括半导体设备102，诸如由其后表面安装在插入件104的上表面上的高功率芯片102a和低功率芯片102b。用焊料凸块108将插入件104直接束缚在封装基板106的上表面上。随后用焊料球112将封装基板106安装到印刷电路板（PCB）110上，使能半导体设备102和PCB110之间的电连接。倒装芯片封装结构与其中用在封装基板上所承载的相对厚的金属线和对应的焊盘将半导体设备（诸如高/低功率芯片）打线结合到封装基板的传统打线结合（wire-bonding）技术的集成电路封装系统相比，提供用经减少的封装大小和更短的互连距离将半导体设备互连到外部电路的优点。
图1中所示的封装结构的布置的一个优点是，高功率芯片102a和低功率芯片102b安装在插入件的同一侧上，以获得更大的集成电路封装密度。因此，要求插入件的大得多的占地面积（footprint）。进一步地，制造插入件的工艺，特别是基于硅穿孔的插入件的工艺，复杂且很昂贵，因为其通过使用穿过插入件的导电过孔（via）（例如导电过孔116b）提供半导体设备和底层的PCB之间垂直电互连、以及通过使用导电连接（例如导电连接116a）提供水平并肩布置的半导体设备之间的平面内电互连。已存在的多裸片封装不但增大插入件的占地面积并因此在封装基板上强加更重的路由负担，而且还增大由于插入件的高复杂性以及诸如凸块间距限制的生产挑战而出现的与插入件制造相关联的成本，特别是在当寻求将不同集成电路垂直地组合在单个封装中的时候。
因此，本领域中需要具有封装大小和互连距离相应减少的较大密度的集成电路的成本有效的封装系统。
发明内容
本发明的一个实施例提供集成电路系统，其通常包括具有穿过插入件的多个导电过孔的插入件，安装在插入件的第一表面上的一个或多个高功率芯片，其中一个或多个高功率芯片在正常运行期间生成至少10W的热量，安装在插入件的第二表面上的一个或多个低功率芯片，其中一个或多个低功率芯片在正常运行期间生成小于5W的热量，并且第一表面和第二表面彼此相对并且大体平行，以及在一个或多个高功率芯片和一个或多个低功率芯片上形成的并配置为包封一个或多个高功率芯片和一个或多个低功率芯片的包封材料。
本发明的一个优点是低功率芯片和高功率芯片分别安装在插入件的正面和背面，与已经存在的高功率和低功率芯片置于（place）插入件的同一侧的多裸片封装相反。因此，插入件的占地面积和与其相关联的生产成本减少。此外，因为插入件将低功率芯片与高功率芯片热隔离，因此低功率芯片可位于接近高功率芯片处而不受到由高功率芯片所生成的热量的不利影响。这种紧密接近和直接穿过插入件体的导电过孔有利地缩短高功率和低功率芯片之间的互连的路径长度，这改进了设备性能并减少IC系统中的互连寄生。
附图说明
因此，可以详细地理解本发明的上述特征，并且可以参考实施例得到对如上面所简要概括的本发明更具体的描述，其中一些实施例在附图中示出。然而，应当注意的是，附图仅示出本发明的典型实施例，因此不应被认为是对其范围的限制，本发明可以具有其他等效的实施例。此外，附图中的图示不是按比例绘制而是提供用于图示目的。
图1是常规倒装芯片封装结构的示意性截面视图。
图2A是根据本发明的一个实施例的、集成电路（IC）系统的示意性截面视图。
图2B是示出插入件和低功率芯片之间的电连接的、经放大的局部截面视图。
图3A是根据本发明的一个实施例的、示出插入件关于高功率和低功率芯片的示例性的位置关系的集成电路（IC）系统的示意性俯视图。
图3B是沿图3A的线A-A获得的截面视图。
图4A是根据本发明的另一个实施例的、示出插入件关于高功率和低功率芯片的示例性的位置关系的集成电路（IC）系统的示意性俯视图。
图4B是沿图4A的线B-B获得的截面视图。
图5示出根据本发明的一个实施例的、用来形成集成电路（IC）系统的示例性处理顺序。
图6A-6F示出在图5所示的处理顺序的不同阶段的插入件的示意性截面视图。
图7是根据本发明的又一个实施例的、集成电路（IC）系统的示意性截面视图。
为了便于理解，在可能的地方已使用同样的参考数字以标记对图是通用的同样的元件。应理解的是，在一个实施例中所公开的元件可被有利地利用在其他实施例中而不用特定复述。
具体实施方式
本发明提供其中一个或多个低功率芯片安装在插入件的一侧上，而一个或多个高功率芯片安装在插入件的另一侧上的系统。插入件具有穿过插入件以电连接低和高功率芯片的多个导电过孔。在各种实施例中，低功率芯片和高功率芯片被包封以防止由于部件之间的不同热膨胀系数而出现的芯片和插入件之间的相对移动。低功率芯片可按并排式配置放置使得每个低功率芯片偏离每个高功率芯片的中心，允许从电源到高功率芯片的更快的、直接的功率馈送而不用经历与低功率芯片相关联的电阻损耗。在一个实施例中，系统可配置为使一个或多个低功率芯片放置在封装基板的表面中所形成的腔内来进一步减少整体封装外形。下文更具体地描述本发明的细节。
图2A是根据本发明的一个实施例的、集成电路（IC）系统200的示意性截面视图。IC系统200包括多个半导体设备，诸如IC芯片和/或其他分立的微电子部件，并配置为电地和机械地将所述芯片和部件连接到印刷电路板（PCB）290。如下文所更具体地讨论，在本发明的各种实施例中，IC系统200可包括一个或多个高功率芯片201、插入件204、以及一个或多个低功率芯片202的堆叠配置，其中一个或多个低功率芯片202可以倒装芯片地凸出（bump）在插入件204的第一表面206a上，而一个或多个高功率芯片201可凸出在插入件204的第二表面206b上。插入件204的第一表面206a和第二表面206b彼此相对并且大体平行。一个或多个低功率芯片202由插入件204将其与一个或多个高功率芯片201热隔离，并且因此不受高功率芯片201显著影响。特别地，与高功率和低功率芯片置于插入件的同一面的已存在的多裸片封装相反，由于高功率芯片201和低功率芯片202分别接附在插入件204的正面和背面，因此插入件204的占地面积减小。
插入件204包括用于堆叠芯片的多个硅穿孔（TSV）205。TSV205适用于作为贯穿插入件204的功率、接地、以及信号的互连，来促进垂直堆叠的芯片例如高功率芯片201和低功率芯片202之间的电连接。具体地，TSV205是穿过插入件204的“微过孔”，以有效提供高功率芯片201和低功率芯片202之间的垂直电连接，而不是像传统3D封装中所一般使用的经过芯片边上的侧壁。因此，TSV205提供路径长度很短的高功率芯片201和低功率芯片202之间的互连。
高功率芯片201可以是在高电压运行的任意半导体设备，诸如中央处理单元（CPU）、图形处理单元（GPU）、应用处理器或其他逻辑设备、或在运行期间生成足够热量来不利地影响位于IC系统200中的低功率芯片202或无源设备的性能的任意IC芯片。“高功率芯片”如本文所定义，是在正常运行期间生成至少10W或更高热量的任意IC芯片。高功率芯片201安装在插入件204的表面上，诸如第二表面206b，并通过电连接207电连接到插入件204的第二表面206b。可使用本领域已知的任意技术上可行的方法做出高功率芯片201和插入件204之间的电连接207，包括但不限于将安置于高功率芯片201的一侧203a上的焊料凸块208接附到插入件204的第二表面206b上形成的焊盘（未示出）上。焊料凸块208包括铜或另一种导电材料，另一种导电材料诸如铝、金、银或两个或更多个元素的合金。可替代地，可通过将高功率芯片201上的针栅阵列（PGA）机械地压入在插入件204中形成的通孔来做出这种电连接。如果需要，可通过用包封材料210保护焊料凸块208来改进焊料凸块208的可靠性。包封材料210可以是树脂，诸如环氧树脂、丙烯酸树脂、硅树脂、聚氨酯树脂、聚酰胺树脂、聚酰亚胺树脂等。
高功率芯片201的一侧203a靠着插入件204安装，并且高功率芯片201的背对插入件204的相对侧203b可用于散热器或其他冷却机构以接附于其上。在图2A所示出的实施例中，高功率芯片201的一侧203b热耦连到散热器212来提高IC系统200的传热。
低功率芯片202可以是在比高功率芯片201的电压相对低的电压上运行的任意半导体设备。低功率芯片202可以是位于IC系统200中的无源设备、诸如RAM、闪存等的存储器设备、I/O芯片、或在运行期间不生成足够热量来不利地影响临近的IC芯片或设备的性能的任意其他芯片。“低功率芯片”如本文所定义的，是在正常运行期间生成近似大约1W、即不超过大约5W的热量的任意IC芯片。低功率芯片202由其背表面216b安装到插入件204的表面上，诸如第一表面206a，并使用能够在插入件204和低功率芯片202之间建立电接触的本领域已知的任意技术上可行的方法电连接到插入件204的第一表面206a上的电连接。图2B是示出插入件204和低功率芯片202之间的使用微凸块（microbump）218的电连接的一个实施例的、经放大的局部截面视图。微凸块218可由包封材料220所包封以提高微凸块218的可靠性。可替代地或另外地，可由包封材料224来提高微凸块218的可靠性，该包封材料224保护整个低功率芯片202并防止由于高功率芯片201、插入件204和低功率芯片202之间不同的热膨胀系数而出现的整个低功率芯片202与插入件204和封装基板214的任意相对移动。在一些使用包封材料224的情况下，可省去包封材料220。
低功率芯片212的另一侧，即前表面216a，可通过本领域中已知的任意技术上可行的方法安装到封装基板214，诸如焊料凸块或导电接附材料。在图2A所示的一个实施例中，使用裸片接附材料215。然而，只要低功率芯片202保持电连接到封装基板214，那么可省略裸片接附材料215。例如，低功率芯片202可通过焊料凸块226电连接到封装基板214，该焊料凸块226置于插入件204和封装基板214之间对应于高功率芯片201的位置的区域。在这种情况下，焊料凸块226可置于插入件204和封装基板214之间在高功率芯片201的中心下面的中间区域。焊料凸块226被提供来将插入件204（以及因此低功率芯片202）安装到封装基板214。焊料凸块226配置为提供从电源（未示出）通过导电线242到高功率芯片201的功率和/或接地信号的直接递送而不经历与低功率芯片202相关联的电阻损耗。焊料凸块226可使用微凸块、或诸如C4凸块的较大的凸块，来提供高功率芯片201和封装基板214之间的有效电连接。因此，高功率芯片201、插入件204、低功率芯片202、以及封装基板214在堆叠配置中彼此电连接。在图2A所示出的一个方面中，封装基板214可具有足以支持所有低功率芯片202并将其包封在包封材料224内的连续长度“L”，来防止封装基板214在包封处理或后续的热循环期间弯曲。
封装基板214通过导电线221和封装引脚222电连接到PCB290。封装引脚222提供IC系统200和PCB290之间的电连接，并可以是本领域中已知的任意技术上可行的芯片封装电连接，包括球栅阵列（BGA）、针栅阵列（PGA）等。虽然本文未示出，但应理解的是封装基板214可以是包括绝缘层的堆叠的层压基板。此外，嵌在封装基板214内的导电线221可包括在封装基板214内延伸的多个水平定向的电线或垂直定向的过孔以提供高和低功率芯片201、202以及PCB290之间的功率、接地和/或输入/输出（I/O）信号互连。本文所使用的术语“水平”定义为与集成电路的平面或表面平行的平面，与其定向无关。并且，术语“垂直”指的是垂直于本文所定义的水平的方向。因此封装基板214为IC系统200提供结构刚性以及电接口用于在高功率芯片201、低功率芯片202和印刷电路板290之间路由输入和输出信号和功率。
存在若干本领域中广泛知悉的合适的材料用于生产本发明的实施例中所使用的层压封装基板，该材料具有必要的机械强度、电性能以及令人满意的低热导率。这种材料可包括但不限于FR-2和FR-4，其是典型的环氧基层压制品，以及三菱瓦斯化学公司（MitsubishiGasandChemical）的树脂基双马来酰亚胺-三嗪（BT）。FR-2是热导率在约0.2W/(K-m)范围中的合成树脂粘合纸。FR-4是具有环氧树脂粘合剂的热导率在约0.35W/(K-m)范围中的编织玻璃纤维布。BT/环氧层压封装基板也具有在约0.35W/(K-m)范围中的热导率。其他刚度合适、电绝缘、并热隔离的具有热导率小于约0.5W/(K-m)的材料也可使用并且仍落在本发明的范围内。
图3A是根据本发明的一个实施例的、示出插入件关于高功率和低功率芯片的示例性的位置关系的集成电路（IC）系统300的示意性俯视图。图3B是沿图3A的线A-A获得的截面视图。在这些实施例中，高功率芯片301安装在插入件304的第一表面310上而低功率芯片302（由图3A中的虚线所指示）安装在插入件304的第二表面312上。第一表面310和第二表面312彼此相对并且大体平行。高功率芯片301、低功率芯片302以及插入件304可以是如上文关于图2A所讨论的那些高功率和低功率芯片201、202以及插入件204。类似地，使用如上文所讨论的本领域中已知的任意技术上可行的方法，诸如焊料凸块306、308，将高功率芯片301和低功率芯片302分别安装到插入件304的第一和第二表面310、312。放置高功率芯片301和低功率芯片302使得低功率芯片302与高功率芯片301部分重叠。具体地，低功率芯片302按并排式配置放置，每个低功率芯片302偏离高功率芯片301的中心（“偏心（off-center）”布置），并且当从俯视图、或以垂直于插入件304的第一表面310的观察轴“M”观察时，与高功率芯片301的边314重叠。在一个实施例中，每个低功率芯片302的输入/输出（I/O）端子303可按行对齐，或可与高功率芯片301的边314按多个行对齐。虽然仅示出四个I/O端子303，应理解的是I/O端子303的数目可变化以改进数据转移处理速度。
因为每个低功率芯片302安置于接近高功率芯片301并且仅由插入件304所分开，所以在低功率芯片302和高功率芯片301之间的互连（即TSV305）的路径长度很短。该缩短的互连距离结合低功率芯片302的“偏心”布置允许从电源（未示出）到高功率芯片301的功率和/或接地信号的更快的、直接的馈送而不用经历与低功率芯片320相关联的电阻损耗，从而满足高电流设备的功率要求。为了提供这种直接功率递送，一个或多个可以是任意合适的形式的电互连（未示出），可用来提供直接从PCB通过插入件305到高功率芯片301的功率和/或接地信号。例如，电互连，诸如图2A中所示的导电线242，可提供从PCB290通过封装基板到焊料凸块226到高功率芯片201的功率的直接馈送，该焊料凸块226与穿过插入件的一个或多个TSV电通信。
图4A是根据本发明的另一个实施例的、示出插入件关于高功率和低功率芯片的示例性的位置关系的集成电路（IC）系统400的示意性俯视图。图4B是沿图4A的线B-B获得的截面视图。在该实施例中，IC系统400通常包括插入件404、安装在插入件404的第一表面410上的两个高功率芯片401a、401b、以及安装在插入件404的第二表面412上的多个低功率芯片（诸如八个低功率芯片402a-402h）。第一表面410和第二表面412彼此相对并且大体平行。类似地，高功率芯片401a、401b、低功率芯片402a-h、以及插入件404可以是如上文关于图2A所讨论的那些高功率和低功率芯片201、202和插入件204，并可使用适合的方式诸如TSV405和焊料凸块406、408来电地和/或机械地彼此连接。放置高功率芯片401a、401b和低功率芯片402a-h使得每个低功率芯片402a-h与高功率芯片401a或401b部分重叠。
类似于上文所讨论的布置和优点，低功率芯片402a-h按并排式配置放置，并且每个低功率芯片402a-h，例如低功率芯片402a、402b、402c和402d，偏离每个高功率芯片的中心，例如高功率芯片401a，并且当从俯视图、或以垂直于插入件404的第一表面410的观察轴“N”观察时与高功率芯片401a的边414重叠。在一些实施例中，低功率芯片402a-d和低功率芯片402e-h可配置为分别与高功率芯片401a和高功率芯片401b一起使用。如果需要，IC系统400可包括附加的低功率和高功率芯片。应理解的是图3A-3B和4A-4B中所示出的布置可取决于应用/芯片设计来变化，并可适用于如上文关于图2A所讨论的IC系统200，或如下文将讨论的IC系统600和700。
图5示出根据本发明的一个实施例的、用来形成诸如图2A的IC系统200的集成电路（IC）系统的示例性处理顺序500。图6A-6F示出在图5所示的处理顺序的不同阶段的插入件604的示意性截面视图。应注意的是，图5中所示出的步骤的数目和顺序不意图限制本发明本文所描述的范围，因为可添加、删除和/或重新定序一个或多个步骤而不偏离本发明的基本范围。
处理顺序500在步骤502开始，其中提供插入件基板604，如图6A所示。插入件604可以是大块含硅基板，其具有穿过该含硅基板的硅穿孔（TSV）605。在各种实施例中，可以约10μm到约20μm的直径来形成TSV605并可用诸如铜的导电材料来完全填充。TSV605一般作为贯穿插入件厚度的功率、接地、以及信号互连，并可使用本领域中任意已存在的硅处理技术来生产。插入件604可具有小于约1200μm的厚度，例如厚度约为800μm。插入件604具有形成在插入件604的表面606a上的诸如微凸块或C4凸块的凸块触头618的阵列，并且每个焊料凸块618连接到TSV605。TSV605的间距“P1”可以约大于50μm，尽管在实际设计中间距“P1”取决于应用可以更大或更小。
在步骤504，一个或多个低功率芯片602，诸如上文关于图2A所讨论的低功率芯片202，以倒装芯片的方式正面侧朝下地安装在插入件604的表面606a上，如图6A所示。术语“正面侧”表示低功率芯片602的用半导体处理所处置使得电路被制造在低功率芯片602的该正面侧上的一侧。低功率芯片202置于插入件604的表面606a上并且凸块触头618被加热和回流（reflow）来形成焊点。这些焊点与TSV605对齐并配置为提供低功率芯片602和插入件604之间的电的或机械的连接。在低功率芯片602安装在凸块触头618上之后，使用底部填充工艺，低功率芯片602、凸块触头618、以及插入件604的表面606a被包封在包封材料620中。包封材料620在结构上将低功率芯片602耦连到封装基板（例如封装基板214）并防止或限制在热循环期间低功率芯片602和封装基板的不同移动。包封材料的高硬度还使能包封材料适应将另外作用在焊点上的热应力。因此，包封材料620减少凸块触头620的开裂，并且延长低功率芯片602和封装基板之间的焊点的寿命。包封材料620可以是诸如液态环氧树脂、可变形凝胶、硅橡胶等可经固化以硬化的任意合适的材料。另外或可替代地，低功率芯片602和插入件604的表面606a的一部分可由包封材料以如图2B所示的类似的方式加以包封而不用使整个表面606a被包封。
在图6B所示的又一个可替代实施例中，插入件604的表面606a可装备有包括微凸块680的阵列和C4凸块682的阵列的凸块触头。C4凸块682可与在插入件604的表面606a上形成图案的匹配导电盘684对准，然后C4凸块682回流以形成焊点。可邻近或围绕低功率芯片602放置C4凸块682。类似地，在低功率芯片602安装在微凸块680上之后，使用底部填充工艺，微凸块680、C4凸块682、C4凸块之间的低功率芯片602、以及插入件604的表面606a被包封在诸如环氧树脂或聚合材料的包封材料686中。C4凸块682的上面部分687可穿过包封材料686暴露在外以促进将插入件604焊到后续减薄工艺中所使用的承载基板上。包封材料686在结构上将低功率芯片602耦连到封装基板（例如封装基板214）并防止或限制在热循环期间低功率芯片602和后续所接附的封装基板的不同移动。包封材料686还减少C4凸块682和/或微凸块680上的疲劳损伤，并且延长低功率芯片602和封装基板之间的焊点的寿命。
在步骤506，诸如图6A中所示的插入件604或图6B中所示的插入件604的插入件被翻转，并以“正面侧朝下”的方式由粘连剂625或如果使用图6B中所示的插入件604那么由粘连剂连同C4凸块682，接附到第一承载基板624。第一承载基板624在后续减薄工艺和减薄后的后置处理步骤期间提供机械的和结构的临时支持。第一承载基板624可包括例如玻璃、硅、硬聚合物等。粘连剂625可以是能够以合适的方式固定第一承载基板624来使能后续处理的本领域中已知的任意的临时粘连剂。粘连剂625应提供充足的机械强度、热稳定性、耐化学性、易于脱胶和清洁。在将插入件604接附到第一承载基板624之后，在插入件604的背面626即背对低功率芯片602的一侧上实施减薄工艺，来达到插入件604的所期望的厚度，同时TSV末端603暴露在外。可使用本领域中任意合适的技术诸如蚀刻工艺和/或平坦化工艺来实施减薄工艺。在一个实施例中，插入件604在减薄后可具有约50μm到约100μm的厚度“T”。图6C示出在插入件604的背面被凹进后接附到第一承载基板624的插入件604的结果状态（自图6B）。
在步骤508，在插入件604减薄之后，一个或多个高功率芯片601安装在插入件604的背面626，如图6D所示。高功率芯片601可包括用于特定应用的任意合适的电路。例如，高功率芯片601可以是上文关于图2A所讨论的任意那些高功率芯片201。在图6D中所示出的实施例中，示出一个高功率芯片601。高功率芯片601以倒装芯片的配置电耦连到插入件604，使得高功率芯片601上的接触盘（未示出）面对插入件604的背面626。高功率芯片601的接触盘经由在高功率芯片601上所形成的并与TSV605对齐的凸块触头688电连接到插入件604。凸块触头688可以是诸如C4凸块的任意合适的导电装置。
在步骤510，使用底部填充工艺，高功率芯片601、凸块触头688和经减薄的插入件604的背面626的部分被包封在包封材料690中，如图6D所示。包封材料690的高硬度使能包封材料适应将另外作用在凸块触头688上的热应力，并且因此减少凸块触头688的开裂并延长高功率芯片601和插入件604之间的焊点的寿命。包封材料690可以是诸如液态环氧树脂、可变形凝胶、硅橡胶等可经固化以硬化的任意合适的材料。另外或可替代地，高功率芯片601、凸块触头688、以及经减薄的插入件604的背面626的一部分可由包封材料以如图2B所示的类似的方式加以包封而不用使整个背面626被包封。
在步骤512，在高功率芯片601已安装到插入件604上并被包封后，使用本领域中已知的如上文所讨论的任意临时粘连剂，承载高功率芯片601和低功率芯片602的插入件604（即半制成设备693）由其正面694接附到第二承载基板692，如图6E所示。半制成设备693的正面是具有经包封的高功率芯片601的一侧。第二承载基板692可使用与第一承载基板624相同的材料来提供充足的机械强度和热稳定性，使能半制成设备693的后续处理，诸如半制成设备693到封装基板的抬升、转移和接附。
在步骤514，在第二承载基板692已接附到插入件604之后，通过将第一承载基板624和半制成设备693之间的临时粘连剂脱胶，第一承载基板624从半制成设备693的背面691分离。脱胶可包括本领域中已知的任意化学或热脱胶技术。图6E示出第一承载基板已移除的状态。
在步骤516，继第一承载基板624的脱胶之后，半制成设备693在第二承载基板692的支持下被抬升和转移，以由其背面691通过C4凸块682接附到封装基板614。C4凸块682重新加热或回流来将半制成设备693冶金地和电地结合到封装基板614。因此封装基板214通过电连接，诸如凸块触头688、TSV605、微凸块680、以及C4凸块682，与高功率芯片601和低功率芯片602电通信。封装基板614可以是如上文结合图2A所讨论的封装基板214。其后，第二承载基板692从半制成设备693的正面694分离，如图6F所示。
在步骤518，封装基板614通过封装引脚622接附到PCB690，如图6F所示。封装引脚622可以是本领域中已知的任意技术上可行的芯片封装电连接，诸如焊料凸块或BGA，来使能高功率和低功率芯片601、602和PCB690之间的电通信。因此，提供经封装的IC系统600。散热器（未示出），诸如图2A中所示出的散热器212，可置于经封装的IC系统之上并由其支持，来提高IC系统的传热。应理解的是，散热器可以是任意所期望的形状并由可传导和消散从IC系统所生成的热量的任意金属制成。
图7示出根据本发明的另一个实施例的、集成电路（IC）系统700的示意性截面视图。IC系统700在配置和运行上大体类似于IC系统200或IC系统600，除了IC系统700的封装基板714装备有腔或凹进的开口730用于容纳低功率芯片702。可通过本领域中已知的任意合适的工艺，诸如湿法刻蚀或干法刻蚀工艺，来在封装基板714的上表面中形成凹进的开口730。低功率芯片702的有效表面719，即具有多个电极片（electrodepad）（未示出）的表面，可与封装基板714的上表面713齐平或略高于封装基板714的上表面713。具有低功率芯片702嵌入其中的封装基板714减少封装基板714的整体高度，提供更薄的封装外形。低功率芯片702的有效表面719电连接到诸如焊料凸块的电连接718，其进而通过穿过插入件704的TSV705和诸如焊料凸块的电连接708电连接到高功率芯片701。封装基板714的凹进的开口730可用制型材料732填充来包封低功率芯片702。类似于图2A或图6F所示出的实施例，使用底部填充工艺，高功率芯片701可被包封在包封材料720中。而且，电连接718之间的缝隙734可被填充或包封在包封材料724中，来防止低功率芯片702由于高功率芯片701、插入件704、以及低功率芯片702之间的不同的热膨胀系数而出现的与插入件的任意相对移动。在各种实施例中，凹进的开口730可具有约20mm到约550mm的厚度“D1”以及约20mm到约850mm的长度“D2”，并且封装基板714可具有约20mm到约850mm的厚度“D3”。应理解的是，尺寸可取决于芯片的大小来变化。
总而言之，本发明的实施例提供优于现有技术装置的各种优点，诸如由于低功率芯片嵌入封装基板内而得到更薄的封装外形。由于高功率和低功率芯片的堆叠配置，如图所示，与其中高功率芯片和低功率芯片并排地放置在插入件的同一侧的已存在的IC封装相反，所以本发明使能插入件的整体占地面积减少。低功率芯片可按“偏心”配置来布置以允许从电源到高功率芯片的功率和/或接地信号的更快的直接馈送，而不经历与低功率芯片相关联的电阻损耗。高功率和低功率芯片之间的互连的更短的路由产生更快的信号传播以及IC系统中的噪声、串扰、以及其他寄生的减少。本发明还由于热量由接附到高功率芯片的散热器所传递和消散而最小化从高功率芯片到低功率芯片的热传递。此外，安置于高功率芯片和低功率芯片之间的插入件起热隔离层的作用，来允许低功率芯片位于接近高功率芯片而不受到由高功率芯片所生成的热量的不利影响。
虽然上述内容针对本发明的实施例，但可设计本发明的其他和进一步的实施例而不脱离其基本范围。不同实施例的范围由下面的权利要求加以确定。

Claims (9)

1.一种集成电路系统，包括：
插入件，其包括穿过所述插入件的多个导电过孔；
安装在所述插入件的第一表面上的一个或多个高功率芯片，其中所述一个或多个高功率芯片在正常运行期间生成至少10W的热量；
安装在所述插入件的第二表面上的一个或多个低功率芯片，其中所述一个或多个低功率芯片在正常运行期间生成小于5W的热量，所述一个或多个低功率芯片中的每个包括与所述一个或多个高功率芯片的边按行对齐的输入/输出端子，并且所述第一表面和所述第二表面彼此相对并且大体平行；以及
在所述一个或多个高功率芯片和所述一个或多个低功率芯片上形成的并配置为包封所述一个或多个高功率芯片和所述一个或多个低功率芯片的包封材料。
2.根据权利要求1所述的系统，其中所述一个或多个低功率芯片通过所述多个导电过孔电连接到所述一个或多个高功率芯片。
3.根据权利要求1所述的系统，其中所述一个或多个低功率芯片以并排式配置放置。
4.根据权利要求3所述的系统，其中所述一个或多个低功率芯片中的每个偏离所述一个或多个高功率芯片中的每个的中心。
5.根据权利要求4所述的系统，其中所述一个或多个低功率芯片中的每个与所述一个或多个高功率芯片的边重叠。
6.根据权利要求1所述的系统，进一步包括电地和机械地连接到所述一个或多个低功率芯片的封装基板，所述封装基板具有足以支持所有低功率芯片的连续长度。
7.根据权利要求6所述的系统，其中所述包封材料包封位于所述封装基板和所述插入件之间的所有低功率芯片。
8.根据权利要求1所述的系统，进一步包括电地和机械地连接到所述一个或多个低功率芯片的封装基板，其中所述封装基板具有在所述封装基板的上表面中形成的凹进的开口，用于容纳所述一个或多个低功率芯片的厚度。
9.根据权利要求8所述的系统，其中所述一个或多个低功率芯片在所述凹进的开口内被包封在包封材料中。
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