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CN114464581A - 封装结构及其制造方法 - Google Patents

封装结构及其制造方法 Download PDF

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Publication number
CN114464581A
CN114464581A CN202210123951.2A CN202210123951A CN114464581A CN 114464581 A CN114464581 A CN 114464581A CN 202210123951 A CN202210123951 A CN 202210123951A CN 114464581 A CN114464581 A CN 114464581A
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CN
China
Prior art keywords
chip
package structure
substrate
side heat
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202210123951.2A
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English (en)
Other versions
CN114464581B (zh
Inventor
朴龙浩
黎英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
Original Assignee
Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Publication date
Application filed by Samsung Semiconductor China R&D Co Ltd, Samsung Electronics Co Ltd filed Critical Samsung Semiconductor China R&D Co Ltd
Priority to CN202210123951.2A priority Critical patent/CN114464581B/zh
Publication of CN114464581A publication Critical patent/CN114464581A/zh
Priority to US17/959,580 priority patent/US20230253285A1/en
Priority to KR1020220130813A priority patent/KR20230120966A/ko
Application granted granted Critical
Publication of CN114464581B publication Critical patent/CN114464581B/zh
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Abstract

本发明提供了一种封装结构及其制造方法,所述封装结构包括:基板;芯片,以倒装芯片方式安装在基板上;以及侧散热件,包括导热材料并且设置在芯片的侧面上。侧散热件电连接到芯片的电路层。

Description

封装结构及其制造方法
技术领域
总体来说,本发明属于半导体封装领域;具体来说,本发明涉及一种侧面散热增强封装结构及其制造方法。
背景技术
芯片功耗产生的热量会使芯片升温从而影响芯片性能乃至对芯片造成不可逆的损坏。对功耗的研究始终贯穿芯片生产的各环节,芯片的能耗比也随着设计的完善和制程的进步而一直在改善。然而,对芯片性能的需求仍在不断提高,因此能耗比的改善并不能解决芯片功耗引起的散热问题。散热问题在高端芯片(例如CPU、GPU等)中表现得更为明显。随着制造工艺的发展,晶体管越来越多,芯片功耗随之也越来越高。
半导体封装不仅可以对芯片进行物理保护,而且可以帮助芯片散热。图1示出了根据现有技术的封装结构9。如图1所示,封装结构9包括基板910以及顺序地设置在基板910上的芯片920、导热层930和散热盖940。封装结构9还包括底填料950。芯片920通过焊球925以倒装芯片方式连接到基板910。导热层930与芯片920的上表面直接接触。散热盖940包括盖部941和壁部942。盖部941的中心部分与导热层930的上表面直接接触。壁部942从盖部941的外围部分向下延伸并通过粘合剂945粘合到基板910。底填料950设置在芯片920与基板910之间。封装结构9通过设置在基板910下面的焊球915向外连接。
功耗集中在芯片的电路层(或功能区)。就图1而言,功耗集中在芯片920的下部,故而芯片920的下部为发热源。封装结构9帮助发热源在垂直向上的方向上进行散热。在该散热过程中,热量从芯片920的下部依次经过芯片920的上部(硅)、导热层930和散热盖940最终进入外部环境(空气)。
然而,硅的导热系数非常低,仅为0.21W/m·K。而硅作为芯片的基体材料难以被替代,从而极大限制了散热效率。当然,在形成芯片之后可以对芯片进行减薄,从而减小硅基体的厚度并提高散热效率。然而,功耗大的芯片通常也会具有大的芯片尺寸。芯片减薄后重量会变轻,导致芯片的翘曲问题更严重,甚至会导致虚焊问题。
发明内容
本发明提供了侧面散热增强封装结构及其制造方法。
示例实施例提供了一种封装结构,所述封装结构可以包括:基板;芯片,可以以倒装芯片方式安装在基板上;以及侧散热件,可以包括导热材料并且设置在芯片的侧面上,其中,侧散热件可以电连接到芯片的电路层。
根据示例实施例,所述封装结构还可以包括:侧导热层,侧导热层可以包括热界面材料并且设置在芯片的侧面与侧散热件之间,侧导热层可以直接接触芯片和/或侧散热件。侧导热层的上表面、芯片的上表面和侧散热件的上表面可以基本上对齐。
根据示例实施例,所述封装结构还可以包括:上导热层,可以设置在芯片的上表面上且与芯片的上表面直接接触;散热盖,可以设置在上导热层的上表面上且与上导热层的上表面直接接触。上导热层可以包括热界面材料。散热盖可以包括导热材料。上导热层和/或散热盖可以具有基本上平板形状。
根据示例实施例,散热盖可以包括盖部和壁部,盖部可以具有基本上平板形状,盖部的中心部分可以与上导热层的上表面直接接触,壁部可以从盖部的外围部分向下延伸。
根据示例实施例,所述封装结构还可以包括:多个连接件,可以设置在芯片与基板之间,以将芯片的电路层与基板电连接;以及连接部,可以设置在芯片的面对基板的下表面上,以连接多个连接件中的至少一个与侧散热件。
根据示例实施例,每个连接件可以包括从芯片朝向基板依次设置的凸块下金属、凸块以及焊球。侧散热件可以包括与凸块相同的材料。连接部可以包括与凸块下金属相同的材料并且与凸块下金属在同一层。
根据示例实施例,侧散热件可以连接第一信号。第一信号可以是芯片信号或虚设信号。
根据示例实施例,第一信号可以是芯片信号中的电流最大的芯片信号、电流前三大的芯片信号中的至少一个、电流前五大的芯片信号中的至少一个或电流前十大的芯片信号中的至少一个。
根据示例实施例,所述封装结构还可以包括:填充件,可以包括底填料、非导电胶和/或非导电膜,并且可以填充芯片与基板之间的空间。
示例实施例提供了一种封装结构的制造方法,可以包括以下步骤:在芯片的侧面上形成包括导热材料的侧散热件;将芯片以倒装芯片方式安装在基板上,其中,侧散热件电连接到芯片的电路层。
根据本发明的包括侧散热件的封装结构可以改善散热效果。另外,根据本发明的包括侧散热件的封装结构可以增加芯片的强度和重量,从而控制或避免翘曲,降低回流过程中虚焊的风险。另外,根据本发明的包括侧散热件的封装结构可以实现电磁屏蔽。
附图说明
通过下面结合附图进行的描述,本发明的目的和特点将会变得更加清楚。
图1示出了根据现有技术的封装结构。
图2是示出根据本发明的实施例的封装结构的剖视图。
图3至图12是示出根据本发明的实施例的制造封装结构的方法的剖视图。
图13至图16分别是示出根据本发明的实施例的封装结构的剖视图。
具体实施方式
在下文中,将参照附图更充分地描述本发明。本领域技术人员将理解的是,在不脱离本发明的精神或范围的情况下,可以以各种不同的方式修改实施例。将省略无关的部分,以清楚地描述本发明。
图2是示出根据本发明的实施例的封装结构1的剖视图。
封装结构1可以包括基板110以及以倒装芯片方式设置在基板110上的芯片120。基板110可以包括陶瓷、玻璃、塑料和/或其它基板材料。例如,基板110可以包括双马来酰亚胺三嗪(BT)树脂。芯片120的向外电连接一侧为正面。在图2中,芯片120的正面对应于芯片120的下表面。芯片120的电路层可以设置在芯片120的正面附近,即,芯片120的电路层可以设置在芯片120的下部。芯片焊盘121可以设置在芯片120的下表面处。芯片120(或芯片焊盘121)可以通过连接件电连接到设置在基板110的上表面处和/或基板110内的连接焊盘(未示出)、布线(未示出)、通路(未示出)和/或电路(未示出)等并且/或者可以通过设置在基板110下面的焊球115向外电连接。
连接件可以包括沿着向下方向依次设置的凸块下金属(UBM)122、凸块123以及焊球124。UBM 122可以增强连接。UBM 122可以包括金属的单层结构或多层结构。例如,UBM122可以包括钛/铜的双层结构。凸块123可以作为连接件的主体。凸块123可以包括金属或合金。例如,凸块123可以包括诸如铜的金属。焊球124可以包括常见焊料。例如,焊球124可以包括金、银、铜、锡等和/或其合金。在实施例中,连接件可以采用可控塌陷芯片连接(Controlled Collapse Chip Connection;C4)和/或焊盘下电路(Circuit under Pad;CuP)。然而,连接件不限于此,只要芯片120可以经由连接件电连接到基板110和/或向外电连接即可。
封装结构1还可以包括设置在芯片120的侧面上的侧散热件126。侧散热件126可以与芯片120的侧面直接接触。侧散热件126的上表面可以与芯片120的上表面基本上对齐。侧散热件126可以包括导热材料。侧散热件126可以包括金属或合金。例如,侧散热件126可以包括诸如金、银、铜、铁、铝等的金属或者其合金。然而,侧散热件126的材料不限于此,只要侧散热件126能够帮助芯片120散热即可。侧散热件126可以与连接件的至少一部分包括相同的材料。例如,在连接件包括凸块123的情况下,侧散热件126可以与凸块123包括相同的材料。然而,本发明不限于此,侧散热件126可以包括与连接件的任何部分都不同的材料。
侧散热件126可以以封闭矩形环的形状设置在芯片120的周围。然而,本发明不限于此,侧散热件126可以以开口矩形环的形状设置;侧散热件126可以设置在芯片120的一个、两个或三个侧面上。
侧散热件126可以增加芯片120的强度和重量。因此,即使芯片120被减薄,芯片120的翘曲也可以被控制或避免,故而减少了芯片120在回流过程中虚焊的风险。如此,芯片120的厚度可以减薄,使得垂直方向的散热距离缩短。
另外,根据芯片120的减薄程度/翘曲程度,侧散热件126的形状、厚度等可以相应调整。例如,如果芯片120的减薄程度/翘曲程度增大,则侧散热件126的横向厚度可以增大并且/或者侧散热件126可以具有封闭矩形环的形状。如果芯片120的减薄程度/翘曲程度减小,则侧散热件126的横向厚度可以减小并且/或者侧散热件126可以具有封闭矩形环之外的形状。
连接部127可以连接侧散热件126与芯片120的电路层。例如,连接部127可以设置在芯片120的下表面上,并且连接侧散热件126与连接件。连接部127可以包括例如金属的导电材料。连接部127可以与连接件的至少一部分包括相同的材料。例如,在连接件包括UBM122的情况下,连接部127可以与UBM 122包括相同的材料并且与UBM 122在同一层。然而,本发明不限于此,连接部127可以包括与连接件的任何部分都不同的材料。连接部127可以用作连接布线。
发热源(即,芯片120的电路层)的热量可以在没有连接部127的情况下传递到侧散热件126;然而,此时的传热路径包括芯片的基体硅等非金属,传热效率低。在连接部127连接侧散热件126与芯片120的电路层的情况下,发热源的热量可以通过热传导(例如金属热传导)传递到芯片120的侧面,传热效率显著提高。因此,封装结构1的散热效果得到进一步改善。
侧散热件126可以直接接触基板110。然而,本发明不限于此。焊球124可以形成在侧散热件126与基板110之间。侧散热件126可以与基板110电绝缘。然而,本发明不限于此。侧散热件126可以直接电连接到或者通过焊球124或通过连接部127和相连的连接件电连接到设置在基板110的上表面处和/或基板110内的连接焊盘(未示出)、布线(未示出)、通路(未示出)和/或电路(未示出)等并且/或者可以通过设置在基板110下面的焊球115向外电连接。
侧散热件126可以连接或传输信号。侧散热件126可以通过基板110连接或传输信号。
侧散热件126可以连接或传输芯片信号,芯片信号是与芯片工作相关的信号。通常,信号电流越大,发热源相关部分产生的热量越大;因此,侧散热件126可以连接或传输电流较大(例如,最大)的芯片信号。例如,侧散热件126可以连接或传输芯片信号中的电流最大的芯片信号、电流前三大的芯片信号中的至少一个、电流前五大的芯片信号中的至少一个或电流前十大的芯片信号中的至少一个。
侧散热件126可以不连接或传输信号。侧散热件126可以连接或传输虚设信号(dummy信号)。在这种情况下,侧散热件126可以用作电磁屏蔽件。
封装结构1还可以包括设置在基板110与芯片120之间的填充件150。填充件150可以包括底填料(UnderFill;UF)、非导电胶(Non-Conductive Paste;NCP;)和/或非导电膜(Non-Conductive Film;NCF)。底填料可以包括环氧树脂。例如,填充件150可以填充芯片120与基板110之间未被占据的空间。
图3至图12是示出根据本发明的实施例的制造封装结构的方法的剖视图。
参照图3,首先,可以进行晶片重组。可以在重组基板200上设置芯片120。芯片120的设置有芯片焊盘121的正面可以向上,背对重组基板200。
参照图4,然后,可以在重组基板200上形成凸块下金属层(UBM层)122’。UBM层122’可以覆盖芯片120的上表面。UBM层122’还可以覆盖芯片120的侧面和重组基板200的暴露的上表面中的至少一者。可以通过例如溅射的各种沉积方法形成UBM层122’。UBM层122’可以包括金属的单层结构或多层结构。例如,UBM层122’可以包括Ti/Cu的双层结构。
参照图5和图6,然后,可以在UBM层122’上形成光致抗蚀剂210,并对光致抗蚀剂210进行图案化,即曝光和显影。图案化的光致抗蚀剂210可以形成有与芯片焊盘121叠置的第一孔。图案化的光致抗蚀剂210还可以形成有在横向方向上暴露芯片120的侧面或UBM层122’的形成在芯片120的侧面上的部分的第二孔。
参照图7,然后,可以在第一孔中形成凸块123并在第二孔中形成侧散热件126;然后,可以在第一孔和第二孔的剩余部分中形成焊料124’。可以通过各种已知方式(例如,镀覆方式)形成凸块123、侧散热件126和焊料124’。然而,本发明不限于此。可以不形成焊料124’。在不形成焊料124’的情况下,凸块123和侧散热件126可以部分或完全填充第一孔和第二孔。
参照图8,然后,可以去除(例如剥离)图案化的光致抗蚀剂210。
参照图9,然后,可以加热焊料124’进行回流,使得焊料124’形成为具有弯曲上表面的焊球124。另外,可以对UBM层122’进行图案化。例如,可以蚀刻UBM层122’。图案化的UBM层122’可以包括位于芯片120(例如,芯片焊盘121)与凸块123之间的UBM 122。图案化的UBM层122’还可以包括位于连接件(即,122、123和124)与侧散热件126之间的连接部127。在UBM层122’覆盖芯片120的侧面和/或重组基板200的暴露的上表面的情况下,图案化的UBM层122’还可以包括位于芯片120的侧面与侧散热件126之间的部分和/或位于侧散热件126与重组基板200之间的部分。
参照图10,然后,可以在芯片120上形成减薄支撑件220。例如,可以使用层压或者其它适合的工艺形成减薄支撑件220。减薄支撑件220填充连接件之间以及连接件与侧散热件126之间的空隙。
参照图11,然后,可以去除重组基板200。然后,可以对芯片120进行减薄。减薄支撑件220可以在去除重组基板200和减薄芯片120的过程中起支撑作用。例如,可以通过背面研磨的方式对芯片120进行减薄;在这种情况下,减薄支撑件220可以为背面研磨带。可以同时减薄芯片120和侧散热件126。减薄后,侧散热件126的减薄表面可以与芯片120的减薄表面基本上对齐。在图案化的UBM层122’包括位于芯片120的侧面上的部分的情况下,所述部分的减薄表面也可以与芯片120的减薄表面基本上对齐。在图案化的UBM层122’包括位于侧散热件126与重组基板200之间的部分的情况下,所述部分会在减薄后被去除。因为侧散热件126的存在可以增加芯片120的强度,所以与不设置侧散热件126的情况相比,芯片120可以被更大程度的减薄。
参照图12,然后,可以在芯片120和侧散热件126的减薄表面上形成切割带230。然后,可以去除减薄支撑件220。
参照图2,然后,可以执行切割工艺,从而形成单个芯片120。然后,可以将芯片120以倒装芯片方式安装在基板110上并去除切割带230,从而形成图2的封装结构1。需要注意的是,在图2中,侧散热件126与芯片120的侧面直接接触。也就是说,图2对应于图4的UBM层122’不覆盖芯片120的实施例。然而,本发明不限于此,封装结构可以包括图案化的UBM层122’的设置在芯片120的侧面与侧散热件126之间的部分。
然而,上述方法只是示例,本发明不限于此。上述图3至图12的方法的主旨在于在芯片的侧面上形成包括导热材料的侧散热件;可以对上述方法进行适当调整或用其它适当的方法在芯片的侧面上形成侧散热件。
图13是示出根据本发明的实施例的封装结构2的剖视图。
封装结构2与封装结构1的不同之处在于,封装结构2还可以包括顺序地设置在芯片120上的上导热层130和散热盖140。上导热层130可以包括热界面材料(TIM)。热界面材料可以包括导热硅脂、(相变型)导热胶、导热凝胶、金属热界面材料等。金属热界面材料可以包括铟。散热盖140可以包括导热材料,所述导热材料可以包括诸如金、银、铜、铁、铝等的金属或者其合金。上导热层130和散热盖140可以具有基本上平板形状。上导热层130和散热盖140的侧面可以与侧散热件126的侧面基本上对齐,然而本发明不限于此。上导热层130和散热盖140中的至少一个的侧面可以在侧散热件126的侧面的外侧或内侧。上导热层130和散热盖140中的至少一个的侧面可以与芯片120的侧面基本上对齐。上导热层130和散热盖140中的至少一个的侧面可以在芯片120的侧面的外侧或内侧。
在封装结构2中,发热源的热量可以从芯片120的下部依次经过芯片120的上部(例如硅)、上导热层130和散热盖140最终进入外部环境(空气)。另外,在上导热层130与侧散热件126直接接触的情况下(例如,在上导热层130的侧面在芯片120的侧面的外侧的情况下),从芯片120传递到侧散热件126的热量也可以再传递到上导热层130和散热盖140从而进入外部环境(空气)。
因此,对于封装结构1和2,封装结构1更轻薄,封装结构2的散热效果更好。
图14是示出根据本发明的实施例的封装结构3的剖视图。
封装结构3与封装结构1的不同之处在于,封装结构3还可以包括设置在芯片120的侧面与侧散热件126之间的侧导热层160。侧导热层160的上表面可以与芯片120的上表面和侧散热件126的上表面基本上对齐。
侧导热层160可以包括热界面材料。热界面材料可以包括导热硅脂、(相变型)导热胶、导热凝胶、金属热界面材料等。金属热界面材料可以包括铟。
侧导热层160可以有助于热量从芯片120的侧面传递到侧散热件126。
图15是示出根据本发明的实施例的封装结构4的剖视图。
封装结构4与封装结构3的不同之处在于,封装结构4还可以包括顺序地设置在芯片120上的上导热层130和散热盖140。封装结构4的上导热层130和散热盖140可以分别与封装结构2的上导热层130和散热盖140基本上相同。
图16是示出根据本发明的实施例的封装结构5的剖视图。
封装结构5与封装结构4的不同之处在于,封装结构5的散热盖140可以包括盖部141和壁部142。盖部141可以具有基本上平板形状。盖部141的中心部分与上导热层130的上表面直接接触。壁部142从盖部141的外围部分向下延伸。壁部142可以通过粘合剂(未示出)粘合到基板110。
对于本领域技术人员将清楚的是,在不脱离本发明的精神或范围的情况下,可以在本发明中做出各种修改和变化。因此,如果本发明的修改和变化落入权利要求及其等同物的范围内,那么本发明意图覆盖本发明的这些修改和变化。

Claims (10)

1.一种封装结构,所述封装结构包括:
基板;
芯片,以倒装芯片方式安装在基板上;以及
侧散热件,包括导热材料并且设置在芯片的侧面上,
其中,侧散热件电连接到芯片的电路层。
2.根据权利要求1所述的封装结构,所述封装结构还包括:
侧导热层,侧导热层包括热界面材料并且设置在芯片的侧面与侧散热件之间,侧导热层直接接触芯片和/或侧散热件,
其中,侧导热层的上表面、芯片的上表面和侧散热件的上表面基本上对齐。
3.根据权利要求1或2所述的封装结构,所述封装结构还包括:
上导热层,设置在芯片的上表面上且与芯片的上表面直接接触;以及
散热盖,设置在上导热层的上表面上且与上导热层的上表面直接接触,
其中,上导热层包括热界面材料,
其中,散热盖包括导热材料,
其中,上导热层和/或散热盖具有基本上平板形状。
4.根据权利要求3所述的封装结构,其中:
散热盖包括盖部和壁部,盖部具有基本上平板形状,盖部的中心部分与上导热层的上表面直接接触,壁部从盖部的外围部分向下延伸。
5.根据权利要求1所述的封装结构,所述封装结构还包括:
多个连接件,设置在芯片与基板之间,以将芯片的电路层与基板电连接;以及
连接部,设置在芯片的面对基板的下表面上,以连接多个连接件中的至少一个与侧散热件。
6.根据权利要求5所述的封装结构,
其中,每个连接件包括从芯片朝向基板依次设置的凸块下金属、凸块以及焊球,
其中,侧散热件包括与凸块相同的材料,
其中,连接部包括与凸块下金属相同的材料并且与凸块下金属在同一层。
7.根据权利要求1所述的封装结构,
其中,侧散热件连接第一信号,
其中,第一信号是芯片信号或虚设信号。
8.根据权利要求7所述的封装结构,
其中,第一信号是芯片信号中的电流最大的芯片信号、电流前三大的芯片信号中的至少一个、电流前五大的芯片信号中的至少一个或电流前十大的芯片信号中的至少一个。
9.根据权利要求1所述的封装结构,所述封装结构还包括:
填充件,包括底填料、非导电胶和/或非导电膜,并且填充芯片与基板之间的空间。
10.一种封装结构的制造方法,包括以下步骤:
在芯片的侧面上形成包括导热材料的侧散热件;以及
将芯片以倒装芯片方式安装在基板上,
其中,侧散热件电连接到芯片的电路层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116705771A (zh) * 2022-12-30 2023-09-05 成都电科星拓科技有限公司 一种塑封可靠性散热增强型电磁屏蔽结构及其封装方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117790424A (zh) * 2024-02-23 2024-03-29 甬矽半导体(宁波)有限公司 扇出型封装结构和扇出型封装结构的制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001007255A (ja) * 1999-06-08 2001-01-12 Taishu Denno Kofun Yugenkoshi 高効率放熱型チップ寸法パッケージ方法及び装置
CN106057747A (zh) * 2015-04-09 2016-10-26 三星电子株式会社 包括散热器的半导体封装件及其制造方法
CN210640228U (zh) * 2019-12-05 2020-05-29 星科金朋半导体(江阴)有限公司 一种芯片的散热结构
CN111574967A (zh) * 2020-05-06 2020-08-25 苏州通富超威半导体有限公司 散热材料、应用该散热材料的芯片封装组件及制备方法
CN112542427A (zh) * 2020-11-19 2021-03-23 苏州通富超威半导体有限公司 一种芯片封装结构
CN112670187A (zh) * 2019-10-16 2021-04-16 台湾积体电路制造股份有限公司 芯片封装结构及其形成方法
WO2021119930A1 (zh) * 2019-12-16 2021-06-24 华为技术有限公司 芯片封装及其制作方法
CN113454774A (zh) * 2019-03-29 2021-09-28 华为技术有限公司 封装芯片及封装芯片的制作方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001007255A (ja) * 1999-06-08 2001-01-12 Taishu Denno Kofun Yugenkoshi 高効率放熱型チップ寸法パッケージ方法及び装置
CN106057747A (zh) * 2015-04-09 2016-10-26 三星电子株式会社 包括散热器的半导体封装件及其制造方法
CN113454774A (zh) * 2019-03-29 2021-09-28 华为技术有限公司 封装芯片及封装芯片的制作方法
CN112670187A (zh) * 2019-10-16 2021-04-16 台湾积体电路制造股份有限公司 芯片封装结构及其形成方法
US20210118767A1 (en) * 2019-10-16 2021-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with heat conductive layer and method for forming the same
CN210640228U (zh) * 2019-12-05 2020-05-29 星科金朋半导体(江阴)有限公司 一种芯片的散热结构
WO2021119930A1 (zh) * 2019-12-16 2021-06-24 华为技术有限公司 芯片封装及其制作方法
CN111574967A (zh) * 2020-05-06 2020-08-25 苏州通富超威半导体有限公司 散热材料、应用该散热材料的芯片封装组件及制备方法
CN112542427A (zh) * 2020-11-19 2021-03-23 苏州通富超威半导体有限公司 一种芯片封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116705771A (zh) * 2022-12-30 2023-09-05 成都电科星拓科技有限公司 一种塑封可靠性散热增强型电磁屏蔽结构及其封装方法

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