[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN103311204A - 倒装芯片封装技术和配置 - Google Patents

倒装芯片封装技术和配置 Download PDF

Info

Publication number
CN103311204A
CN103311204A CN2013100716233A CN201310071623A CN103311204A CN 103311204 A CN103311204 A CN 103311204A CN 2013100716233 A CN2013100716233 A CN 2013100716233A CN 201310071623 A CN201310071623 A CN 201310071623A CN 103311204 A CN103311204 A CN 103311204A
Authority
CN
China
Prior art keywords
tube core
package substrate
weld
underfill
fluxing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2013100716233A
Other languages
English (en)
Inventor
弗兰克·J·尤斯基
罗伯特·C·哈特曼
保罗·D·班茨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qorvo US Inc
Original Assignee
Triquint Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Triquint Semiconductor Inc filed Critical Triquint Semiconductor Inc
Publication of CN103311204A publication Critical patent/CN103311204A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/1312—Antimony [Sb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/2912—Antimony [Sb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81395—Bonding interfaces outside the semiconductor or solid-state body having an external coating, e.g. protective bond-through coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明内容的实施例涉及倒装芯片封装技术和配置。一种装置可以包括：封装衬底，该封装衬底具有形成在该封装衬底上的多个焊垫，该多个焊垫被配置成承载形成在管芯上的相应的多个互连结构；以及布置在封装衬底上的助熔底部填充材料，该助熔底部填充材料包括助熔剂和环氧材料，该助熔剂被配置成利于在多个互连结构中的各个互连结构和多个焊垫中的各个焊垫之间形成焊接接合部，该环氧材料被配置成在形成焊接接合部期间硬化以机械地加固焊接接合部。还可以描述和/或要求其他实施例。

Description

倒装芯片封装技术和配置
技术领域
本公开内容的实施例大体涉及集成电路封装的领域，具体地涉及倒装芯片封装技术和配置。
背景技术
集成电路（IC）封装件可以包括使用能焊接的材料与封装衬底耦接的各种元件（如，管芯和/或无源元件）。例如，可以形成焊点以将元件电气地和/或机械地耦接至封装衬底。当暴露于与热过程（如，焊接回流（solder reflow）或模制工艺）相关联的升高温度时或者当经受设备或客户的处理时，焊点可能会有故障（如，开裂或断裂）。热故障可以部分地归因于与集成电路封装件的各种材料相关联的膨胀率/收缩率。例如，管芯和封装衬底的材料可能具有不同的热膨胀系数（TCE），从而在与热过程相关联的加热/冷却期间导致不同的膨胀率/收缩率。
此外，在传统的传递模制技术中，管芯可以完全密封在封装衬底上使得模制材料与封装衬底为直接物理接触。模制的形成可以产生空隙，该空隙使得焊料迁移从而引起电气故障或者该空隙捕集水分。当空隙中的水分的温度升高（例如，高于水分的沸点）时，水分可能爆破或以其他方式施加压力。这样的爆破和/或压力的施加可以通过例如引起管芯与封装衬底之间的互连或焊点的故障而引起管芯的短路和/或其他故障。
另外，当前形成IC封装件的技术可以包括一个或更多个清洁操作以清洁封装衬底的表面（例如，除去在焊点区域处或焊点区域附近的助熔剂残留物），以提供用于模制工艺的清洁表面，该模制工艺形成密封元件并与封装衬底耦接的模制品。一个或更多个清洁操作可以增加用于制作IC封装件的制造工艺的成本和/或时间。
发明内容
本发明的目的在于提供一种倒装芯片封装技术和配置。
根据本发明的一个方面，提供了一种装置，包括：封装衬底，封装衬底具有形成在封装衬底上的多个焊垫，多个焊垫被配置成承载形成在管芯上的相应的多个互连结构；以及布置在封装衬底上的助熔底部填充材料，助熔底部填充材料包括助熔剂和环氧材料，助熔剂被配置成利于在多个互连结构中的各个互连结构和多个焊垫中的各个焊垫之间形成焊接接合部（solder bond），环氧材料被配置成在形成焊接接合部期间硬化以机械地加固焊接接合部。
根据本发明的另一个方面，提供了一种方法，包括：提供具有形成在封装衬底上的多个焊垫的封装衬底，多个焊垫被配置成承载形成在管芯上的相应的多个互连结构；以及在封装衬底上沉积助熔底部填充材料，助熔底部填充材料包括助熔剂和环氧材料，助熔剂被配置成利于使用能焊接的材料在多个互连结构中的各个互连结构和多个焊垫中的各个焊垫之间形成焊接接合部，环氧材料被配置成在形成焊接接合部期间硬化以机械地加固焊接接合部。
附图说明
通过以下结合附图的详细描述将容易理解实施例。为了便于此描述，相同的附图标记表示相同的结构元件。在附图的图中通过示例的方式而非通过的限制的方式来示出实施例。
图1示意性地示出根据各种实施例的包括助熔底部填充材料（fluxingunderfill material）和片状模制结构的示例性集成电路（IC）封装件配置的横截面侧视图。
图2示意性地示出根据各种实施例的包括助熔底部填充材料和片状模制结构的另一示例性IC封装件配置的横截面侧视图。
图3示意性地示出根据各种实施例的包括助熔底部填充材料和带结构的另一示例性IC封装件配置的横截面侧视图。
图4示意性地示出根据各种实施例的包括助熔底部填充材料和片状模制结构的另一示例性IC封装件配置的横截面侧视图。
图5是根据各种实施例的用于制造如本文中所描述的IC封装件的方法的流程图。
图6示意性地示出根据各种实施例的包括IC封装件的示例性系统。
具体实施方式
本公开内容的实施例描述倒装芯片封装技术和配置。在以下的详细描述中，参照构成本文的一部分的附图，其中相同的附图标记自始至终表示相同的部分，并且通过说明可以实践本公开内容的主题的实施例而示出附图。要理解，在不背离本公开内容的范围的情况下，可以使用其他实施例并且可以做出结构或逻辑变化。因此，不应当以限制意义理解以下的详细描述，并且由所附权利要求和它们的等价物限定实施例的范围。
为了本公开内容的目的，短语“A和/或B”意味着（A）、（B）或（A和B）。为了本公开内容的目的，短语“A、B、和/或C”意味着（A）、（B）、（C）、（A和B）、（A和C）、（B和C）、或（A、B和C）。
描述可以使用短语“在一种实施例中”或“在实施例中”，其各自可以指相同或不同实施例中的一个或更多个实施例。此外，关于本公开内容的实施例所使用的术语“包括”、“包含”、“具有”等是同义词。术语“耦接”可以指直接连接、间接连接或间接连通。
以最助于理解所要求的主题事物的方式，将各种操作依次描述为多个离散操作。然而，描述的顺序不应当被理解为其暗示着这些操作必需依赖于顺序。具体地，可以不以表示的顺序执行这些操作。可以以与所描述的实施例不同的顺序执行所描述的操作。在另外的实施例中，可以执行各种另外的操作和/或可以略去所描述的操作。
描述可以使用基于视角的描述，如上方/下方、后方/前方、或顶部/底部。这样的描述仅用于使讨论便利，而并非意在将本文中描述的实施例的应用限制为任何特定方向。
图1示意性地示出根据各种实施例的包括助熔底部填充材料（fluxingunderfill material）112和片状模制结构118的示例性集成电路（IC）封装件100配置的横截面侧视图。IC封装件100包括封装衬底如印刷电路板（PCB）102，并包括安装在PCB102的表面上的一个或更多个元件。
该一个或更多个元件可以包括例如以倒装芯片配置与PCB102耦接的一个或更多个管芯（在下文中为管芯104），如可以看见的那样。以倒装芯片配置，管芯104的有源表面（例如，在其上形成有电子器件的表面）使用形成在该有源表面上的互连结构108而与PCB102耦接。
根据各种实施例，管芯104可以包括有源和/或无源元件。管芯104可以表示表面声波（SAW）器件、体声波（BAW）器件、砷化镓（GaAs）器件、氮化镓（GaN）器件、和/或用于无线通信的射频（RF）管芯，然而，在这一点上主题事物不受限制。管芯可以包括开关倒装芯片，如单刀四掷（SP4T）开关。在其他实施例中，管芯104可以表示包括例如处理器管芯和/或存储器管芯的任何适当的半导体管芯。
安装在PCB102上的一个或更多个元件还可以包括一个或更多个无源元件（在下文中为无源元件114）。无源元件114可以包括例如电容器、电感器、电阻器、变压器或滤波器。在其他实施例中，无源元件114可以包括其他类型的器件。
根据各种实施例，利用使用能焊接的材料形成的一个或更多个焊接接合部（bond）（例如，焊接接合部116或焊接接合部110），管芯104和/或无源元件114可以与PCB102电气地和/或机械地耦接。例如，在一些实施例中，无源元件114可以使用由焊膏（solder paste）形成的焊接接合部116与PCB102耦接。焊膏可以包括助熔剂和能焊接的材料的混合物。用于焊接接合部110和116的能焊接的材料可以包括例如锡、银、金、铜、铅、锑或它们的合金。在其他实施例中，焊接接合部110和116可以使用其他能焊接的材料形成。
在一些实施例中，PCB102可以包括形成在PCB102上的多个焊垫（在下文中为焊垫106）。如可以看见的那样，焊垫106可以被配置成承载形成在管芯104上的相应的多个互连结构（在下文中为互连结构108）。管芯104的互连结构108可以使用焊接接合部110与PCB102的焊垫106电气地和/或机械地耦接。焊垫106和互连结构108可以包括导电材料，例如金属（如铜）。在所描述的实施例中，焊垫106被布置在PCB102的面向管芯104的表面上。
在一些实施例中，互连结构108可以包括柱结构，如所描绘的，该柱结构延伸以在PCB102和管芯104之间提供间隙距离G2的大部分。在一些实施例中，互连结构108可以包括焊垫、凸块、接线柱或其他结构，以利于将管芯104电气和/或机械耦接至PCB102。在一些实施例中，互连结构108可以延伸以提供比间隙距离G2的大部分小的间隙距离。在一些实施例中，焊接接合部110可以包括焊料凸块。焊接接合部110可以将互连结构108附接至焊垫106。
助熔底部填充材料112可以在PCB102上布置在管芯104和PCB102之间，如可以看见的那样。助熔底部填充材料112可以至少包括助熔剂和环氧材料。助熔剂可以通过例如从能焊接的表面除去氧化物而利于形成焊接接合部110。助熔剂可以包括例如清洁焊垫106的表面和/或互连结构108的表面的有机酸族，在一些实施例中助熔剂可以包括布置在互连结构108的表面或末端上的能焊接的材料（例如，锡）。在形成焊接接合部110和/或焊接接合部116的焊接回流工艺期间，助熔剂可以清洁互连结构108的表面。在一些实施例中，助熔剂可以包括例如松香、枞酸（abiatic acid）、氯化铵等。在其他实施例中，助熔剂可以包括其他材料。
助熔底部填充材料112可以包括环氧材料，该环氧材料被配置成在形成焊接接合部110的焊接回流工艺期间硬化，以在随后的热循环或处理期间机械地加固焊接接合部110并且防止焊接接合部110的故障（如，开裂、断裂或分离）。在一些实施例中，环氧材料可以包括被配置成允许或利于在与焊接回流工艺相关联的温度（例如，达到260℃或更大）下固化或硬化环氧材料的环氧树脂和/或硬化剂。例如，环氧树脂可以是在与焊接回流工艺相关联的温度下硬化至C阶环氧材料的B阶环氧（例如，预浸料）材料。硬化剂可以在焊接回流温度下催化环氧树脂的硬化作用。
助熔底部填充材料112可以覆盖PCB102的面向管芯104的、在管芯104和PCB102之间的表面，如可以看见的那样。助熔底部填充材料112还可以密封焊接接合部110，从而减缓可能在随后的热处理下（例如，在形成片状模制结构118期间）引起焊接接合部110故障的应力或其他机械力。机械应力或其他力可以归因于管芯104材料和PCB102材料的不匹配的热膨胀系数（CTE），管芯104材料和PCB102材料的不匹配的热膨胀系数在加热/冷却过程期间导致材料的不同膨胀率/收缩率。助熔底部填充材料112可以吸收应力，使得减小或消除传递至焊接接合部110的应力。在一些实施例中，助熔底部填充材料112可以填充在管芯104和PCB102之间的区域（例如，使得助熔底部填充材料112直接接触管芯104），如可以看见的那样。在一些实施例中，助熔底部填充材料112可以包括另外的材料或剂。
片状模制结构118可以形成在PCB102上或上方，如可以看见的那样，以保护安装在PCB102上元件免受处理或其他环境危害。片状模制结构118还可以提供用于IC封装件100的激光标刻（例如，激光标刻150）的表面。片状模制结构118可以包括环氧材料（例如，B阶材料），在环氧材料被施加热量时环氧材料软化。在一些实施例中，在高达175℃的温度下执行片状模制结构118的形成。在其他实施例中，可以在其他温度下执行片状模制结构118的形成。
在一些实施例中，通过在安装在PCB102上的元件（例如，管芯104、无源元件114）上放置片状模制结构118的表面并且向片状模制结构118的相反表面施加热量以引起片状模制结构118的材料软化，形成片状模制结构118。可以向片状模制结构118和/或PCB102施加力以使得软化的片状模制结构118部分地密封管芯104和/或无源元件114。例如，片状模制结构118可以密封管芯104的被布置为与管芯104的有源表面相反的无源表面，并且还可以密封管芯104的基本上与管芯104的有源/无源表面垂直的表面（例如，侧表面105）的至少一部分，如可以看见的那样。
在一些实施例中，片状模制结构118具有厚度T1。根据各种实施例，厚度T1可以具有在275微米至375微米的范围内的值。片状模制结构118可以形成为至少提供在最高元件的表面（例如，图1中管芯104的无源表面）与片状模制结构118的外表面S1之间的距离D1。距离D1可以是允许外表面S1的激光标刻（例如，激光标刻150）而不破坏片状模制结构118的距离。在一些实施例中，距离D1具有从25微米至100微米的值。
片状模制结构118的外表面S1可以与PCB102隔开距离D2。在一些实施例中，距离D2可以小于或等于500微米。片状模制结构118的内表面可以与PCB102隔开间隙距离G1。在一些实施例中，间隙距离G1具有从50微米至175微米的值。管芯104的有源表面可以与PCB102隔开间隙距离G2。在一些实施例中，间隙距离G2具有从55微米至65微米的值。在其他实施例中，可以使用D1、D2、G1、G2和T1的其他值。
如图1中可以看见的，在一些实施例中，空气间隙可以隔开片状模制结构118和助熔底部填充材料112。在其他实施例中，片状模制结构118和助熔底部填充材料112可以直接物理接触（例如，间隙距离G1小于或等于间隙距离G2）。
在一些实施例中，间隙距离G1表示在片状模制结构118的内表面与PCB102之间的最小间隙距离。间隙距离G1可以具有大于0的值以在片状模制结构118和PCB102之间提供空气间隙。在片状模制结构118和PCB102之间的空气间隙可以向陷于在助熔底部填充材料112中可能存在的空隙中的任何水分提供疏散路径。例如，当空隙中的水分达到升高温度（例如，水分的沸点）时，水分可以爆破而离开空隙或以其他方式对周围结构（例如，管芯104、互连结构108、焊接接合部110、焊垫106、PCB102）施加压力从而导致焊接接合部110的故障。在片状模制结构118和PCB102之间的空气间隙可以通过向水分提供疏散路径而减轻这些有害影响。
根据各种实施例，激光标刻150可以被形成在片状模制结构118的外表面S1中。在一些实施例中，激光标刻150可以具有进入片状模制结构118约25微米的深度。激光标刻150可以提供IC封装件100的标识。例如，激光标刻150可以标识：在IC封装件100中包含的产品；表明产品在何时和/或何地被制造的信息；以及/或者方位指示符（例如，引脚1定位符），该方位指示符用以指示IC封装件100相对于配置成读取方位指示符的机器的方位。
根据各种实施例，外表面S1可以是平滑的以利于方便使用取放设备来自动组装。例如，取放设备可以包括配备有真空的吸嘴，以粘附至IC封装件100的平滑表面并且将IC封装件100放置到另一产品（例如，电子组件或载体）中。
结合使用助熔底部填充材料112和片状模制结构118可以消除如下需求：使用传统传递或粘附至封装衬底并且完全密封管芯（例如，包括管芯与封装衬底之间的底部填充区域）压缩模制化合物来密封管芯（例如，管芯104）。助熔底部填充材料112可以增加焊接接合部110的焊接点可靠性，并且提供相对于传递或压缩模制技术的较低成本的解决方案。
本公开内容的实施例还可以允许在制作IC封装件100中使用较大的面板尺寸，提供IC封装件100的水分敏感级别（MSL）1性能，以及允许在PCB102上元件（例如，无源元件114、管芯104、焊垫106等）至另一元件的较近间隔从而允许缩小IC封装件100的尺寸。通过提供助熔底部填充材料112可以使元件的间隔靠得更近，其中助熔底部填充材料112消除了密封并底部填充管芯或者底部填充在无源元件114下方的区域的传递模制工艺。执行模制过程的常规工艺（例如，传递模制或压缩模制）可能需要比本公开内容的实施例更大的间隔。
图2示意性地示出根据各种实施例的包括助熔底部填充材料112和片状模制结构118的另一示例性IC封装件200配置的横截面侧视图。除了在图2中空气间隙可以隔开助熔底部填充材料112和管芯104之外，IC封装件200可以与关于图1的IC封装件100所描述的实施例一致。
在管芯104和助熔底部填充材料112之间的空气间隙可以为被陷于在助熔底部填充材料112中形成的空隙中的水分提供另外的疏散路径。在管芯104和助熔底部填充材料112之间的空气间隙还可以减轻与疏散的水分相关联的有害影响（例如，焊接接合部110的破损）。在一些实施例中，助熔底部填充材料112被布置成覆盖互连结构108的一部分、焊垫106以及焊接接合部110，以机械地加固焊接接合部110。
图3示意性地示出根据各种实施例的包括助熔底部填充材料112和带结构318的另一示例性IC封装件300配置的横截面侧视图。除了可以使用带结构318替代片状模制结构118之外，IC封装件300可以与关于图1的IC封装件100所描述的实施例一致。
根据各种实施例，带结构318可以包括耦接在一起的至少两个层。带结构318的第一层320可以包括在被施加热量时软化的材料，如B阶环氧材料。带结构318的第二层322可以包括完全固化或硬化的材料，如C阶环氧材料。在一些实施例中，第二层322可以被称为粘合层，原因是其被配置成粘附至在PCB102上安装的元件（例如，图3中的管芯104）。
通过在安装在PCB102上的元件（例如，管芯104和无源元件114）上放置带结构318，可以形成带结构318。可以向带结构318的表面（例如，第二层322的外表面）施加热量以软化第一层320，并且力可以用于使带结构318和PCB102在一起以使得第一层320的软化的材料密封管芯104的至少无源表面。在一些实施例中，第一层320还可以密封管芯104的基本上与管芯104的有源/无源表面垂直的表面的至少一部分，如可以看见的那样。在一些实施例中，在高达175℃的温度下执行带结构318的形成。在其他实施例中，可以在其他温度下执行带结构18的形成。
在一些实施例中，带结构318可以具有在125微米至200微米的范围内的厚度T2。例如，第一层320可以具有在75微米至100微米的范围内的厚度T3，并且第二层322可以具有在50微米至100微米的范围内的厚度T4。在其他实施例中，T2、T3、T4的厚度可以使用其他值。
带结构318可以与关于片状模制结构118所描述的实施例一致。例如，在一些实施例中，空气间隙可以隔开带结构318和助熔底部填充材料112，并且在其他实施例中，带结构318可以物理接触助熔底部填充材料112。在一些实施例中，间隙距离G1表示在带结构318的内表面与PCB102之间的最小间隙距离，并且具有大于0的值以在带结构318和PCB102之间提供空气间隙。在带结构318和PCB102之间的空气间隙可以向陷于在助熔底部填充材料112中可能存在的空隙中的任何水分提供疏散路径。
根据各种实施例，激光标刻150可以形成在带结构318的表面中，如可以看见的那样。在一些实施例中，激光标刻150可以具有约25微米的深度。根据各种实施例，带结构的外表面（例如，第二层322的表面）可以是平滑的以利于方便使用取放设备来自动组装。例如，取放设备可以包括配备有真空的吸嘴以粘附至IC封装件300的平滑表面并且将IC封装件300放置到另一产品（例如，电子组件或载体）中。助熔底部填充材料112可以与关于图1和图2中的助熔底部填充材料112所描述的实施例一致。
图4示意性地示出根据各种实施例的包括助熔底部填充材料112和片状模制结构118的另一示例性IC封装件400配置的横截面侧视图。在一些实施例中，管芯104、互连结构108、焊接接合部110、焊垫106、助熔底部填充材料112、片状模制结构118以及激光标刻150可以与关于图1所描述的实施例一致。
IC封装件400可以包括封装衬底，如挠曲带（flex tape）402。挠曲带402可以包括例如单侧挠曲带。在一些实施例中，挠曲带402可以包括聚酰亚胺，而在其他实施例中挠曲带402可以包括其他的适当材料。
焊垫106被形成在挠曲带402的第一表面A1上，如可以看见的那样。在挠曲带402的第一表面A1和第二表面A2之间穿过挠曲带402形成一个或更多个开口430。挠曲带402的第二表面A2可以面向以倒装芯片配置安装在挠曲带402上的管芯104，其中挠曲带402使用互连结构108和焊接接合部110将管芯104耦接至焊垫106。互连结构108和焊接接合部110可以通过形成在挠曲带402中的一个或更多个开口430而耦接至焊垫106的背面侧，如可以看见的那样。以此方式将管芯104耦接至挠曲带402，管芯104可以准确地定位至挠曲带402并且防止管芯104相对于挠曲带402的移动，从而与仅将管芯放置在挠曲带上并且将管芯模制至挠曲带的技术相比较，导致制作IC封装件400的较高产量（例如，形成激光标刻150或者单切/锯切IC封装件400的较少错误）。
片状模制结构118（例如，或者在一些实施例中，如关于图3所描述的带结构318）可以形成在管芯104上。在一些实施例中，具有间隙距离G3的空气间隙可以隔开片状模制结构118和挠曲带402。在片状模制结构118和挠曲带402之间的空气间隙可以向陷于在助熔底部填充材料112中可能存在的空隙中的任何水分提供疏散路径。在一些实施例中，间隙距离G3可以为0。也就是说，片状模制结构118可以直接物理接触挠曲带402以密闭地密封IC封装件400中的管芯104。挠曲带402和/或底部填充材料112可以吸收在与形成片状模制结构118相关联的热过程期间的IC封装件400的材料的机械应力，或者吸收与处理相关联的机械应力。
可以在焊垫106上形成如可以看见的一个或更多个封装互连结构（例如，焊料球420），以进一步允许IC封装件400与其他电子组件如主板组件的电气耦接。在一些实施例中，IC封装件400可以被配置成以球栅阵列（BGA）或接点栅格阵列（LGA）配置与其他电子组件耦接。在一些实施例中，IC封装件400可以是用于单管芯的封装件。在这样的实施例中，管芯104可以是GaAs管芯。在其他实施例中，IC封装件400可以是用于多个管芯和/或无源元件（例如，图1的无源元件114）的封装件。在其他实施例中，管芯104可以包括其他类型的管芯。根据各种实施例，IC封装件100、200、300或400可以是准备运向客户的最终产品。
图5是根据各种实施例的用于制造如本文中所述的IC封装件（例如，IC封装件100、200、300或400）的方法500的流程图。方法500可以与关于图1至图4所描述的实施例一致。
在502处，方法500包括设置在其上形成有多个焊垫（例如，图1至图4的焊垫106）的封装衬底（例如，图1至图3的PCB102或图4的挠曲带402）。多个焊垫可以被配置成承载在一个或更多个管芯（例如，图1至图4的管芯104）上形成的相应的多个互连结构（例如，图1至图4的互连结构108），其中一个或更多个管芯以倒装芯片配置耦接至封装衬底。在一些实施例中，封装衬底可以包括多个焊料焊垫（solder-on-pad，SOP）。SOP可以具有布置在焊垫的表面上能焊接的材料，以与一个或更多个管芯的互连结构或者无源元件形成焊接接合部（例如，图1至图4的焊接接合部110或116）。在其他实施例中，能焊接的材料可以被沉积或布置在一个或更多个管芯的互联结构上。
在504处，方法500包括在封装衬底上沉积助熔底部填充材料（例如，图1至图4的助熔底部填充材料112）。可以例如通过模板印刷工艺沉积助熔底部填充材料。被配置成支持封装衬底的设备可以精确地定位与金属模板邻近的封装衬底，该封装衬底可以改变厚度（例如，从70微米至150微米）。可以将助熔底部填充材料置于模板的顶部上，并且金属刮刀可以推动助熔底部填充材料横跨模板的顶部以填充形成在模板中的开口（例如，可以通过激光或化学处理来形成开口）。在刮刀经过开口并且静止下来之后，可以从模板设备移除封装衬底，其中助熔底部填充材料位于封装衬底的要耦接一个或更多个管芯的区域上。在其他实施例中，可以使用其他适当技术来沉积助熔底部填充材料。
在无源元件（例如，图1至图3的无源元件114）耦接至封装衬底的实施例中，方法500还包括：在506处，在封装衬底上沉积焊膏。可以通过如本文中所描述的模板印刷工艺来沉积焊膏。焊膏可以沉积在封装衬底的要耦接无源元件的区域上。在其他实施例中，可以使用其他适当技术来沉积焊膏。在其他实施例中，封装衬底可以包括被配置成承载无源元件的SOP。
在508处，方法500还可以包括在沉积有助熔底部填充材料的区域中将一个或更多个管芯附接至封装衬底，和/或在焊膏的区域中将无源元件附接至封装衬底。可以例如相对于封装衬底来定位或放置管芯，使得能焊接的材料接触焊垫和管芯的互连结构，或者能焊接的材料在焊垫或管芯的互连结构的能焊接的距离内。能焊接的材料可以如本文中所描述的那样放置在互连结构或焊垫（例如，SOP）上。可以相对于封装衬底来定位无源元件，或将无源元件放置在焊膏的能焊接的距离内。
可以执行焊接回流工艺以软化和硬化能焊接的材料，以在一个或更多个管芯与封装衬底之间和/或在无源元件与封装衬底之间形成焊接接合部。在一些实施例中，焊接回流工艺可以是同时在一个或更多个管芯与封装衬底之间以及在无源元件与封装衬底之间形成焊接接合部的单次焊接回流工艺（single solder reflow process）。单次焊接回流工艺还可以同时固化或硬化助熔底部填充材料的环氧材料。助熔底部填充材料的助熔剂可以在单次焊接回流工艺期间清洁能焊接的表面（例如，从互连结构和/或焊垫除去氧化物）。在一些实施例中，焊接回流工艺可以包括施加热量以提供高达260℃的焊接回流温度。在其他实施例中，焊接回流工艺可以包括高于或低于260℃的温度。
在510处，方法500还可以包括在管芯和/或无源元件上形成片状模制结构（例如，图1、图2和图4的片状模制结构118）或带结构（例如，图3的带结构318）。通过将片状模制结构或带结构置于安装在封装衬底上的一个或更多个管芯和/或无源元件上，并且施加热量以软化片状模制结构或带结构的材料，可以形成片状模制结构或带结构。在一些实施例中，形成片状模制结构或带结构的工艺可以包括施加热量以提供高达175℃的温度。在其他实施例中，可以使用其他温度来形成片状模制结构或带结构。可以向片状模制结构或带结构和/或封装衬底施加力，以使得软化的材料如本文中所描述的那样密封一个或更多个管芯和/或无源元件的一部分。可以在片状模制结构或带结构与封装衬底之间设置空气间隙，使得片状模制结构或带结构与封装衬底彼此没有物理接触，以向可能陷在助熔底部填充材料的空隙中的水分提供疏散路径。
根据各种实施例，可以使用一种或更多种清洁操作（例如，清洁操作、干燥操作和/或等离子清洁操作）从封装衬底的表面除去助熔残留物，以利于或允许片状模制结构或带结构粘附至封装衬底的（例如，当图1至图3的间隙距离G1或图4的间隙距离G3为0时）。在片状模制结构或带结构与封装衬底之间设置有空气间隙的其他实施例中（例如，当图1至图3的间隙距离G1或图4的间隙距离G3大于0时），可以不需要清洁操作来清洁封装衬底的表面。在一些实施例中，继执行焊接回流工艺程之后且在形成片状模制化合物或带结构之前，不对封装衬底执行清洁操作。
在512处，方法500还可以包括对片状模制结构或带结构进行激光标刻。片状模制结构或带结构的表面可以被激光标刻以表明关于IC封装件的元件的信息。
在514处，方法500还可以包括对封装衬底进行单切。在一些实施例中，IC封装件可以形成在如下封装衬底上：该封装衬底以封装衬底的矩阵阵列形式与其他封装衬底物理耦接。也就是说，使用本文中所描述的原理可以在矩阵阵列的封装衬底上同时形成多个IC封装件。使用包括例如锯切或激光切割的任何适当的技术，可以从矩阵阵列的其他封装衬底上单切封装衬底。单切的封装衬底随后可以被运至客户或置于另一电子组件（例如，图6的系统600）中。
本文中所描述的IC封装件（例如，图1至图4的IC封装件100、200、300或400）的实施例可以结合到各种其他系统中。在一些实施例中，IC封装件可以包括例如倒装芯片模块、表面声波（SAW）模块、或滤波器组模块或者其组合。
图6中示出示例性系统600的框图。如所描述的，系统600包括功率放大器（PA）模块602，在一些实施例中，功率放大器模块602可以为射频（RF）PA模块。系统600可以包括与功率放大器模块602耦接的收发器604，如图所示。功率放大器模块602可以包括本文中所描述的IC封装件。
功率放大器模块602可以从收发器604接收RF输入信号RFin。功率放大器模块602可以放大RF输入信号RFin，以提供RF输出信号RFout。RF输入信号RFin和RF输出信号RFout两者均可以作为传输链的一部分，在图6中分别由Tx-RFin和Tx-RFout表示。
放大的RF输出信号RFout可以被提供至天线开关模块（ASM）606，ASM606经由天线结构608来完成RF输出信号RFout的无线（OTA）发送。ASM606还可以经由天线结构608接收RF信号，并且沿着传输链将所接收的RF信号Rx耦合至收发器604。
在各种实施例中，天线结构608可以包括一个或更多个定向和/或全向天线，包括例如偶极天线、单极天线、贴片天线、环形天线、微带天线或适于RF信号的OTA发送/接收的任何其他类型天线。
系统600可以是包括功率放大的任何系统。IC封装件可以包含向包括有电力调节应用（例如，交流（AC）-直流（DC）变流器、DC-DC变流器、DC-AC变流器等）的电源开关应用提供高效的开关器件的元件（例如，图1至图4中的管芯104）。在各种实施例中，对于在高的射频功率和频率下的功率放大而言系统600可以特别有用。例如，系统600可以适于陆地和卫星通信、雷达系统中的任何一个或更多个，并且可能适于各种工业和医学应用。更具体地，在各种实施例中，系统600可以是从雷达设备、卫星通信设备、移动手持终端、移动电话基站、广播无线电波或电视放大系统中选择的一个。
虽然为了说明的目的已经在本文中示出和描述了特定的实施例，但是许多替代的和/或等效的实施例或者被推断为实现相同目的的实施可以代替所示出和描述的实施例而不背离本公开内容的范围。此应用意在覆盖本文中所讨论的实施例的任何修正或变化。因此，其显然意指仅通过权利要求和其等价物来限定本文中所描述的实施例。

Claims (25)

1.一种装置，包括：
封装衬底，所述封装衬底具有形成在所述封装衬底上的多个焊垫，所述多个焊垫被配置成承载形成在管芯上的相应的多个互连结构；以及
布置在所述封装衬底上的助熔底部填充材料，所述助熔底部填充材料包括助熔剂和环氧材料，所述助熔剂被配置成利于在所述多个互连结构中的各个互连结构和所述多个焊垫中的各个焊垫之间形成焊接接合部，所述环氧材料被配置成在形成所述焊接接合部期间硬化以机械地加固所述焊接接合部。
2.根据权利要求1所述的装置，其中，所述助熔剂被配置成通过从所述各个互连结构和所述各个焊垫的能焊接的表面除去氧化物而利于所述焊接接合部的形成。
3.根据权利要求1所述的装置，还包括：
所述管芯，所述管芯利用所述焊接接合部、以倒装芯片配置的方式配置在所述封装衬底上，所述焊接接合部将所述多个互连结构中的所述各个互连结构附接至所述多个焊垫中的所述各个焊垫，其中，所述助熔底部填充材料被布置在所述管芯和所述封装衬底之间。
4.根据权利要求3所述的装置，其中，所述助熔底部填充材料覆盖所述封装衬底的面向所述管芯的表面的一部分。
5.根据权利要求4所述的装置，其中，所述助熔底部填充材料填充在所述管芯和所述封装衬底之间的区域。
6.根据权利要求4所述的装置，其中，所述助熔底部填充材料覆盖所述各个互连结构的所述焊接接合部；以及
其中，在所述助熔底部填充材料与所述管芯之间设置有空气间隙。
7.根据权利要求3所述的装置，其中，
所述封装衬底包括印刷电路板；以及
所述多个焊垫被布置在所述印刷电路板的面向所述管芯的表面上。
8.根据权利要求3所述的装置，其中，
所述封装衬底包括具有多个开口的挠曲带，所述多个开口形成在所述挠曲带的面向所述管芯的第一表面和所述挠曲带的被布置为与所述第一表面相反的第二表面之间；以及
所述各个焊垫被布置在所述挠曲带的所述第二表面上，所述各个互连结构通过所述多个开口中的各个开口与所述各个焊垫接合。
9.根据权利要求3所述的装置，还包括：
片状模制结构或带结构，所述片状模制结构或所述带结构包括形成在所述管芯上的环氧材料，以密封所述管芯的无源表面和所述管芯的与所述管芯的所述无源表面基本垂直的表面的至少一部分，其中，空气间隙将所述片状模制结构或所述带结构与所述封装衬底隔开。
10.根据权利要求9所述的装置，其中，空气间隙将所述片状模制结构或所述带结构与所述助熔底部填充材料隔开。
11.根据权利要求9所述的装置，其中，
所述片状模制结构或所述带结构的表面具有激光标刻；以及
所述片状模制结构或所述带结构的所述表面是平滑的以利于真空粘附。
12.根据权利要求9所述的装置，其中，所述带结构形成在所述管芯上，所述带结构包括第一层和第二层，所述第一层包括B阶材料并且所述第二层包括C阶材料。
13.根据权利要求1所述的装置，还包括：
使用焊膏而表面安装在所述封装衬底上的一个或更多个无源元件。
14.根据权利要求13所述的装置，其中，所述一个或更多个无源元件包括电容器、电感器、电阻器或滤波器中的至少一种。
15.一种方法，包括：
提供具有形成在封装衬底上的多个焊垫的所述封装衬底，所述多个焊垫被配置成承载形成在管芯上的相应的多个互连结构；以及
在所述封装衬底上沉积助熔底部填充材料，所述助熔底部填充材料包括助熔剂和环氧材料，所述助熔剂被配置成利于使用能焊接的材料在所述多个互连结构中的各个互连结构和所述多个焊垫中的各个焊垫之间形成焊接接合部，所述环氧材料被配置成在形成所述焊接接合部期间硬化以机械地加固所述焊接接合部。
16.根据权利要求15所述的方法，还包括：
以倒装芯片配置的方式将所述管芯附接至所述封装衬底。
17.根据权利要求16所述的方法，其中，所述将所述管芯附接至所述封装衬底包括：
相对于所述封装衬底定位所述管芯，使得所述能焊接的材料被布置在所述各个互连结构和所述各个焊垫之间；以及
执行单次焊接回流工艺，以在所述各个互连结构和所述各个焊垫之间形成所述焊接接合部并且硬化所述助熔底部填充材料的所述环氧材料。
18.根据权利要求17所述的方法，其中，所述助熔剂被配置成在所述单次焊接回流工艺期间、通过从所述各个互连结构和所述各个焊垫的能焊接的表面除去氧化物而利于所述焊接接合部的形成。
19.根据权利要求17所述的方法，还包括：
在执行所述单次焊接回流工艺之前，在所述封装衬底的要安装一个或更多个无源元件的区域上沉积焊膏；以及
将所述一个或更多个无源元件定位成接触所述焊膏，其中，执行所述单次焊接回流工艺在所述一个或更多个无源元件和所述封装衬底之间形成焊接接合部。
20.根据权利要求17所述的方法，还包括：
在所述管芯上形成片状模制结构或带结构，以密封所述管芯的无源表面和所述管芯的与所述管芯的所述无源表面基本垂直的表面的至少一部分，其中，空气间隙将所述片状模制结构或所述带结构与所述封装衬底隔开。
21.根据权利要求20所述的方法，其中，所述方法包括形成所述片状模制结构，所述片状模制结构通过以下步骤形成：
在所述管芯上放置B阶环氧材料；
向所述B阶环氧材料的表面施加热量；以及
施加力以使所述B阶环氧材料和所述管芯在一起，以使得所述B阶环氧材料密封所述管芯的无源表面和所述管芯的与所述管芯的所述无源表面基本垂直的表面的至少一部分。
22.根据权利要求21所述的方法，其中，
在高达175℃的温度下执行向所述B阶环氧材料的所述表面施加热量；以及
执行所述单次焊接回流工艺包括在高达260℃的温度下向所述能焊接的材料施加热量。
23.根据权利要求20所述的方法，其中，继执行所述单次焊接回流工艺之后且在形成所述片状模制结构或所述带结构之前，不对所述封装衬底执行清洁工艺。
24.根据权利要求20所述的方法，还包括：
对所述片状模制结构或所述带结构进行激光标刻。
25.根据权利要求15所述的方法，其中，所述提供具有多个焊垫的封装衬底包括：
提供具有多个焊料焊垫SOP的封装衬底，所述多个焊料焊垫具有布置在所述焊垫的表面上的能焊接的材料。
CN2013100716233A 2012-03-06 2013-03-06 倒装芯片封装技术和配置 Pending CN103311204A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/413,595 US20130234344A1 (en) 2012-03-06 2012-03-06 Flip-chip packaging techniques and configurations
US13/413,595 2012-03-06

Publications (1)

Publication Number Publication Date
CN103311204A true CN103311204A (zh) 2013-09-18

Family

ID=49113380

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2013100716233A Pending CN103311204A (zh) 2012-03-06 2013-03-06 倒装芯片封装技术和配置

Country Status (3)

Country Link
US (2) US20130234344A1 (zh)
KR (1) KR20130102016A (zh)
CN (1) CN103311204A (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108598254A (zh) * 2018-04-19 2018-09-28 嘉盛半导体(苏州)有限公司 滤波器封装方法及封装结构
TWI772011B (zh) * 2021-05-04 2022-07-21 特豪科技股份有限公司 真空式回焊方法及裝置
TWI775280B (zh) * 2021-01-20 2022-08-21 力晶積成電子製造股份有限公司 電容集成結構、電容單元及其製造方法
CN115255538A (zh) * 2021-04-30 2022-11-01 特豪科技股份有限公司 真空式回焊方法及装置

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10153180B2 (en) * 2013-10-02 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor bonding structures and methods
US9627346B2 (en) 2013-12-11 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill pattern with gap
KR20160001169A (ko) * 2014-06-26 2016-01-06 삼성전자주식회사 마킹층을 포함하는 반도체 패키지
CN104157617B (zh) * 2014-07-29 2017-11-17 华为技术有限公司 芯片集成模块、芯片封装结构及芯片集成方法
US9269887B1 (en) * 2015-01-06 2016-02-23 Triquint Semiconductor, Inc. Ultrathin flip-chip packaging techniques and configurations
US10321575B2 (en) * 2015-09-01 2019-06-11 Qualcomm Incorporated Integrated circuit (IC) module comprising an integrated circuit (IC) package and an interposer with embedded passive components
US9873250B2 (en) * 2016-03-14 2018-01-23 Stmicroelectronics, Inc. Microfluidic assembly with mechanical bonds
US10923365B2 (en) * 2018-10-28 2021-02-16 Richwave Technology Corp. Connection structure and method for forming the same
US20200273823A1 (en) * 2019-02-27 2020-08-27 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
CN116705700A (zh) * 2022-02-24 2023-09-05 星科金朋私人有限公司 制造半导体封装的方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6946601B1 (en) * 2004-05-28 2005-09-20 Via Technologies Inc. Electronic package with passive components
US20050236704A1 (en) * 2004-04-27 2005-10-27 Jeng-Da Wu Chip package structure and process for fabricating the same
US20090127703A1 (en) * 2007-11-20 2009-05-21 Fujitsu Limited Method and System for Providing a Low-Profile Semiconductor Assembly
US7633144B1 (en) * 2006-05-24 2009-12-15 Amkor Technology, Inc. Semiconductor package
US20110198762A1 (en) * 2010-02-16 2011-08-18 Deca Technologies Inc. Panelized packaging with transferred dielectric

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4949224A (en) * 1985-09-20 1990-08-14 Sharp Kabushiki Kaisha Structure for mounting a semiconductor device
US6353420B1 (en) * 1999-04-28 2002-03-05 Amerasia International Technology, Inc. Wireless article including a plural-turn loop antenna
JP4403631B2 (ja) * 2000-04-24 2010-01-27 ソニー株式会社 チップ状電子部品の製造方法、並びにその製造に用いる擬似ウエーハの製造方法
US6281046B1 (en) * 2000-04-25 2001-08-28 Atmel Corporation Method of forming an integrated circuit package at a wafer level
US6458472B1 (en) * 2001-01-08 2002-10-01 Henkel Loctite Corporation Fluxing underfill compositions
JP4126891B2 (ja) * 2001-08-03 2008-07-30 セイコーエプソン株式会社 半導体装置の製造方法
SG115455A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Methods for assembly and packaging of flip chip configured dice with interposer
SG115456A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
JP2004247530A (ja) * 2003-02-14 2004-09-02 Renesas Technology Corp 半導体装置及びその製造方法
US7939934B2 (en) * 2005-03-16 2011-05-10 Tessera, Inc. Microelectronic packages and methods therefor
US7790504B2 (en) * 2006-03-10 2010-09-07 Stats Chippac Ltd. Integrated circuit package system
US8125072B2 (en) * 2009-08-13 2012-02-28 Infineon Technologies Ag Device including a ring-shaped metal structure and method
US8236617B2 (en) * 2010-06-04 2012-08-07 Stats Chippac, Ltd. Semiconductor device and method of forming thermally conductive layer between semiconductor die and build-up interconnect structure
US8456021B2 (en) * 2010-11-24 2013-06-04 Texas Instruments Incorporated Integrated circuit device having die bonded to the polymer side of a polymer substrate
JP5385247B2 (ja) * 2010-12-03 2014-01-08 信越化学工業株式会社 ウエハモールド材及び半導体装置の製造方法
JP6055259B2 (ja) * 2012-10-03 2016-12-27 日東電工株式会社 封止シート被覆半導体素子、その製造方法、半導体装置およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050236704A1 (en) * 2004-04-27 2005-10-27 Jeng-Da Wu Chip package structure and process for fabricating the same
US6946601B1 (en) * 2004-05-28 2005-09-20 Via Technologies Inc. Electronic package with passive components
US7633144B1 (en) * 2006-05-24 2009-12-15 Amkor Technology, Inc. Semiconductor package
US20090127703A1 (en) * 2007-11-20 2009-05-21 Fujitsu Limited Method and System for Providing a Low-Profile Semiconductor Assembly
US20110198762A1 (en) * 2010-02-16 2011-08-18 Deca Technologies Inc. Panelized packaging with transferred dielectric

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108598254A (zh) * 2018-04-19 2018-09-28 嘉盛半导体(苏州)有限公司 滤波器封装方法及封装结构
TWI775280B (zh) * 2021-01-20 2022-08-21 力晶積成電子製造股份有限公司 電容集成結構、電容單元及其製造方法
US11854742B2 (en) 2021-01-20 2023-12-26 Powerchip Semiconductor Manufacturing Corporation Capacitor intergated structure.capacitor unit and manufacturing process thereof
CN115255538A (zh) * 2021-04-30 2022-11-01 特豪科技股份有限公司 真空式回焊方法及装置
TWI772011B (zh) * 2021-05-04 2022-07-21 特豪科技股份有限公司 真空式回焊方法及裝置

Also Published As

Publication number Publication date
US20130234344A1 (en) 2013-09-12
US20140106511A1 (en) 2014-04-17
KR20130102016A (ko) 2013-09-16

Similar Documents

Publication Publication Date Title
CN103311204A (zh) 倒装芯片封装技术和配置
US11961805B2 (en) Devices and methods related to dual-sided radio-frequency package with overmold structure
CN108604582B (zh) 承载超薄衬底
CN109637934B (zh) 电子器件及制造电子器件的方法
US20170179041A1 (en) Semiconductor package with trenched molding-based electromagnetic interference shielding
WO2017111956A1 (en) Semiconductor package with electromagnetic interference shielding
KR102607649B1 (ko) 반도체 패키지들
US8945989B2 (en) Stiffened semiconductor die package
KR101363392B1 (ko) 고출력 증폭기용 GaN 반도체 패키지 및 그 제조방법
EP4160668A1 (en) Leadless power amplifier package including topside termination arrangements
KR20160135688A (ko) 박형 샌드위치 임베디드 패키지
CN103065984A (zh) 用于半导体器件的封装方法
US11749589B2 (en) Module
KR101649429B1 (ko) 관통 기판 비아들을 갖는 집적 회로 구성들 및 관통 기판 비아들을 갖는 집적 회로 구성들을 형성하는 방법들
US9704812B1 (en) Double-sided electronic package
CN111642122B (zh) 电磁屏蔽结构及其制造方法
US8912641B1 (en) Low profile electronic package and associated methods
PH12013000075A1 (en) Flip-chip packaging techniques and configurations
KR101898479B1 (ko) 복수 캐리어 기판을 이용한 인쇄회로기판 제조 방법
US20120074561A1 (en) Backmetal replacement for use in the packaging of integrated circuits
US20140097545A1 (en) Package structure and method for manufacturing package structure
US20140197549A1 (en) Semiconductor package and method of manufacturing the same
JPS58138062A (ja) 半導体装置のボンデイング方式

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20161123

Address after: North Carolina

Applicant after: Qorvo USA Inc.

Address before: oregon

Applicant before: Triquint Semiconductor Inc

WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20130918