CN102799537A - Management method for dual-port RAM (Random Access Memory) buffer in spacecraft AOS (Advanced Orbiting System) - Google Patents
Management method for dual-port RAM (Random Access Memory) buffer in spacecraft AOS (Advanced Orbiting System) Download PDFInfo
- Publication number
- CN102799537A CN102799537A CN2012102142008A CN201210214200A CN102799537A CN 102799537 A CN102799537 A CN 102799537A CN 2012102142008 A CN2012102142008 A CN 2012102142008A CN 201210214200 A CN201210214200 A CN 201210214200A CN 102799537 A CN102799537 A CN 102799537A
- Authority
- CN
- China
- Prior art keywords
- vcdu
- child partition
- signal
- read
- packet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
The invention discloses a management method for a dual-port RAM (Random Access Memory) buffer in a spacecraft AOS (Advanced Orbiting System). The management method comprises the following steps of: partitioning the dual-port RAM buffer according to the length of VCDU (Virtual Channel Data Unit) data packets in the AOS, and coding partitioned sub-partitions; when the VCDU data packet is written, determining the to-be-written sub-partition according to a writing selection signal, wherein if the sub-partition is empty, the VCDU data packet is written into the sub-partition and the writing selection signal points to the next sub-partition, and if the sub-partition is full, the VCDU data packet is discarded; and when the VCDU data packet is read, determining the to-be-read sub-partition according to a reading selection signal, wherein if the sub-partition is full, the VCDU data packet in the sub-partition is read, and the reading selection signal points to the next to-be-read sub-partition, and if the sub-partition is empty, abandoning the current reading operation. The method disclosed by the invention realizes independent storage management on the VCDU data packets in the dual-port RAM buffer.
Description
Technical field
The present invention relates to a kind of spacecraft AOS system dual port RAM buffer management method.
Background technology
The data service and the data type of spacecrafts such as novel remote sensing satellite, deep space probe and airship are numerous; Attributes such as the speed of Various types of data, distribution, real-time, importance, transmission quality requirements have nothing in common with each other; Therefore when Aerospace Data Systems designs, generally adopting the AOS that dirigibility is strong, adaptability is good (Advanced Orbiting System, senior to the rail system) agreement to carry out the packing of data, scheduling and multiple connection handles.According to the AOS agreement; The data of various particular types are through packing with after formaing processing; Form (the Virtual Channel Data Unit of some kinds of virtual channel data unit units that length is fixed, form is identical by data category; VCDU), and pseudo channel of every type of VCDU correspondence (Virtual Channel, VC); Each pseudo channel is the same physical channel of time slot time-sharing multiplex with the transmission cycle of VCDU frame, realizes all VCDU data cells replacing, transmitting continuously on physical channel through the scheduling multiple connection.
In the process of the AOS protocol processes equipment (like the data multiplexer) of spacecraft to VCDU scheduling service data and multiple connection processing; Be required to be each virtual channel allocation and organize suitable buffer area to be used to receive the VCDU data cell; This buffer area should be at broad speed range endoadaptation synchronous, asynchronous or etc. the time input, can output when waiting at a high speed be provided to physical channel again simultaneously.In storage on the star with handle under all limited condition of resource, need that a kind of interface operation is simple, zmodem, high efficiency buffer zone tissue and management method, realize the high speed scheduling of VCDU Service Data Unit and transmit.
Because VCDU service needed output high-speed data-flow, so adopt the internal logic resource and the buffer memory area resource of high speed fpga chip to realize the VCDU business function in the AOS protocol processes equipment.In the prior art, buffer area is usually designed to the FIFO form, and the operation of its read-write interface is simpler, but has the inherent shortcoming that can't independently recover after data shift and the logic upset taking place under the space radiation environment influence.Adopt the design of double-interface RAM buffer district can overcome the defective of FIFO well; But existing scheme needs line module to participate in the address administration and the switching controls in double-interface RAM buffer district usually; Make complex design, reliability reduces, and can not well adapt to the application requirements of spacecraft data system.
Summary of the invention
Technology of the present invention is dealt with problems and is: to the deficiency of prior art, a kind of spacecraft AOS system dual port RAM buffer management method is provided, has realized the autonomous storage administration of VCDU packet in the dual port RAM buffer zone.
Technical solution of the present invention is:
A kind of spacecraft AOS system dual port RAM buffer management method is used for dual port RAM is read and write Autonomous Control, may further comprise the steps:
According to VCDU length of data package in the AOS system dual port RAM buffer zone is divided, and to the child partition coding after dividing;
When writing the VCDU packet:
Receive the VCDU data stream of input; Select signal to confirm child partition to be written according to writing;
If child partition is dummy status, then the VCDU packet write child partition, and select signal to point to next child partition writing to write when finishing; If child partition is for full state, then with the VCDU data packet discarding;
When reading the VCDU packet:
Select signal to confirm child partition to be read according to reading;
If child partition is then read the VCDU packet in the child partition for full state, and when reading end, will read and select signal to point to the next child partition that continues; If child partition is a dummy status, then abandon current read operation.
Further, when writing the VCDU packet, each VCDU packet all writes dual port RAM according to the address realm that writes of 0～L-1, and said write selects signal to confirm the current child partition that writes; When writing the writing the address and be L of VCDU packet, said write selects signal to point to next child partition, and puts current child partition for full, and wherein, L is said VCDU data packet length.
Further, when reading the VCDU packet, each VCDU packet is all read dual port RAM according to the address realm of reading of 0～L-1, and said reading selects signal to confirm the current child partition of reading; Read the address when being L when what read the VCDU packet, said reading selects signal to point to next child partition, and puts current child partition for empty, and wherein, L is said VCDU data packet length.
Further; Said child partition has sky marking signal and full scale will signal; When said empty marking signal effectively and the then corresponding child partition of full scale will invalidating signal be dummy status; Effective and the invalid then corresponding child partition of empty marking signal is full state when said full scale will signal, and said empty marking signal drives by reading clock, and full scale will signal drives by writing clock; After child partition writes complete VCDU packet, write clock and put full scale will signal for effectively, read clock detection after effective full scale will, it is invalid putting the sky marking signal; After child partition was read complete VCDU packet, reading clock, to put the sky marking signal effective, writes clock detection behind effective empty marking signal, and it is invalid putting full scale will signal.
The present invention compared with prior art has following advantage:
(1) the buffer zone external interface simple, general-purpose of employing dual port RAM buffer zone autonomous management method has the advantage identical with fifo buffer, is convenient in the design of spacecraft AOS protocol devices, adopt; Closed loop Autonomous Control mode is adopted in tissue that buffer zone is inner and switching, and is externally transparent, need not line module and participates in, and saves on the star and handles resource, reduces the system design complexity.
(2) compare with the fifo buffer of available technology adopting, the dual port RAM buffer zone has better fault freedom in space radiation environment.When single-particle inversion or bursty interference data occurring, FIFO meeting occurrence logic mistake and internal data displacement fault also continue to accumulate and can't recover, and ground receiving equipment must carry out the fault-tolerant processing of complicacy to data.Can recover voluntarily behind the ram buffer generation single-particle inversion among the present invention, the bursty interference data can be dropped and the data shift mistake can not occur, have reduced the processing burden of ground receiving system.
(3) through the sky of judging the dual port RAM child partition, the feasibility of two signal specified datas of full scale will read-write operation; Realized a kind of reliable read-write authorization; When all child partitions are all empty, do not abandon newly arrived data, can protect the data in the buffer zone; When all child partitions all less than the time abandon read operation, can effectively prevent the output of interfering data in short-term.
Description of drawings
Fig. 1 is a process flow diagram of the present invention;
Fig. 2 is for writing sequential relationship;
Fig. 3 is for reading sequential relationship.
Embodiment
Just combine flow process shown in the accompanying drawing 1 that the present invention is done further introduction below.
With the example that is operating as to VCDU data cell in the AOS system; It is k that the AOS system is provided with pseudo channel quantity altogether; Pseudo channel multiple connection output code speed is greater than the input code speed maximal value sum of pseudo channel, and promptly the VCDU data cell of each pseudo channel reception can in time be read by the multiple connection scheduler module.The length of each pseudo channel VCDU data cell is fixed as L (124Byte≤L≤1275Byte).
(1), the buffer zone of each pseudo channel is divided into the child partition of several same size, the corresponding dual port RAM storage area of each child partition according to the length L of above-mentioned VCDU data cell.The available buffer size of i road pseudo channel is M
i(Byte), child partition quantity n
iFor:
In the following formula, i=1 ..., k, k are the pseudo channel number; J is an integer, n
iFor rounding the result.
Child partition to above-mentioned definite size is encoded, and adopts the binary counting value that each subregion is encoded, and is designated as: 0b, 1b, 10b, 11b, 100b ..., (2
j-1) b.
(2) write the VCDU packet
When writing the VCDU packet, the VCDU data packet stream that serial is imported carries out the complete single VCDU packet of serial to parallel conversion acquisition.What the outside write dual port RAM at every turn is a complete VCDU packet, and promptly a VCDU packet is write full dual port RAM child partition.Each child partition is provided with an empty marking signal EMP and a full scale will signal FULL, when writing the VCDU packet to child partition, operates by byte, and as far as write operation, the address realm that writes of each VCDU packet is 0～L-1.Actual storage zone in dual port RAM is by the child partition of selecting signal to confirm to writing of each VCDU, write to select signal to point to the current VCDU packet that writes of storage.The length that writes to the VCDU packet that writes is added up; After L byte writes completion; A complete VCDU packet is written to by writing in the child partition of selecting the signal appointment; Put current buffer zone for expiring state, promptly empty marking signal EMP is invalid and full scale will signal FULL is effectively, writes simultaneously to select signal to add 1 sensing next one child partition to be written.
Before child partition is carried out write operation, need check by full state the sky of child partition.The empty marking signal EMP and the full scale will signal FULL that are utilized as each child partition setting judge.If empty marking signal EMP is that effectively full scale will signal FULL is invalid, then current child partition is empty, allows to write the VCDU packet; Otherwise current child partition is for full, shows that all child partitions have write fullly, do not have the child partition that is in dummy status, then abandons the VCDU packet that current needs write.
(3) read the VCDU packet
When reading the VCDU packet, the data in the dual port RAM buffer zone read a complete VCDU packet by the multiple connection scheduling unit by byte at every turn, promptly read the child partition of an empty storage VCDU packet.The VCDU packet is corresponding with writing, and as far as read operation, the effective range that reads of multiple connection scheduling unit is 0～L-1, and the VCDU packet that concrete data content is stored by the child partition of reading in the dual port RAM of selecting the signal sensing is confirmed.
Before child partition is read, adopt empty marking signal EMP and full scale will signal FULL child partition to be read to be carried out the judgement of empty full state equally.If the child partition non-NULL then will be read data wherein by address realm 0～L-1 as a complete VCDU packet; Otherwise, there is not the child partition that is in full state, abandon current read operation.
Above-mentioned write or the read operation process in, the interface signal relevant with dual port RAM comprises:
Write operation comprises: write clock CLKw; Write and enable WrEN, write fashionable effective in data; Write address WrAddr writes the back counts in every byte data, and scope is 0～L-1; The direct control data of above signal writes in the dual port RAM by byte.
Read operation comprises: read clock CLKr; Read to enable RdEN, effective length is the L byte; Read address RdAddr, read the back counts in every byte data, scope is 0～L-1; Above signal directly is used to control dual port RAM by the byte output data.
Corresponding to above-mentioned interface signal; Write or readout in, the EMP signal drives by reading clock CLKr, changes at the CLKr rising edge; Put 1 this child partition of expression and read, put 0 and represent to be written into a VCDU packet in this child partition and not read for empty or data.The FULL signal drives by writing clock CLKw, changes at the CLKw rising edge, puts to have write frame data in 1 this subregion of expression and wait for and reading that putting 0 this subregion of expression is that sky allows to write data.The EMP of each subregion of original state is masked as 1, and FULL is masked as 0.
The operation condition of empty full Status Flag signal is following:
EMP puts 1 condition: read address RdAddr and arrive VCDU frame end, RdAddr=L;
EMP puts 0 condition: by CLKr sampling FULL signal, to put EMP be 0 when detecting the FULL rising edge;
FULL puts 1 condition: write address WrAddr arrives VCDU frame end, WrAddr=L;
FULL puts 0 condition: by CLKw sampling EMP signal, to put FULL be 0 when detecting the EMP rising edge.
Autonomous management to the dual port RAM buffer zone is embodied in the empty full scale will of above child partition synchronization mechanism, and writes and select signal Wr_Sel and read to select the Cyclic Selection of signal Rd_Sel to child partition.According to RAM subregion result, Wr_Sel signal and Rd_Sel signal that width is the j bit are set, be respectively applied for control write operation and read operation and between each child partition, switch.The child partition numbering of the corresponding current selected of the binary counting value of Wr_Sel signal and Rd_Sel signal; Initial value is 0b, points to the subregion that is numbered 0b, and the every switching of write or read afterwards once; Wr_Sel or Rd_Sel counting add 1; Point to the next son subregion, between each child partition, circulate according to this, form the work mechanism of changing a job of taking turns.
Wr_Sel signal and Rd_Sel signal-count condition are following:
Wr_Sel+1: write address WrAddr arrives VCDU frame end, and WrAddr=L representes that current child partition write, and write operation switches to the next son subregion, and Wr_Sel adds 1 operation and drives by writing clock CLKw;
Rd_Sel+1: read address RdAddr and arrive VCDU frame end, RdAddr=L representes that current child partition runs through, and read operation switches to the next son subregion, and Rd_Sel adds 1 operation and drives by reading clock CLKr.
Embodiment
The embodiment of the invention can adopt FPGA to realize in the data multiplexing controlling equipment of satellite or airship, also can adopt dual port RAM chip and DLC(digital logic circuit) to realize.
Adopt the satellite data system of AOS agreement that 2 pseudo channels are set; VCDU data packet length L is 1020Byte; The 1st pseudo channel can be 4096Byte with the capacity of dual port RAM buffer zone, and the 2nd pseudo channel can be 2048Byte with the capacity of dual port RAM buffer zone.
According to the VCDU data packet length dual port RAM buffer zone being carried out child partition divides
The dual port RAM buffer zone carries out five equilibrium according to the VCDU long data packet, and each partition size is got 1024Byte.Pseudo channel 1 available partition number is 4, is numbered 00b, 01b, 10b, 11b, and pseudo channel 2 available partitions are 2, are numbered 0b, 1b.
Write interface parameters
Pseudo channel 1: effective width is the gate-control signal Gate1 of 1020 bytes; Serial data input DATAw1; Write clock CLKw1 frequency 20MHz, average code speed 10Mbps.Pseudo channel 2: effective width is the gate-control signal Gate2 of 1020 bytes; Serial data input DATAw2; Write clock CLKw2 frequency 10MHz, average code speed 1.5Mbps.It is as shown in Figure 2 to write sequential relationship, and buffer zone byte-oriented operation according to the invention is gone here and there and changed the serial data stream of input among Fig. 2, and produces to write and enable WrEN and write address WrAddr, with writing the direct control signal of clock CLKw as dual port RAM.
Read interface parameters
Effective length be 1020 bytes read to enable RdEN; Reading clock CLKr frequency is 2.5MHz, average code speed 18Mbps; Read address RdAddr, effectively model is 0～1019.Read sequential relationship such as Fig. 3, DATAr is the data of buffer zone by byte output.
The empty full scale will of each child partition of pseudo channel signal controlling
Pseudo channel 1 is set: empty sign EMP1 [0..3], full scale will FULL1 [0..3]; Pseudo channel 2: empty sign EMP2 [0..1], full scale will FULL2 [0..1].The corresponding relation such as the following table 1 of empty full scale will and each pseudo channel RAM subregion.
Table 1
The sky sign of each child partition and full scale will signal are provided with in the read-write process to child partition according to above-mentioned interface signal, and it is following that pseudo channel 1 is numbered the empty full scale will of the child partition control mode signal of 00b:
EMP
1[0] signal drives by reading clock CLKr, in the variation of CLKr rising edge, puts 1 expression 00b subregion and has been read for empty or data, puts 0 and representes to be written into frame data in the 00b subregion and not read.FULL
1[0] signal drives by writing clock CLKw1, changes at the CLKw1 rising edge, puts to have write frame data in the 1 expression 00b subregion and wait for and reading that putting 0 expression 00b subregion is that sky allows to write data.The EMP of original state 00b subregion
1[0] is masked as 1, FULL
1[0] is masked as 0.The condition of marking signal action is following:
EMP
1[0] puts 1 condition: read address RdAddr and arrive VCDU frame end, RdAddr=1020;
EMP
1[0] puts 0 condition: by CLKr sampling FULL
1[0] signal is when detecting FULL
1[0] rising edge is put EMP
1[0] be 0;
FULL
1[0] put 1 condition: write address WrAddr1 arrives VCDU frame end, WrAddr1=1020;
FULL
1[0] puts 0 condition: by CLKw1 sampling EMP
1[0] signal is when detecting EMP
1[0] rising edge is put FULL
1[0] be 0.
Other child partitions are empty, the control mode of full scale will signal is identical with above-mentioned 00b subregion.
The child partition switch-over control signal is set
Pseudo channel 1: write and select Wr_ Se, read to select Rd_Sel1, width is 2bit; Pseudo channel 2: write and select Wr_Sel2, read to select Rd_Sel2, width is 1 bit.The corresponding relation such as the following table 2 of signal and each pseudo channel RAM subregion selected in read-write.
Table 2
Wr_Sel1 signal and Rd_Sel1 signal original state are 00b, point to the 00b subregion of pseudo channel 1; Wr_Sel2 signal and Rd_Sel2 signal original state are 0b, point to the 0b subregion of pseudo channel 2.
Writing of pseudo channel 1 selected the Wr_Sel1 signal and read to select Rd_Sel1 signal switching mode following:
Wr_Sel1+1: when write address WrAddr1 arrives VCDU packet end, WrAddr1=1020 representes that current child partition write, and write operation switches to the next son subregion, and Wr_Sel1 adds 1 operation and drives by writing clock CLKw1.
Rd_Sel1+1: read address RdAddr and arrive VCDU packet end, RdAddr=1020 representes that current child partition runs through, and read operation switches to the next son subregion, and Rd_Sel1 adds 1 operation and drives by reading clock CLKr.
Write and select the Wr_Sel1 signal and read to select the Rd_Sel1 signal to change according to the mode of scale-of-two cycle count, be followed successively by 00b, 01b, 10b, 11b, 00b ..., realize 4 child partitions of circulation sensing pseudo channel 1 like this, reach the target of switching.
Writing of pseudo channel 2 selected the Wr_Sel2 signal and read to select the Rd_Sel2 control mode signal same as described above, according to the 1bit cycle count, be followed successively by 0b, 1b, 0b, 1b, 0b ..., be implemented in blocked operation between 2 child partitions of pseudo channel 2.
Write authorization control
The buffer data read-write process of pseudo channel 1 and pseudo channel 2 is independent fully.When satisfying the Writing condition of child partition, the VCDU packet of outside input can write direct in the current child partition of channel.
The enabled condition of writing of pseudo channel 1 is: write and select Wr_Sel1 to choose current child partition, current child partition sky is masked as 1, completely is masked as 0.Original state Wr_Sel1 points to the 00b subregion, and the sky sign EMP of 00b subregion
1[0] be 1, full scale will FULL
1[0] be 0; So allow to write data, after having 1 frame VCDU packet to write among the 00b, Wr_Sel1+1 points to the child partition that is numbered 01b; When having the VCDU packet to arrive once more; Then judge 01b subregion Writing condition, when allowing, write the 01b subregion, write operation is afterwards carried out in each by stages successively.The authorization control mode that writes of pseudo channel 2 is identical with pseudo channel 1.
Arrive as new VCDU packet, but write the current subregion non-NULL of selecting signal to choose, promptly sky is masked as 0 or completely be masked as 1, and then newly arrived VCDU data are dropped.
When the imperfect mistake of length takes place in current child partition ablation process some VCDU packets; Then read-write selects the operation condition of the empty full scale will of signal and child partition not satisfy; The state of a control of current RAM subregion remains unchanged; Still can write current RAM subregion when new VCDU data arrives is arranged once more, cover the deficiency of data of last time.
Read authority control
The enabled condition of reading of pseudo channel 1 is: read to select Rd_Sel1 to choose current child partition; Current child partition sky is masked as 0, and full scale will FULL is 1, and is effective from the transmission enable signal RdEN of multiple connection scheduler module.Initially after a frame VCDU packet writes, at first propose read data request, read to select this moment Rd_Sel1 to point to the 00b subregion, its empty sign EMP by the 00b subregion
1[0] be 0, full scale will FULL
1[0] be 1, when read data request was obtained the authorization, RdEN was effective for the transmission enable signal, satisfies like this and reads enabled condition, and the multiple connection scheduler module reads frame data from the 00b subregion of pseudo channel 1.Run through back 00b subregion and become dummy status, Rd_Sel1+1 points to the 01b subregion, sense data when 01b subregion proposition read request is obtained the authorization.It is identical with pseudo channel 1 that 2 block RAM partition datas of pseudo channel 2 read control procedure.
Reading completion or writing completion status of any one RAM subregion all can trigger corresponding empty sign, full scale will, write and select or read to select the commentaries on classics of signal automatic switchover wheel.
According to above implementation procedure, adopt FPGA to design easily, FPGA design proposal of the present invention has been applied in certain remote sensing satellite data multiplexing device, and is good in rail work.
The unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.
Claims (4)
1. a spacecraft AOS system dual port RAM buffer management method is used for dual port RAM is read and write Autonomous Control, it is characterized in that may further comprise the steps:
According to VCDU length of data package in the AOS system dual port RAM buffer zone is divided, and to the child partition coding after dividing;
When writing the VCDU packet:
Receive the VCDU data stream of input; Select signal to confirm child partition to be written according to writing;
If child partition is dummy status, then the VCDU packet write child partition, and select signal to point to next child partition writing to write when finishing; If child partition is for full state, then with the VCDU data packet discarding;
When reading the VCDU packet:
Select signal to confirm child partition to be read according to reading;
If child partition is then read the VCDU packet in the child partition for full state, and when reading end, will read and select signal to point to the next child partition that continues; If child partition is a dummy status, then abandon current read operation.
2. a kind of spacecraft AOS as claimed in claim 1 system dual port RAM buffer management method; It is characterized in that: when writing the VCDU packet; Each VCDU packet all writes dual port RAM according to the address realm that writes of 0～L-1, and said write selects signal to confirm the current child partition that writes; When writing the writing the address and be L of VCDU packet, said write selects signal to point to next child partition, and puts current child partition for full, and wherein, L is said VCDU data packet length.
3. a kind of spacecraft AOS as claimed in claim 1 system dual port RAM buffer management method; It is characterized in that: when reading the VCDU packet; Each VCDU packet is all read dual port RAM according to the address realm of reading of 0～L-1, and said reading selects signal to confirm the current child partition of reading; Read the address when being L when what read the VCDU packet, said reading selects signal to point to next child partition, and puts current child partition for empty, and wherein, L is said VCDU data packet length.
4. like arbitrary described a kind of spacecraft AOS system dual port RAM buffer management method in the claim 1～3; It is characterized in that: said child partition has sky marking signal and full scale will signal; When said empty marking signal effectively and the then corresponding child partition of full scale will invalidating signal be dummy status; Effective and the invalid then corresponding child partition of empty marking signal is full state when said full scale will signal, and said empty marking signal drives by reading clock, and full scale will signal drives by writing clock; After child partition writes complete VCDU packet, write clock and put full scale will signal for effectively, read clock detection after effective full scale will, it is invalid putting the sky marking signal; After child partition was read complete VCDU packet, reading clock, to put the sky marking signal effective, writes clock detection behind effective empty marking signal, and it is invalid putting full scale will signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210214200.8A CN102799537B (en) | 2012-06-18 | 2012-06-18 | Management method for dual-port RAM (Random Access Memory) buffer in spacecraft AOS (Advanced Orbiting System) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210214200.8A CN102799537B (en) | 2012-06-18 | 2012-06-18 | Management method for dual-port RAM (Random Access Memory) buffer in spacecraft AOS (Advanced Orbiting System) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102799537A true CN102799537A (en) | 2012-11-28 |
| CN102799537B CN102799537B (en) | 2015-07-08 |
Family
ID=47198650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210214200.8A Active CN102799537B (en) | 2012-06-18 | 2012-06-18 | Management method for dual-port RAM (Random Access Memory) buffer in spacecraft AOS (Advanced Orbiting System) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102799537B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105912479A (en) * | 2016-04-07 | 2016-08-31 | 武汉数字派特科技有限公司 | Concurrent data caching method and structure |
| CN110209612A (en) * | 2019-06-05 | 2019-09-06 | 中国核动力研究设计院 | One kind being based on multi-mode DPRAM access method and system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1851633A (en) * | 2005-04-22 | 2006-10-25 | 华为技术有限公司 | Dynamic self-management buffer zone |
| US7242633B1 (en) * | 2004-09-10 | 2007-07-10 | Xilinx, Inc. | Memory device and method of transferring data in memory device |
-
2012
- 2012-06-18 CN CN201210214200.8A patent/CN102799537B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7242633B1 (en) * | 2004-09-10 | 2007-07-10 | Xilinx, Inc. | Memory device and method of transferring data in memory device |
| CN1851633A (en) * | 2005-04-22 | 2006-10-25 | 华为技术有限公司 | Dynamic self-management buffer zone |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105912479A (en) * | 2016-04-07 | 2016-08-31 | 武汉数字派特科技有限公司 | Concurrent data caching method and structure |
| CN110209612A (en) * | 2019-06-05 | 2019-09-06 | 中国核动力研究设计院 | One kind being based on multi-mode DPRAM access method and system |
| CN110209612B (en) * | 2019-06-05 | 2021-04-13 | 中核控制系统工程有限公司 | Multi-state-based DPRAM (dual-port random access memory) access method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102799537B (en) | 2015-07-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102932696B (en) | Satellite-borne high-speed data multiplexer system and realizing method thereof | |
| JP4480845B2 (en) | TDM switch system with very wide memory width | |
| CN105141352B (en) | A kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing system and method | |
| CN104778025A (en) | Circuit structure of first-in first-out memory based on random access memory | |
| CN102624633A (en) | Time-trigger-based SpaceWire network communication method | |
| CN102799537B (en) | Management method for dual-port RAM (Random Access Memory) buffer in spacecraft AOS (Advanced Orbiting System) | |
| US20160239439A1 (en) | Shared Buffer Arbitration For Packet-Based Switching | |
| US7439763B1 (en) | Scalable shared network memory switch for an FPGA | |
| CN104468156B (en) | A kind of method and apparatus that resource overhead is saved using time-slot arbitration | |
| CN103309981A (en) | ADC (analog-to-digital converter) data organization system with high storage efficiency and ADC data organization method | |
| CN102118304B (en) | Cell switching method and cell switching device | |
| EP1091289B1 (en) | Device for processing sonet or SDH frames-DS0 to channel mapping | |
| CN102237943B (en) | Method and device for processing optical transmission frame overhead | |
| CN103220168B (en) | A kind of processing method based on fixed length protocol data packet length exception | |
| US7568074B1 (en) | Time based data storage for shared network memory switch | |
| CN102164095B (en) | Datagram segmentation and reassembly system and realization method for onboard switching module | |
| CN102984088A (en) | Method applied to AFDX exchanger for ensuring uniformity of frame forwarding sequence | |
| CN106683694A (en) | Rate-adaptive storer interface circuit | |
| CN1841978B (en) | Method and apparatus for realizing multipath signal re-timing | |
| US7730276B1 (en) | Striping of data into memory of a network data switch to prevent read and write collisions | |
| CN106445836B (en) | Asynchronous data reading/writing method, system and device | |
| US6721827B2 (en) | Data processing apparatus and data processing method | |
| CN104597805A (en) | System and method for achieving circular register shifting based on FIFO | |
| CN116470927B (en) | Data processing method, device, equipment and storage medium | |
| US7996604B1 (en) | Class queue for network data switch to identify data memory locations by arrival time |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |