CN110209612B - Multi-state-based DPRAM (dual-port random access memory) access method and system - Google Patents
Multi-state-based DPRAM (dual-port random access memory) access method and system Download PDFInfo
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- CN110209612B CN110209612B CN201910487141.3A CN201910487141A CN110209612B CN 110209612 B CN110209612 B CN 110209612B CN 201910487141 A CN201910487141 A CN 201910487141A CN 110209612 B CN110209612 B CN 110209612B
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- G06F13/1668—Details of memory controller
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Abstract
The invention discloses a multi-state-based DPRAM access method, which comprises the following steps: when any controller needs to read data from the receiving buffer area, state information of two buffer areas in the resource state area is called, and an operation corresponding to the state information is obtained from the distribution matrix for execution. The invention also discloses a DPRAM access system based on multiple states. The invention provides a multi-state-based DPRAM access method and a multi-state-based DPRAM access system, and provides a data communication resource access method which achieves high safety, high certainty and high robustness.
Description
Technical Field
The invention relates to the field of safety level equipment of nuclear power plants, in particular to a multi-state-based DPRAM access method and system.
Background
A DPRAM data interaction method is generally used for guaranteeing data interaction between boards in the security level equipment. The advantage of using DPRAM to exchange data is that the components at both ends can independently access the resources inside the DPRAM, but because of this independence, it may cause the components at both ends of the DPRAM to access the same address data, and although the DPRAM manufacturer gives a conflict output signal, this only guarantees the integrity of single data, but not the integrity of data blocks. The conventional method is to divide a queue buffer of a data block in a DPRAM for data interaction of two end elements, but the method needs to open up a queue buffer with proper depth according to the use characteristics of the two end elements; secondly, there is a hardwired state access method, which requires the use of additional state lines for indicating the data access state across the element.
In the prior art, a ping-pong buffer area is used to ensure continuous data interaction of the DPRAM, but the DPRAM controllers are required to perform synchronous interaction, and when asynchronous interaction is performed, two controllers may read and write the same buffer area at the same time, which may cause error reporting of the DPRAM.
Disclosure of Invention
The technical problem to be solved by the invention is that a technology for ensuring continuous DPRAM data interaction by using a ping-pong buffer area exists in the prior art, but synchronous interaction is required by using a controller of the DPRAM, and when asynchronous interaction is carried out, two controllers can read and write the same buffer area at the same time, so that the error report of the DPRAM can be caused.
The invention is realized by the following technical scheme:
a multi-state based DPRAM access method, comprising: the DPRAM comprises a sending buffer area and a receiving buffer area; dividing the receive buffer into two buffers: resource 1 and resource 2; setting a resource state area in the DPRAM, and updating changed state information into the resource state area when the state of any one of the resource 1 and the resource 2 is changed; the method comprises the steps that the same distribution matrix is arranged on two controllers which asynchronously interact with a DPRAM, the distribution matrix is the corresponding relation between the states of the two buffers and the operation executed by the controllers, and the buffers in use in the distribution matrix cannot be reused before the use is finished; when any controller needs to read data from the receiving buffer area, state information of two buffer areas in the resource state area is called, and an operation corresponding to the state information is obtained from the distribution matrix for execution.
In the prior art, when asynchronous interaction is carried out, two controllers may read and write the same buffer area at the same time, when one controller reads or writes one buffer area, the buffer area needs to be locked first, and if the two controllers lock the buffer area at the same time, DPRAM error reporting can occur; in the general field, the delay caused by such error reporting generally does not affect the operation of the whole system, but for the field of nuclear security, the delay caused by such error reporting may have fatal influence; in addition, for the core security field, the processing items and functions of the two controllers are completely different, so that the two controllers cannot perform synchronous interaction on the DPRAMs, and the scheme of the present invention needs to be adopted to process the special problems in the special field.
When the invention is applied, the DPRAM comprises a sending buffer area and a receiving buffer area, the sending buffer area and the receiving buffer area are generally required to be arranged on the DPRAM, the sending buffer area is a buffer area for sending data to the outside by two controllers, and the receiving buffer area is a buffer area for interacting between the two controllers and receiving data from the outside, and the two buffer areas are independent; dividing the receive buffer into two buffers: resource 1 and resource 2, it should be noted here that the number of receiving buffers is generally many, all receiving buffers may be divided here, or a part of receiving buffers for interaction may be divided here, where said division is to divide one receiving buffer into two blocks, that is, resource 1 and resource 2, where data interaction does not occur between the two blocks, which are independent of each other, and this is equivalent to using a ping-pong buffer in the prior art; however, unlike the existing ping-pong operation, the present invention further provides a resource status area for storing the status of the resource 1 and the resource 2, and when the status of any one of the resource 1 and the resource 2 changes, the status of the resource 1 and the resource 2 is updated to the resource status area for the two controllers to read and write.
Meanwhile, an allocation matrix is required to be set to operate and direct the use of the resource 1 and the resource 2, and since the allocation matrix needs to allocate two buffers for the resource 1 and the resource 2, the allocation matrix is a two-dimensional matrix, that is, each state of the resource 1 corresponds to each state of the resource 2 to generate an operation direction, where the number of the operation directions is the square of the number of the states of the resource 2 or the resource 1.
When one controller needs to read data from a receiving buffer area, the state information of two buffer areas in a resource state area is called first, then the state information is matched with an allocation matrix, and the operation corresponding to the state information can be found out, so that the condition that the same buffer area conflicts is avoided.
Further, the states of the resource 1 and the resource 2 are set as five types: writing resources, writing resources successfully, reading resources empty, and reading resources abnormally.
When the method is applied, the controller locks the buffer area when reading and writing data, so that the common state cannot identify the direct difference between the writing resource and the reading resource.
Further, the allocation matrix is:
the columns of the allocation matrix correspond to five states of resource 2 in sequence: writing the resource 2, successfully writing the resource 2, leaving the resource 2 empty, reading the resource 2, and abnormal the resource 2;
the rows of the allocation matrix correspond to five states of resource 1 in sequence: writing resource 1, writing resource 1 successfully, reading resource 1 abnormally.
When the method is applied, the operation of the controller is guided by adopting the distribution matrix, so that the operation setting under each state is very critical; when the two buffers are both in the condition of writing resources, the controller cannot operate the two resources to avoid collision, the controller waits for the two resources, and so on, and when the two resources are written successfully, the two resources need to be compared and then a priority order is selected for reading in order to ensure the continuity of the data block.
Further, the method also comprises the following steps: dividing the two controllers into a master machine and a slave machine; the host and the slave can be mutually converted; the master machine writes data into the DPRAM, and the slave machine reads data from the DPRAM.
When the invention is applied, the two controllers are interacted through the DPRAM, the states of the two controllers are different, so the invention adopts the mode that the controller for writing data is defined as a host computer, and the controller for reading data is defined as a slave computer; the state of the master and the slave is a transient state, that is, if the controller comprises a controller a and a controller B, when the controller a sends data to the controller B, the controller a is the master and the controller B is the slave; in the next process, the data can be converted into data sent by the controller B to the controller A, the controller B is a master computer, and the controller A is a slave computer.
Further, the method also comprises the following steps: when the host needs to send data through the slave, the host writes the data into a sending buffer area and updates the state of the sending buffer area; and reading the data in the sending buffer area and sending the data out after the state of the slave polling to the sending buffer area is updated.
When the invention is applied, as for the sending buffer zone, the problem of collision is not involved, so the data sending is carried out by adopting the ping-pong operation mode, the process of the ping-pong operation mode is simple, and the invention is suitable for the situation that collision is not involved.
Further, the method also comprises the following steps:
when the host needs to send data to the slave, the host reads the states of the resource 1 and the resource 2 from the resource state area, updates the state of the buffer area to be a data writing state after finding an available buffer area, and writes the data into the available buffer area; updating the buffer area state to be a data writing success state after the data writing into the available buffer area is completed;
the slave reads the states of the resource 1 and the resource 2 from the resource state area, acquires the operation corresponding to the states of the resource 1 and the resource 2 from the distribution matrix, and updates the state of the buffer area to be a read data state when the slave starts to read the data in the buffer area; and when the slave finishes reading from the buffer, updating the state of the buffer into a data empty state.
When the method is applied, different processing is creatively carried out on the sending buffer area and the receiving buffer area, so that the sending buffer area and the receiving buffer area both carry out targeted strategies according to the characteristics of the sending buffer area and the receiving buffer area, thereby not only avoiding error delay, but also reducing the resource consumption generated by reading the distribution matrix.
A multi-state based DPRAM access system comprising: DPRAM, master and slave; the master machine and the slave machine asynchronously access the DPRAM, data are written into the DPRAM by the master machine, and data are read from the DPRAM by the slave machine;
the DPRAM includes a transmit buffer and a receive buffer, and the receive buffer is divided into two buffers: resource 1 and resource 2;
setting a resource state area NDB in the DPRAM, and updating changed state information into the resource state area when the state of any one of the resource 1 and the resource 2 is changed;
the host and the slave are both provided with the same distribution matrix, when the slave needs to read data from the receiving buffer area, the state information of the two buffer areas in the resource state area is called, and the operation corresponding to the state information is obtained from the distribution matrix for execution; the master and slave can be switched with each other.
When the invention is applied, the DPRAM comprises a sending buffer area and a receiving buffer area, the sending buffer area and the receiving buffer area are generally required to be arranged on the DPRAM, the sending buffer area is a buffer area for sending data to the outside by two controllers, and the receiving buffer area is a buffer area for interacting between the two controllers and receiving data from the outside, and the two buffer areas are independent; dividing the receive buffer into two buffers: resource 1 and resource 2, it should be noted here that the number of receiving buffers is generally many, all receiving buffers may be divided here, or a part of receiving buffers for interaction may be divided here, where said division is to divide one receiving buffer into two blocks, that is, resource 1 and resource 2, where data interaction does not occur between the two blocks, which are independent of each other, and this is equivalent to using a ping-pong buffer in the prior art; however, unlike the existing ping-pong operation, the present invention further provides a resource status area for storing the status of the resource 1 and the resource 2, and when the status of any one of the resource 1 and the resource 2 changes, the status of the resource 1 and the resource 2 is updated to the resource status area for the two controllers to read and write.
Meanwhile, an allocation matrix is required to be set to operate and direct the use of the resource 1 and the resource 2, and since the allocation matrix needs to allocate two buffers for the resource 1 and the resource 2, the allocation matrix is a two-dimensional matrix, that is, each state of the resource 1 corresponds to each state of the resource 2 to generate an operation direction, where the number of the operation directions is the square of the number of the states of the resource 2 or the resource 1.
When one controller needs to read data from a receiving buffer area, the state information of two buffer areas in a resource state area is called first, then the state information is matched with an allocation matrix, and the operation corresponding to the state information can be found out, so that the condition that the same buffer area conflicts is avoided.
Further, the states of the resource 1 and the resource 2 are set as five types:
writing resources, writing resources successfully, reading resources and reading resources abnormally;
the distribution matrix is:
the columns of the allocation matrix correspond to five states of resource 2 in sequence: writing the resource 2, successfully writing the resource 2, leaving the resource 2 empty, reading the resource 2, and abnormal the resource 2;
the rows of the allocation matrix correspond to five states of resource 1 in sequence: writing resource 1, writing resource 1 successfully, reading resource 1 abnormally.
Further, when the host needs to send data through the slave, the host writes the data into a sending buffer area and updates the state of the sending buffer area;
and reading the data in the sending buffer area and sending the data out after the state of the slave polling to the sending buffer area is updated.
Further, when the host needs to send data to the slave, the host reads the states of the resource 1 and the resource 2 from the resource state area, updates the state of the buffer area to be a data writing state after finding an available buffer area, and writes the data into the available buffer area; updating the buffer area state to be a data writing success state after the data writing into the available buffer area is completed;
the slave reads the states of the resource 1 and the resource 2 from the resource state area, acquires the operation corresponding to the states of the resource 1 and the resource 2 from the distribution matrix, and updates the state of the buffer area to be a read data state when the slave starts to read the data in the buffer area; and when the slave finishes reading from the buffer, updating the state of the buffer into a data empty state.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the invention provides a multi-state-based DPRAM access method and a multi-state-based DPRAM access system, and provides a data communication resource access method which achieves high safety, high certainty and high robustness.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a functional structure design block diagram of the present invention;
FIG. 2 is a diagram of transmit buffer status exchange according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1
As shown in fig. 1, the present invention provides a multi-state based DPRAM access method, which includes: the DPRAM comprises a sending buffer area and a receiving buffer area; dividing the receive buffer into two buffers: resource 1 and resource 2; setting a resource state area in the DPRAM, and updating changed state information into the resource state area when the state of any one of the resource 1 and the resource 2 is changed; the method comprises the steps that the same distribution matrix is arranged on two controllers which asynchronously interact with a DPRAM, the distribution matrix is the corresponding relation between the states of the two buffers and the operation executed by the controllers, and the buffers in use in the distribution matrix cannot be reused before the use is finished; when any controller needs to read data from the receiving buffer area, state information of two buffer areas in the resource state area is called, and an operation corresponding to the state information is obtained from the distribution matrix for execution.
In the prior art, when asynchronous interaction is carried out, two controllers may read and write the same buffer area at the same time, when one controller reads or writes one buffer area, the buffer area needs to be locked first, and if the two controllers lock the buffer area at the same time, DPRAM error reporting can occur; in the general field, the delay caused by such error reporting generally does not affect the operation of the whole system, but for the field of nuclear security, the delay caused by such error reporting may have fatal influence; in addition, for the core security field, the processing items and functions of the two controllers are completely different, so that the two controllers cannot perform synchronous interaction on the DPRAMs, and the scheme of the present invention needs to be adopted to process the special problems in the special field.
In this embodiment, the DPRAM includes a sending buffer and a receiving buffer, and generally, the sending buffer and the receiving buffer need to be present on the DPRAM, where the sending buffer is a buffer for sending data to the outside by two controllers, and the receiving buffer is a buffer for receiving data from the outside and interacting between the two controllers, and the two buffers are independent; dividing the receive buffer into two buffers: resource 1 and resource 2, it should be noted here that the number of receiving buffers is generally many, all receiving buffers may be divided here, or a part of receiving buffers for interaction may be divided here, where said division is to divide one receiving buffer into two blocks, that is, resource 1 and resource 2, where data interaction does not occur between the two blocks, which are independent of each other, and this is equivalent to using a ping-pong buffer in the prior art; however, unlike the existing ping-pong operation, the present invention further provides a resource status area for storing the status of the resource 1 and the resource 2, and when the status of any one of the resource 1 and the resource 2 changes, the status of the resource 1 and the resource 2 is updated to the resource status area for the two controllers to read and write.
Meanwhile, an allocation matrix is required to be set to operate and direct the use of the resource 1 and the resource 2, and since the allocation matrix needs to allocate two buffers for the resource 1 and the resource 2, the allocation matrix is a two-dimensional matrix, that is, each state of the resource 1 corresponds to each state of the resource 2 to generate an operation direction, where the number of the operation directions is the square of the number of the states of the resource 2 or the resource 1.
When one controller needs to read data from a receiving buffer area, the state information of two buffer areas in a resource state area is called first, then the state information is matched with an allocation matrix, and the operation corresponding to the state information can be found out, so that the condition that the same buffer area conflicts is avoided.
To further illustrate the working state of the present embodiment, the states of the resource 1 and the resource 2 are set as five types: writing resources, writing resources successfully, reading resources empty, and reading resources abnormally.
In the implementation of the embodiment, the controller locks the buffer area when reading and writing data, so that the common state cannot identify the direct difference between the writing resource and the reading resource.
To further illustrate the working state of this embodiment, the allocation matrix is:
the columns of the allocation matrix correspond to five states of resource 2 in sequence: writing the resource 2, successfully writing the resource 2, leaving the resource 2 empty, reading the resource 2, and abnormal the resource 2;
the rows of the allocation matrix correspond to five states of resource 1 in sequence: writing resource 1, writing resource 1 successfully, reading resource 1 abnormally.
In the implementation of this embodiment, since the operation of the controller is guided by using the distribution matrix, the operation setting for each state is very critical; when the two buffers are both in the condition of writing resources, the controller cannot operate the two resources to avoid collision, the controller waits for the two resources, and so on, and when the two resources are written successfully, the two resources need to be compared and then a priority order is selected for reading in order to ensure the continuity of the data block.
To further illustrate the working state of the present embodiment, the method further includes the following steps: dividing the two controllers into a master machine and a slave machine; the host and the slave can be mutually converted; the master machine writes data into the DPRAM, and the slave machine reads data from the DPRAM.
In the implementation of this embodiment, when the two controllers interact with each other through the DPRAM, the states of the two controllers are different, so the controller for writing data is defined as the master, and the controller for reading data is defined as the slave; the state of the master and the slave is a transient state, that is, if the controller comprises a controller a and a controller B, when the controller a sends data to the controller B, the controller a is the master and the controller B is the slave; in the next process, the data can be converted into data sent by the controller B to the controller A, the controller B is a master computer, and the controller A is a slave computer.
As shown in fig. 2, to further illustrate the working state of the present embodiment, the method further includes the following steps: when the host needs to send data through the slave, the host writes the data into a sending buffer area and updates the state of the sending buffer area; and reading the data in the sending buffer area and sending the data out after the state of the slave polling to the sending buffer area is updated.
In this embodiment, for the transmission buffer, since the collision problem is not involved, the data transmission is performed by using the ping-pong operation mode, which has a simple process and is suitable for the situation that collision is not involved.
To further illustrate the working state of the present embodiment, the present embodiment further includes the following steps:
when the host needs to send data to the slave, the host reads the states of the resource 1 and the resource 2 from the resource state area, updates the state of the buffer area to be a data writing state after finding an available buffer area, and writes the data into the available buffer area; updating the buffer area state to be a data writing success state after the data writing into the available buffer area is completed;
the slave reads the states of the resource 1 and the resource 2 from the resource state area, acquires the operation corresponding to the states of the resource 1 and the resource 2 from the distribution matrix, and updates the state of the buffer area to be a read data state when the slave starts to read the data in the buffer area; and when the slave finishes reading from the buffer, updating the state of the buffer into a data empty state.
When the method is applied, different processing is creatively carried out on the sending buffer area and the receiving buffer area, so that the sending buffer area and the receiving buffer area both carry out targeted strategies according to the characteristics of the sending buffer area and the receiving buffer area, thereby not only avoiding error delay, but also reducing the resource consumption generated by reading the distribution matrix.
Example 2
As shown in FIG. 1, the present invention is a multi-state based DPRAM access system comprising: DPRAM, master and slave; the master machine and the slave machine asynchronously access the DPRAM, data are written into the DPRAM by the master machine, and data are read from the DPRAM by the slave machine;
the DPRAM includes a transmit buffer and a receive buffer, and the receive buffer is divided into two buffers: resource 1 and resource 2;
setting a resource state area NDB in the DPRAM, and updating changed state information into the resource state area when the state of any one of the resource 1 and the resource 2 is changed;
the host and the slave are both provided with the same distribution matrix, when the slave needs to read data from the receiving buffer area, the state information of the two buffer areas in the resource state area is called, and the operation corresponding to the state information is obtained from the distribution matrix for execution; the master and slave can be switched with each other.
In this embodiment, the DPRAM includes a sending buffer and a receiving buffer, and generally, the sending buffer and the receiving buffer need to be present on the DPRAM, where the sending buffer is a buffer for sending data to the outside by two controllers, and the receiving buffer is a buffer for receiving data from the outside and interacting between the two controllers, and the two buffers are independent; dividing the receive buffer into two buffers: resource 1 and resource 2, it should be noted here that the number of receiving buffers is generally many, all receiving buffers may be divided here, or a part of receiving buffers for interaction may be divided here, where said division is to divide one receiving buffer into two blocks, that is, resource 1 and resource 2, where data interaction does not occur between the two blocks, which are independent of each other, and this is equivalent to using a ping-pong buffer in the prior art; however, unlike the existing ping-pong operation, the present invention further provides a resource status area for storing the status of the resource 1 and the resource 2, and when the status of any one of the resource 1 and the resource 2 changes, the status of the resource 1 and the resource 2 is updated to the resource status area for the two controllers to read and write.
Meanwhile, an allocation matrix is required to be set to operate and direct the use of the resource 1 and the resource 2, and since the allocation matrix needs to allocate two buffers for the resource 1 and the resource 2, the allocation matrix is a two-dimensional matrix, that is, each state of the resource 1 corresponds to each state of the resource 2 to generate an operation direction, where the number of the operation directions is the square of the number of the states of the resource 2 or the resource 1.
When one controller needs to read data from a receiving buffer area, the state information of two buffer areas in a resource state area is called first, then the state information is matched with an allocation matrix, and the operation corresponding to the state information can be found out, so that the condition that the same buffer area conflicts is avoided.
Example 3
In this embodiment, on the basis of embodiment 1 and embodiment 2, in order to further illustrate the working process and the design process of this embodiment, the following examples are given:
1. design constraints are as follows:
the two ends of the DPRAM are divided into a host and a slave;
the DPRAM is divided into a sending buffer area and two receiving buffer areas according to functions;
the host can update the buffer data.
2. Summary of the contents:
as shown in fig. 1: the two ends of the DPRAM are a CPU for executing functions and an FPGA for executing data communication, and the DPRAM exchanges corresponding data.
The invention is divided into three parts: DPRAM resources (hereinafter, simply referred to as resources), DPRAM resource states, and state matrices. The three sections are described as follows:
DPRAM resources: the method comprises the steps that asynchronous access is needed for elements at two ends of a DPRAM (one end of the method is a CPU, and the other end of the method is an FPGA), and the access method is unidirectional for DPRAM resources at each end (namely, an A end can only write, and a B end can only read);
DPRAM resource status: the resource states are divided into 5 states:
writing a resource;
the writing of the resource is successful;
the resource is empty;
reading resources;
DPRAM resource exceptions.
State matrix: the user can select the resources according to the state of the DPRAM resources. The row-column relationship of the state matrix is shown in the following table:
| two resource states | Write resource 2 | Write resource 2 success | Resource 2 is empty | Read resource 2 | Resource 2 Exception |
| Write resource 1 | Wait for 2 resource writes to complete | Read resource 2 | Equal resources 1 | Equal resources 1 | Without updating |
| Write resource 1 success | Reading resource 1 | Comparing two resources | Reading resource 1 | Reading resource 1 | Without updating |
| Resource 1 is empty | Equal resource 2 | Read resource 2 | Without updating | Without updating | Without updating |
| Reading resource 1 | Equal resource 2 | Read resource 2 | Without updating | Without updating | Without updating |
| Resource 1 Exception | Without updating | Without updating | Without updating | Without updating | Without updating |
3. The implementation of the operation flow is as follows:
according to the division, the flow of the DPRAM operation in the system is divided into two types: a transmit buffer operational flow and a receive buffer operational flow.
The operational state diagram of the transmit buffer is shown in fig. 2:
the host of the sending buffer area is a CPU, so that the slave FPGA only needs to poll the state of the sending buffer area all the time, and the conflict avoidance of the state of the sending buffer area is provided by a BUSY signal of a DPRAM, and the specific sequence is as follows:
the CPU writes the data to be sent into a sending buffer area according to the requirement;
the CPU changes the state to the update state 1;
and after the FPGA polls that the sending state is changed into the updating state 1 from the updating state 2 of the last time, the data of the sending buffer area is sent out.
In FIG. 2 Idel is idle, W _ TB is write lock, W _ TS is write unlock, R _ TB is read lock, and R _ TS is read unlock.
Receiving a buffer area operation flow:
the operation of the receiving buffer area is divided into two parts, namely a CPU side operation flow and an FPGA side operation flow;
the CPU side operates:
the CPU reads the state of the receiving buffer areas 1 and 2;
inquiring a slave processing matrix according to the state of the buffer area;
if the available buffer area x exists, updating the state of the buffer area x into CPU read data;
reading the data of the buffer area x;
and after the reading is finished, updating the state of the buffer area x to be idle.
FPGA side operation flow
After successful data is received, reading the states of the buffer areas 1 and 2;
inquiring a host processing matrix according to the state of the buffer area;
if available buffer area x exists, updating the state of the buffer area x into FPGA write data;
writing data to buffer x;
and after the writing is finished, updating the state of the buffer area x into the FPGA writing completion.
The method is already used in a module which is used for standby redundancy configuration in a safe DCS and uses the communication in the station.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A multi-state based DPRAM access method, comprising:
the DPRAM comprises a sending buffer area and a receiving buffer area;
dividing the receive buffer into two buffers: resource 1 and resource 2;
setting a resource state area in the DPRAM, and updating changed state information into the resource state area when the state of any one of the resource 1 and the resource 2 is changed;
the method comprises the steps that the same distribution matrix is arranged on two controllers which asynchronously interact with a DPRAM, the distribution matrix is the corresponding relation between the states of the two buffers and the operation executed by the controllers, and the buffers in use in the distribution matrix cannot be reused before the use is finished;
when any controller needs to read data from the receiving buffer area, state information of two buffer areas in the resource state area is called, and an operation corresponding to the state information is obtained from the distribution matrix for execution;
further comprising the steps of:
dividing the two controllers into a master machine and a slave machine; the host and the slave can be mutually converted;
the host writes data into the DPRAM, and the slave reads data from the DPRAM;
further comprising the steps of:
when the host needs to send data to the slave, the host reads the states of the resource 1 and the resource 2 from the resource state area, updates the state of the buffer area to be a data writing state after finding an available buffer area, and writes the data into the available buffer area; updating the buffer area state to be a data writing success state after the data writing into the available buffer area is completed;
the slave reads the states of the resource 1 and the resource 2 from the resource state area, acquires the operation corresponding to the states of the resource 1 and the resource 2 from the distribution matrix, and updates the state of the buffer area to be a read data state when the slave starts to read the data in the buffer area; and when the slave finishes reading from the buffer, updating the state of the buffer into a data empty state.
2. A multi-state based DPRAM access method according to claim 1, wherein the states of resource 1 and resource 2 are set to five types:
writing resources, writing resources successfully, reading resources empty, and reading resources abnormally.
3. The multi-state based DPRAM access method of claim 2, wherein the allocation matrix is:
the columns of the allocation matrix correspond to five states of resource 2 in sequence: writing the resource 2, successfully writing the resource 2, leaving the resource 2 empty, reading the resource 2, and abnormal the resource 2;
the rows of the allocation matrix correspond to five states of resource 1 in sequence: writing resource 1, writing resource 1 successfully, reading resource 1 abnormally.
4. The multi-state based DPRAM access method of claim 1, further comprising the steps of:
when the host needs to send data through the slave, the host writes the data into a sending buffer area and updates the state of the sending buffer area;
and reading the data in the sending buffer area and sending the data out after the state of the slave polling to the sending buffer area is updated.
5. A multi-state based DPRAM access system, comprising: DPRAM, master and slave; the master machine and the slave machine asynchronously access the DPRAM, data are written into the DPRAM by the master machine, and data are read from the DPRAM by the slave machine;
the DPRAM includes a transmit buffer and a receive buffer, and the receive buffer is divided into two buffers: resource 1 and resource 2;
a resource state area is arranged in the DPRAM, and when the state of any one of the resource 1 and the resource 2 changes, the changed state information is updated into the resource state area;
the host and the slave are both provided with the same distribution matrix, when the slave needs to read data from the receiving buffer area, the state information of the two buffer areas in the resource state area is called, and the operation corresponding to the state information is obtained from the distribution matrix for execution; the host and the slave can be mutually converted; the allocation matrix is the corresponding relation between the states of the two buffer areas and the operation executed by the controller, and the buffer area in use in the allocation matrix is not used again before the use is finished;
when the host needs to send data to the slave, the host reads the states of the resource 1 and the resource 2 from the resource state area, updates the state of the buffer area to be a data writing state after finding an available buffer area, and writes the data into the available buffer area; updating the buffer area state to be a data writing success state after the data writing into the available buffer area is completed;
the slave reads the states of the resource 1 and the resource 2 from the resource state area, acquires the operation corresponding to the states of the resource 1 and the resource 2 from the distribution matrix, and updates the state of the buffer area to be a read data state when the slave starts to read the data in the buffer area; and when the slave finishes reading from the buffer, updating the state of the buffer into a data empty state.
6. The multi-state based DPRAM access system of claim 5, wherein the states of resource 1 and resource 2 are set to five:
writing resources, writing resources successfully, reading resources and reading resources abnormally;
the distribution matrix is:
the columns of the allocation matrix correspond to five states of resource 2 in sequence: writing the resource 2, successfully writing the resource 2, leaving the resource 2 empty, reading the resource 2, and abnormal the resource 2;
the rows of the allocation matrix correspond to five states of resource 1 in sequence: writing resource 1, writing resource 1 successfully, reading resource 1 abnormally.
7. The multi-state based DPRAM access system of claim 5, wherein when a master needs to send data through a slave, the master writes the data into a send buffer and updates the send buffer state;
and reading the data in the sending buffer area and sending the data out after the state of the slave polling to the sending buffer area is updated.
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