CN102487033B - Method for forming standard SOI (Silicon On Insulator) structure - Google Patents
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Abstract
The invention relates to a method for forming a standard SOI (Silicon On Insulator) structure. The method comprises the following steps of: providing a substrate which comprises a first semiconductor layer, a first insulating layer positioned on the first semiconductor layer and a second semiconductor layer positioned on the insulating layer; patterning the first insulating layer and the second semiconductor layer, forming an opening and exposing the first semiconductor layer; forming a side wall with a preset height on the side wall of the opening, and forming a first semiconductor material with the preset height in the opening; and forming a second semiconductor material in the opening, and covering the side wall and the first semiconductor material, wherein the surface of the second semiconductor material is level to that of the second semiconductor layer. Compared with the prior art, the method is simple in process and easy in implementation.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to the method that forms upper silicon of quasi-insulator (Silicon on Insulator is called for short SOI) structure.
Background technology
Along with the development of semiconductor technology, the integrated level of integrated circuit is more and more higher, and (CD) is more and more less for the characteristic size of device.When the feature size downsizing of device is to deep-submicron (0.25 micron hereinafter referred to as deep-submicron), the leakage current of device increases, drain-induced barrier reduces (DIBL, Drain induction barrier lower) effect and short-channel effect are more and more obvious, become the subject matter that the needs of device dimensions shrink overcome.
Ultra-thin body (UTB) SOI device architecture is a kind of MOS device based on SOI substrate, and silicon film thickness is very thin, can effectively suppress short-channel effect and reduce off-state leakage current.But, in order to realize good grid control ability, ultra-thin body SOI device architecture needs very thin silicon fiml, it is long that general silicon film thickness requires to be less than 1/4 grid, this not only proposes harsh requirement to technique, and very thin si membrane can cause, and mobility reduces, threshold voltage increases and the problem such as performance fluctuation increase, seriously reduce the performance of device; On the other hand, self-heating effect, drain electrode end are all the problem that ultra-thin body SOI device architecture exists by buried regions to the coupling of channel region and threshold value adjusting.
The problem existing in order to solve ultra-thin body SOI device architecture, " Wang Yangyuan, Zhang Xing, Liu Xiaoyan, Kang Jinfeng, yellow as " at Chinese science E, collect: information science 2008 the 38th the 6th phase of volume 921st～932 pages of papers of delivering " new technology and new construction device in 32nm and following technology node CMOS technology thereof " disclose a kind of novel accurate SOI device architecture, can effectively overcome the problem that above-described ultra-thin body SOI device architecture exists.Fig. 1 is the cross-sectional view of the accurate SOI device architecture that provides in paper, and with reference to figure 1, this accurate SOI device architecture comprises: substrate 10; L-type isolation structure 11, is arranged in described substrate 10; Grid structure, comprising: grid 21, and the gate dielectric layer 22 between grid 21 and substrate 10, is positioned at grid 21 and gate dielectric layer 22 side wall 23 around; Source region 12, drain region 13, be arranged on substrate 10, described L-type isolation structure 11; Extension area, 14He drain region, extension area, source region 15, in substrate 10, between side wall 23 and L-type isolation structure 11.The method that proposes the accurate SOI device architecture shown in Fig. 1 in paper is: first carry out STI (shallow trench isolation from) technique; After STI technique completes, carry out the injection of raceway groove threshold value, adjusting threshold voltage; Afterwards, on substrate, form gate dielectric layer, on gate dielectric layer, form polysilicon layer, on polysilicon layer, form silicon nitride layer and oxide layer and protect subsequent etching and the impact of oxidation technology on grid structure as hard mask; Etching forms after grid 21 and gate dielectric layer 22, at grid 21 and gate dielectric layer 22, forms oxide layer side wall 23 around; Form after side wall 23, with inductively coupled plasma (ICP, inductively coupled plasma) anisotropic etching active area regions and region, drain region, active area regions defines the region in source region, and drain region zone definitions goes out the region in drain region; Afterwards, in active area regions and region, drain region, form silicon nitride side wall, protection extension area, 14He drain region, extension area, source region 15 is not oxidized in the process of follow-up formation L-type isolation structure 11; Then, then use ICP etching active area regions and region, drain region, utilize low temperature wet-oxygen oxidation to form L-type isolation structure 11 around active area regions and region, drain region and region, drain region; Afterwards, wet method is removed silicon nitride side wall, deposit spathic silicon is filled active area regions and the region, drain region being etched, then carry out chemical-mechanical planarization, wet etching polysilicon, carry out 12He drain region, source region 13 Implantations, after Implantation, carry out rapid thermal annealing, finally carry out hypoxemia, form the subsequent techniques such as contact hole and metal interconnecting wires.
Yet, the method for the accurate SOI device architecture of formation of above-described prior art, complex process, particularly fills active area regions and the additional chemical-mechanical planarization in region, drain region with polysilicon, and wet etching polysilicon; And source region and drain region adopt polysilicon and non-monocrystalline silicon, its electric property is affected.
Summary of the invention
The problem that the present invention solves is that the method for the accurate SOI device architecture of formation of prior art is complicated, and source region and drain region adopt polysilicon and non-monocrystalline silicon, and its electric property is affected.
For addressing the above problem, the invention provides a kind of method that forms accurate soi structure, comprising:
Substrate is provided, and described substrate comprises the first semiconductor layer, is positioned at the first insulating barrier on described the first semiconductor layer, is positioned at the second semiconductor layer on described insulating barrier;
Graphical described the first insulating barrier and described the second semiconductor layer, form opening, exposes described the first semiconductor layer;
At the sidewall of described opening, form the side wall of predetermined altitude, and in described opening, form the first semi-conducting material of described predetermined altitude;
In described opening, form the second semi-conducting material, cover described side wall and described the first semi-conducting material, and the surface of described the second semi-conducting material is equal with the surface of described the second semiconductor layer.
Optionally, also comprise:
On the surface forming at described the second semi-conducting material and the second semiconductor layer, form grid structure, described grid structure comprises: the gate dielectric layer between grid, the surface that forms at grid and described the second semi-conducting material and the second semiconductor layer and be positioned at described grid and gate dielectric layer side wall around;
Take described grid structure as mask, carry out Implantation, in the substrate of described grid structure both sides, form source region and drain region.
Optionally, described graphical described the first insulating barrier and described the second semiconductor layer, form opening at described substrate, exposes described the first semiconductor layer and comprise:
On described the second semiconductor layer, form patterned hard mask layer;
The described patterned hard mask layer of take is mask, and the first insulating barrier and described the first semiconductor layer described in etching form opening.
Optionally, described hard mask layer comprises: silicon oxide layer and silicon nitride layer, and described silicon oxide layer is positioned on described the second semiconductor layer, and described silicon nitride layer is positioned on described silicon oxide layer.
Optionally, at the sidewall of described opening, form the side wall of predetermined altitude, and the first semi-conducting material that forms described predetermined altitude in described opening comprises:
Form the second insulating barrier, cover the surface of described patterned hard mask layer, the bottom of described opening and sidewall;
Return to carve and remove the surface of described patterned hard mask layer and the second insulating barrier of open bottom, at the sidewall formation side wall of described opening;
In described opening, form the first semi-conducting material of predetermined altitude;
Remove the second insulating barrier not covered by described the first semi-conducting material, form the side wall of predetermined altitude.
Optionally, utilize epitaxial growth method in described opening, to form the first semi-conducting material of predetermined altitude.
Optionally, utilize epitaxial growth method in described opening, to form the second semi-conducting material.
Optionally, described epitaxial growth method is selected from: rapid heat chemical vapour deposition, high vacuum chemical vapour deposition, molecular beam epitaxy.
Optionally, the material of described the second insulating barrier is silica.
Optionally, the method for described formation silica is thermal oxidation or plasma enhanced chemical vapor deposition.
Optionally, the thickness of described the second insulating barrier is 10 dust～200 dusts.
Optionally, the thickness of described the first insulating barrier is 100 dust～2000 dusts.
Optionally, described the first semiconductor layer, the second semiconductor layer, the first semi-conducting material and the second semi-conducting material are selected from monocrystalline silicon, monocrystalline carbon doped silicon or monocrystalline germanium silicon.
Optionally, described the first semiconductor layer and described the second semiconductor layer are monocrystalline silicon, and the indices of crystallographic plane of described monocrystalline silicon are (100), (110) or (111).
Optionally, described predetermined altitude is 50nm～300nm.
Compared with prior art, the present invention has the following advantages:
The method of the accurate soi structure of formation of the present invention, provides the substrate that comprises the first semiconductor layer, the first insulating barrier, the second semiconductor layer, and silicon-on-insulator is namely provided; At the first insulating barrier and the second semiconductor layer, form opening, expose the first semiconductor layer; In forming the side wall, opening of predetermined altitude, the sidewall of opening forms the first semi-conducting material of predetermined altitude; Afterwards, in opening, form the second semi-conducting material, cover side wall and the first semi-conducting material, and the surface of the second semi-conducting material is equal with the surface of the second semiconductor layer.The first insulating barrier on the side wall of the predetermined altitude of opening sidewalls and the first semiconductor layer has just formed the isolation structure of L-type like this, afterwards, can on the second semiconductor layer and the second semi-conducting material, form grid structure, carry out Implantation and form source region and drain region, compared with prior art, formation technique is simple.
And, in specific embodiment, form after the isolation structure of L-type, form grid structure, and source region and drain region, wherein source region is identical with the material of the second semiconductor layer using as substrate and the second semi-conducting material with drain region, because the semi-conducting material using as substrate is monocrystalline, therefore source region and drain region be also monocrystalline, can solve like this problem that affects device performance that prior art use polysilicon produces as source region and drain region.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the accurate SOI device architecture of prior art;
Fig. 2 is the flow chart of method of the accurate soi structure of formation of the specific embodiment of the present invention;
The cross-sectional view of the method for the accurate soi structure of formation that Fig. 3 a～Fig. 3 g is the specific embodiment of the invention;
Fig. 3 h for forming the cross-sectional view of grid structure on accurate soi structure.
Embodiment
The method of the accurate soi structure of formation of the specific embodiment of the invention, provides the substrate that comprises the first semiconductor layer, the first insulating barrier, the second semiconductor layer, and silicon-on-insulator is namely provided; At the first insulating barrier and the second semiconductor layer, form opening, expose the first semiconductor layer; In forming the side wall, opening of predetermined altitude, the sidewall of opening forms the first semi-conducting material of predetermined altitude; Afterwards, in opening, form the second semi-conducting material, cover side wall and the first semi-conducting material, and the surface of the second semi-conducting material is equal with the surface of the second semiconductor layer.The first insulating barrier on the side wall of the predetermined altitude of opening sidewalls and the first semiconductor layer has just formed the isolation structure of L-type like this, afterwards, can on the second semiconductor layer and the second semi-conducting material, form grid structure, carry out Implantation and form source region and drain region, compared with prior art, formation technique is simple.
And, in specific embodiment, form after the isolation structure of L-type, form grid structure, and source region and drain region, wherein source region is identical with the material of the second semiconductor layer using as substrate and the second semi-conducting material with drain region, because the semi-conducting material using as substrate is monocrystalline, therefore source region and drain region be also monocrystalline, can solve like this problem that affects device performance that prior art use polysilicon produces as source region and drain region.
For those skilled in the art be can better understand the present invention, below in conjunction with accompanying drawing, describe the specific embodiment of the present invention in detail.
Fig. 2 is the flow chart of method of the accurate soi structure of formation of the specific embodiment of the present invention, ginseng figure Fig. 2, and the method for the accurate soi structure of formation of the specific embodiment of the invention comprises:
Step S21, provides substrate, and described substrate comprises the first semiconductor layer, is positioned at the first insulating barrier on described the first semiconductor layer, is positioned at the second semiconductor layer on described the first insulating barrier;
Step S22, graphical described the first insulating barrier and described the second semiconductor layer, form opening, exposes described the first semiconductor layer;
Step S23, forms the side wall of predetermined altitude at the sidewall of described opening, and in described opening, forms the first semi-conducting material of described predetermined altitude;
Step S24 forms the second semi-conducting material in described opening, cover described side wall and described the first semi-conducting material, and the surface of described the second semi-conducting material is equal with the surface of described the second semiconductor layer.
The cross-sectional view of the method for the accurate soi structure of formation that Fig. 3 a～Fig. 3 g is the specific embodiment of the invention, in order to make those skilled in the art can better understand the present invention the method for the accurate soi structure of formation of embodiment, below in conjunction with specific embodiment combination, referring to figs. 2 and 3 a～Fig. 3 g, describe the method for the accurate soi structure of formation of the specific embodiment of the invention in detail.
In conjunction with referring to figs. 2 and 3 a, perform step S21, substrate 30 is provided, described substrate 30 comprises the first semiconductor layer 31, is positioned at the first insulating barrier 32 on described the first semiconductor layer 31, is positioned at the second semiconductor layer 33 on described the first insulating barrier 32.In the present invention, the material of described the first semiconductor layer 31 can be monocrystalline silicon or single-crystal silicon Germanium, or monocrystalline carbon doped silicon; Or the material that can also comprise other, such as III-V compounds of group such as GaAs.The material of the second semiconductor layer 33 can be monocrystalline silicon or single-crystal silicon Germanium, or monocrystalline carbon doped silicon; Or the material that can also comprise other, such as III-V compounds of group such as GaAs.In the specific embodiment of the invention, described the first semiconductor layer 31 and described the second semiconductor layer 33 are all selected monocrystalline silicon, and the indices of crystallographic plane are (100), (110) or (111).In the present invention, the thickness of the first insulating barrier 32 is 100 dust～2000 dusts, and in the specific embodiment of the invention, the first insulating barrier 32 is silica.
In conjunction with referring to figs. 2 and 3 c, perform step S22, graphical described the first insulating barrier 32 and described the second semiconductor layer 33, form opening 35, exposes described the first semiconductor layer 31.In the specific embodiment of the invention, form graphical described the first insulating barrier 32 and described the second semiconductor layer 33, form opening 35, expose described the first semiconductor layer 31, be specially: with reference to figure 3b, on described the second semiconductor layer 33, form patterned hard mask layer 34.With reference to figure 3c, the described patterned hard mask layer 34 of take is mask, and the first insulating barrier 32 and described the second semiconductor layer 33 described in etching form opening 35.Below, the method for the formation opening 35 of the detailed description specific embodiment of the invention:
With reference to figure 3b, on described the second semiconductor layer 33, form hard mask layer 34, in the specific embodiment of the invention, hard mask layer 34 comprises: silicon oxide layer 341 and silicon nitride layer 342, described silicon oxide layer 341 is positioned on described the second semiconductor layer 33, and described silicon nitride layer 342 is positioned on described silicon oxide layer 341.Wherein, silicon oxide layer 341 is as the stress-buffer layer between silicon nitride layer 342 and the second semiconductor layer 33.In other embodiments, hard mask layer can be also single layer structure.On hard mask layer 34, form photoresist layer, on silicon nitride layer 342, form photoresist layer, the method that forms photoresist layer can be spin-coating method, drop-coating or spread coating, utilizes spin-coating method to form photoresist layer in the specific embodiment of the invention.Afterwards, photoresist layer is exposed, developed, form patterned photoresist layer, define the figure of opening; Then, utilize and take patterned photoresist layer as mask etching hard mask layer 34, the figure on patterned photoresist layer is transferred to hard mask layer 34, form patterned hard mask layer 34.
With reference to figure 3c, the described patterned hard mask layer 34 of take is mask, and the first insulating barrier 32 and described the second semiconductor layer 33 described in etching form opening 35.In the specific embodiment of the invention, use the first insulating barrier 32 and described the second semiconductor layer 33 described in dry etching, form opening 35.
In conjunction with referring to figs. 2 and 3 e, execution step S23, forms the side wall 36 of predetermined altitude at the sidewall of described opening 35, and at the first semi-conducting material 37 of the described predetermined altitude of the interior formation of described opening 35.In the specific embodiment of the invention, predetermined altitude is 50nm～300nm.In the specific embodiment of the invention, at the sidewall of described opening 35, form the side wall 36 of predetermined altitude, and comprise at the first semi-conducting material 37 of the described predetermined altitude of the interior formation of described opening 35: with reference to figure 3d, form the second insulating barrier, cover the surface of described patterned hard mask layer 34, bottom and the sidewall of described opening 35; Return to carve remove the surface of described patterned hard mask layer and the second insulating barrier of open bottom, the sidewall of described opening form side wall 36 '.With reference to figure 3e, at the first semi-conducting material 37 of the interior formation predetermined altitude of described opening 35; Remove the second insulating barrier not covered by described the first semi-conducting material 37, form the side wall 36 of predetermined altitude.Be specially:
With reference to figure 3d, form the second insulating barrier, cover the surface of described patterned hard mask layer 34, bottom and the sidewall of described opening 35.In the specific embodiment of the invention, the material of described the second insulating barrier is silica, and the method that forms silica is thermal oxidation or plasma enhanced chemical vapor deposition.And in the specific embodiment of the invention, the thickness of described the second insulating barrier is 10 dust～200 dusts.Return to carve and remove the surface of described patterned hard mask layer 34 and the second insulating barrier of opening 35 bottoms, the sidewall of described opening 35 form side wall 36 ', because the material of the second insulating barrier is silica, side wall 36 ' form after carving for the second insulating barrier is returned, therefore side wall 36 ' material be also silica, and its thickness is 10 dust～200 dusts.
With reference to figure 3e, at the first semi-conducting material 37 of the interior formation predetermined altitude of described opening 35.In the present invention, utilize epitaxial growth method at the first semi-conducting material 37 of the interior formation predetermined altitude of described opening 35.And in the present invention, epitaxial growth method is selected from: rapid heat chemical vapour deposition, high vacuum chemical vapour deposition, molecular beam epitaxy.In the specific embodiment of the invention, adopt the vertical epitaxial growth method growth regulation semiconductor material 37 in epitaxial growth method, that is to say, along the direction growth regulation semiconductor material 37 of vertical openings 35 bottoms.The first semi-conducting material 37 can be monocrystalline silicon or single-crystal silicon Germanium, or monocrystalline carbon doped silicon; Or the material that can also comprise other, such as III-V compounds of group such as GaAs.In the specific embodiment of the invention, the first semi-conducting material 37 can be monocrystalline silicon, utilizes rapid heat chemical CVD (Chemical Vapor Deposition) method at the first semi-conducting material 37 of the interior formation predetermined altitude of described opening 35.Form after the first semi-conducting material 37 of predetermined altitude, remove the second insulating barrier not covered by described the first semi-conducting material 37, form the side wall 36 of predetermined altitude, in the specific embodiment of the invention, utilize wet etching (for example hydrofluoric acid) to remove the second insulating barrier not covered by described the first semi-conducting material 37; Before removing the second insulating barrier not covered by described the first semi-conducting material 37, first need other structures outside the second insulating barrier to utilize mask or photoresist to protect.In other embodiments of the invention, also can utilize dry etching to remove the second insulating barrier not covered by described the first semi-conducting material 37.
In conjunction with referring to figs. 2 and 3 f, execution step S24, at interior formation the second semi-conducting material 38 of described opening 35, cover described side wall 36 and described the first semi-conducting material 37, and the surface of described the second semi-conducting material 38 is equal with the surface of described the second semiconductor layer 33.In the present invention, utilize epitaxial growth method at interior formation the second semi-conducting material 38 of described opening 35.And in the present invention, described epitaxial growth method is selected from: rapid heat chemical vapour deposition, high vacuum chemical vapour deposition, molecular beam epitaxy.In the specific embodiment of the invention, adopt the horizontal epitaxial growth method in epitaxial growth method to generate the second semi-conducting material 38.The direction of growth along continuous straight runs of semi-conducting material 38, namely along the surface direction of the first semi-conducting material 37, semi-conducting material 38 is very slow in the speed of growth of vertical-horizontal direction, namely the speed of growth of the surface direction of vertical the first semi-conducting material is very slow, the ratio of the speed of growth of horizontal direction and vertical-horizontal direction is 1: 0～1: 0.2, in the specific embodiment of the invention, preferably 1: 0～1: 0.1.The second semi-conducting material 38 can be monocrystalline silicon or single-crystal silicon Germanium, or monocrystalline carbon doped silicon; Or the material that can also comprise other, such as III-V compounds of group such as GaAs.In the specific embodiment of the invention, the second semi-conducting material 38 is all selected monocrystalline silicon, utilizes rapid heat chemical CVD (Chemical Vapor Deposition) method at monocrystalline silicon second semi-conducting material 38 of the interior formation predetermined altitude of described opening 35.
Afterwards, with reference to figure 3g, and in conjunction with reference to figure 3f, remove hard mask layer, form accurate soi structure.In the specific embodiment of the invention, utilize wet etching to remove hard mask layer 34, utilize wet etching to remove silicon oxide layer 341 and silicon nitride layer 342.
In the specific embodiment of the invention, form after the accurate soi structure shown in Fig. 3 g, continuation forms grid structure in this structure, with reference to figure 3h, be specially: on the surface forming at described the second semiconductor layer 33 and the second semi-conducting material 38, form grid structure, described grid structure comprises: the gate dielectric layer 42 between grid 41, the surface that forms at grid 41 and described the second semiconductor layer 33 and the second semi-conducting material 38 and be positioned at described grid 41 and gate dielectric layer 42 side wall 43 around; Take described grid structure as mask, carry out Implantation, in the substrate of described grid structure both sides, form source region and drain region (not shown).In the specific embodiment of the invention, form behind source region, drain region, can carry out annealing process, the temperature in annealing process is less than 600 ℃.
Complete after above processing step, can continue to form contact hole and interconnection line.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (17)
1. form a method for accurate soi structure, it is characterized in that, comprising:
Substrate is provided, and described substrate comprises the first semiconductor layer, is positioned at the first insulating barrier on described the first semiconductor layer, is positioned at the second semiconductor layer on described insulating barrier;
Before forming grid structure, graphical described the first insulating barrier and described the second semiconductor layer, form opening, exposes described the first semiconductor layer; The position of described opening is corresponding in the direction of the upper surface of vertical the first semiconductor layer with the position of described grid structure;
At the sidewall of described opening, form the side wall of predetermined altitude, and in described opening, form the first semi-conducting material of described predetermined altitude;
In described opening, form the second semi-conducting material, cover described side wall and described the first semi-conducting material, and the surface of described the second semi-conducting material is equal with the surface of described the second semiconductor layer.
2. the method for the accurate soi structure of formation as claimed in claim 1, is characterized in that, also comprises:
On the surface forming at described the second semi-conducting material and the second semiconductor layer, form grid structure, described grid structure comprises: the gate dielectric layer between grid, the surface that forms at grid and described the second semi-conducting material and the second semiconductor layer and be positioned at described grid and gate dielectric layer side wall around;
Take described grid structure as mask, carry out Implantation, in the substrate of described grid structure both sides, form source region and drain region.
3. the method for the accurate soi structure of formation as claimed in claim 1 or 2, is characterized in that, described graphical described the first insulating barrier and described the second semiconductor layer form opening at described substrate, expose described the first semiconductor layer and comprise:
On described the second semiconductor layer, form patterned hard mask layer;
The described patterned hard mask layer of take is mask, and the first insulating barrier and described the first semiconductor layer described in etching form opening.
4. the method for the accurate soi structure of formation as claimed in claim 3, is characterized in that, described hard mask layer comprises: silicon oxide layer and silicon nitride layer, and described silicon oxide layer is positioned on described the second semiconductor layer, and described silicon nitride layer is positioned on described silicon oxide layer.
5. the method for the accurate soi structure of formation as claimed in claim 3, is characterized in that, forms the side wall of predetermined altitude at the sidewall of described opening, and the first semi-conducting material that forms described predetermined altitude in described opening comprises:
Form the second insulating barrier, cover the surface of described patterned hard mask layer, the bottom of described opening and sidewall;
Return to carve and remove the surface of described patterned hard mask layer and the second insulating barrier of open bottom, at the sidewall formation side wall of described opening;
In described opening, form the first semi-conducting material of predetermined altitude;
Remove the second insulating barrier not covered by described the first semi-conducting material, form the side wall of predetermined altitude.
6. the method for the accurate soi structure of formation as claimed in claim 5, is characterized in that, utilizes epitaxial growth method in described opening, to form the first semi-conducting material of predetermined altitude.
7. the method for the accurate soi structure of formation as claimed in claim 1, is characterized in that, utilizes epitaxial growth method in described opening, to form the second semi-conducting material.
8. the method for the accurate soi structure of formation as claimed in claim 6, is characterized in that, described epitaxial growth method is selected from: rapid heat chemical vapour deposition, high vacuum chemical vapour deposition, molecular beam epitaxy.
9. the method for the accurate soi structure of formation as claimed in claim 7, is characterized in that, described epitaxial growth method is selected from: rapid heat chemical vapour deposition, high vacuum chemical vapour deposition, molecular beam epitaxy.
10. the method for the accurate soi structure of formation as claimed in claim 5, is characterized in that, the material of described the second insulating barrier is silica.
The method of the accurate soi structure of 11. formation as claimed in claim 9, is characterized in that, the method for described formation silica is thermal oxidation or plasma enhanced chemical vapor deposition.
The method of the accurate soi structure of 12. formation as claimed in claim 5, is characterized in that, the thickness of described the second insulating barrier is 10 dust～200 dusts.
The method of the accurate soi structure of 13. formation as claimed in claim 10, is characterized in that, the thickness of described the second insulating barrier is 10 dust～200 dusts.
The method of the accurate soi structure of 14. formation as claimed in claim 1 or 2, is characterized in that, the thickness of described the first insulating barrier is 100 dust～2000 dusts.
The method of the accurate soi structure of 15. formation as claimed in claim 1 or 2, is characterized in that, described the first semiconductor layer, the second semiconductor layer, the first semi-conducting material and the second semi-conducting material are selected from monocrystalline silicon, monocrystalline carbon doped silicon or monocrystalline germanium silicon.
The method of the accurate soi structure of 16. formation as claimed in claim 15, is characterized in that, described the first semiconductor layer and described the second semiconductor layer are monocrystalline silicon, and the indices of crystallographic plane of described monocrystalline silicon are (100), (110) or (111).
The method of the accurate soi structure of 17. formation as claimed in claim 1 or 2, is characterized in that, described predetermined altitude is 50nm～300nm.
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