CN105826233B - SOI device and preparation method thereof - Google Patents
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Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to an SOI device and a preparation method thereof.A buried oxide layer is formed in an SOI substrate through a silicon epitaxial growth process and a thermal oxidation process, and the thickness of the buried oxide layer positioned below a channel region is less than that of the buried oxide layer positioned below a source region and/or a drain region; the SOI device has high soft error resistance, and the performance of the device can be adjusted by applying a body region bias effect, so that the performance of the device is further improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an SOI (silicon on insulator) device and a preparation method thereof.
Background
SOI (silicon-on-insulator) refers to silicon on an insulating layer, which is composed of three layers of "silicon thin film/insulating layer/silicon substrate". The uppermost silicon film (silicon film for short) is used for semiconductor devices such as CMOS and the like, and the intermediate insulating buried layer (silicon dioxide, buried oxide layer for short, and BOX layer for short) is used for isolating the devices from the silicon substrate.
Compared with a bulk silicon device, the SOI device has the characteristics of small parasitic capacitance, low leakage, low probability of soft error occurrence and the like, so the SOI device is more and more widely applied in the field of semiconductors.
Therefore, how to compromise the body bias effect and soft error resistance of the device becomes the direction of research for those skilled in the art.
Disclosure of Invention
Aiming at the existing problems, the invention discloses an SOI device and a preparation method thereof, aiming at overcoming the problem that the performance of the device is difficult to adjust by applying a body region bias effect because a buried oxide layer in the SOI device is thicker in the prior art.
In order to achieve the above object, the present application describes an SOI device, including:
an SOI substrate;
a buried oxide layer embedded in the SOI substrate;
a source region and a drain region disposed in the SOI substrate above the buried oxide layer;
a channel region disposed in the substrate between the source region and the drain region;
wherein the thickness of the buried oxide layer under the channel region is smaller than the thickness of the buried oxide layer under the source region and/or the drain region.
The above SOI device, wherein the SOI device further comprises:
and the gate stack structure covers the upper surface of the SOI substrate positioned in the channel region.
The SOI device described above, wherein the gate stack structure comprises:
the grid structure covers the upper surface of the SOI substrate positioned in the channel region;
and the side wall covers the side wall of the grid structure.
The above SOI device, wherein the gate structure comprises:
the gate oxide layer covers the upper surface of the SOI substrate positioned in the channel region;
the grid electrode covers the upper surface of the grid oxide layer;
the side walls cover the side walls of the grid electrode and the side walls of the grid oxide layer.
The application also describes a preparation method of the SOI device, wherein the preparation method comprises the following steps:
providing a semiconductor structure comprising a first silicon layer, a first oxide layer and a second silicon layer, wherein a through hole is formed in the first oxide layer, the first oxide layer is arranged on the first silicon layer, and part of the surface of the first silicon layer is exposed through the through hole; the second silicon layer is filled in the through hole and covers the upper surface of the first oxide layer, and a groove is further formed in the second silicon layer above the through hole;
carrying out thermal oxidation process on the semiconductor structure to form a second oxide layer on the bottom of the groove and the side wall of the groove;
removing the second oxide layer on the side wall of the groove, and reserving the second oxide layer at the bottom of the groove to connect the first oxide layers on two sides of the through hole to form a buried oxide layer;
filling a third silicon layer in the groove to connect the second silicon layers positioned at two sides of the groove to form an SOI substrate;
continuing to prepare a gate stack structure on the SOI substrate which is positioned right above the through hole, and forming a source region, a drain region and a channel region between the source region and the drain region of the gate stack structure in the SOI substrate;
wherein the thickness of the second oxide layer remaining at the bottom of the recess is less than the thickness of the first oxide layer.
The above method for manufacturing an SOI device, wherein the step of forming the semiconductor structure comprises:
sequentially forming a first oxide material layer and a first nitride material layer on the surface of the first silicon layer from bottom to top, and etching the first nitride material layer back to the upper surface of the first silicon layer to form an opening, wherein the opening is in an I-shaped structure with a thin middle and two thick sides, and the remaining first oxide material layer forms a first oxide layer provided with the through hole;
performing a silicon epitaxial growth process to form a first silicon material layer with the same thickness as the first oxide layer at the bottom of the opening, and performing a silicon germanium epitaxial growth process to form a silicon germanium layer on the surface of the first silicon material layer;
continuing to deposit a second oxide material layer to fill the opening, and removing the remaining first nitride material layer;
partially etching the silicon germanium layer to remove the silicon germanium layer positioned in the middle of the I-shaped structure, and performing a silicon epitaxial growth process to form a second silicon material layer;
after removing the second oxide material layer, forming the semiconductor structure;
wherein the first silicon material layer and the second silicon material layer constitute the second silicon layer.
In the preparation method of the SOI device, the silicon germanium layer is partially etched by adopting an isotropic etching process to remove the silicon germanium layer located in the middle of the i-shaped structure.
In the above method for manufacturing an SOI device, the step of removing the second oxide layer on the sidewall of the groove and leaving the second oxide layer at the bottom of the groove to connect the first oxide layers at two sides of the through hole to form a buried oxide layer specifically includes:
depositing a second nitride material layer until the groove is filled, and then carrying out a planarization process to expose the upper surface of the second silicon material layer;
continuing to perform a thermal oxidation process to form a third oxide layer to cover the exposed upper surface of the second silicon material layer;
and removing the second silicon nitride material layer, partially removing the second oxide layer and the third oxide layer to expose partial side walls of the grooves and partial surfaces of the second silicon material layer, and connecting the reserved second oxide layer with the first oxide layer positioned on two sides of the through hole to form the buried oxide layer.
In the above method for manufacturing an SOI device, the second oxide layer and the third oxide layer are partially removed by an isotropic etching process to expose a portion of the sidewall of the recess and a portion of the surface of the second silicon material layer.
In the above method for manufacturing an SOI device, the step of filling the groove with the third silicon layer to connect the second silicon layers located at two sides of the groove to form the SOI substrate specifically includes:
performing a silicon epitaxial growth process to form a third silicon material layer filling the groove;
and carrying out a planarization process on the third silicon material layer to form the third silicon layer, wherein the third silicon layer is connected with the second silicon layers positioned at two sides of the groove to form the SOI substrate.
The preparation method of the SOI device, wherein the gate stack structure includes:
the grid structure covers the upper surface of the SOI substrate right above the through hole;
and the side wall covers the side wall of the grid structure.
The above method for manufacturing an SOI device, wherein the gate structure comprises:
the gate oxide layer covers the upper surface of the SOI substrate right above the through hole;
the grid electrode covers the upper surface of the grid oxide layer;
the side walls cover the side walls of the grid electrode and the side walls of the grid oxide layer.
The invention has the following advantages or beneficial effects:
the invention discloses an SOI device and a preparation method thereof.A buried oxide layer is formed in an SOI substrate through a silicon epitaxial growth process and a thermal oxidation process, and the thickness of the buried oxide layer positioned below a channel region is less than that of the buried oxide layer positioned below a source region and/or a drain region; the SOI device has high soft error resistance, and the performance of the device can be adjusted by applying a body region bias effect, so that the performance of the device is further improved.
Description of the specific figures
The invention and its features, aspects and advantages will become more apparent from reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Like reference symbols in the various drawings indicate like elements. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
FIG. 1 is a schematic structural diagram of an SOI device in an embodiment of the present invention;
fig. 2a-2q are flow charts of methods of fabricating SOI devices in embodiments of the present invention.
Detailed Description
The invention will be further described with reference to the following drawings and specific examples, which are not intended to limit the invention thereto.
As shown in fig. 1, the present embodiment relates to an SOI device including: an SOI substrate 201; a buried oxide layer 202 embedded in the SOI substrate 201; a source region 2031 and a drain region 2032 (the source region and the drain region in the embodiment of the present invention may be interchanged) are provided in the SOI substrate above the buried oxide layer 202; and a channel region 207 between the source region 2031 and the drain region 2032; wherein the thickness of the buried oxide layer 202 under the channel region 207 is smaller than the thickness of the buried oxide layer 202 under the source region 2031 and/or the drain region 2032; specifically, the buried oxide layer 202 includes a first portion 2021 directly under the channel region 207 and a second portion 2022 directly under the source region 2031 and/or the drain region 2032, and the thickness of the first portion 2021 is smaller than that of the second portion 2022.
In the embodiment of the present invention, the SOI device further includes a gate stack structure covering the upper surface of the SOI substrate 201 located in the channel region 207, where the gate stack structure includes a gate structure covering the upper surface of the SOI substrate 201 located in the channel region 207 and a sidewall 206 covering a sidewall of the gate structure; further the gate structure comprises a gate oxide layer 204 covering the upper surface of the SOI substrate 201 in the channel region 207 and a gate 205 covering the upper surface of the gate oxide layer 204, wherein the sidewall covers the sidewall of the gate 205 and the sidewall of the gate oxide layer 204.
Preferably, the gate 205 is made of polysilicon, and the gate oxide layer 204 is made of silicon dioxide.
Meanwhile, the invention also provides a preparation method of the SOI device, which specifically comprises the following steps as shown in FIGS. 2a-2 q:
in step S1, a first silicon layer 101 is provided, as shown in fig. 2 a.
Step S2, sequentially forming a first oxide material layer and a first nitride material layer covering the first oxide material layer on the surface of the first silicon layer 101 from bottom to top, and etching back the first oxide material layer to the upper surface of the first silicon layer 101 by using a dry etching process to form an i-shaped opening with a thin middle and thick two sides, where the opening penetrates through the remaining first nitride material layer 103 and the remaining first oxide material layer 102, in an embodiment of the present invention, the first oxide material layer is made of silicon oxide (such as silicon dioxide), and the first nitride material layer is made of silicon nitride; the structure shown in fig. 2b (1) and 2b (2), wherein fig. 2b (1) is a top view of the structure after the opening is formed, and fig. 2b (2) is a cross-sectional view at a-a in fig. 2b (1).
In step S3, a silicon epitaxial growth process is performed to form a first silicon material layer 104 at the bottom of the opening, and the thickness of the first silicon material layer 104 is consistent with the thickness of the remaining first oxide material layer 102, that is, the first silicon material layer 104 penetrates through the remaining first oxide material layer 102, and the upper surface of the first silicon material layer 104 is flush with the upper surface of the first oxide material layer 102, and the lower surface is flush with the lower surface of the remaining first oxide material layer 102, and the first silicon material layer 104 just fills the via hole left after the etching of the first oxide material layer in step S2, so that it is easy to know that the opening includes the via hole, as shown in fig. 2 c.
Step S4, continuing the sige epitaxial growth process, forming a sige layer 105 on the surface of the first silicon material layer 104, wherein the first silicon material layer 104 and the sige layer 105 only cover a portion of the opening, and forming the sige layer 105 on the surface of the second silicon layer 104 by using the sige epitaxial growth process is a technique well known to those skilled in the art and will not be described herein again, as shown in fig. 2 d.
Step S5, continue to deposit the second oxide material layer until the opening is filled, at this time, a part of the second oxide material layer covers the upper surface of the remaining first nitride material layer 103 located at both sides of the opening, and after performing a planarization process on the second oxide material layer to remove the second oxide material layer located above the remaining first nitride material layer 103, form a second oxide material layer 106 covering the surface of the silicon germanium layer 105 and having an upper surface flush with the upper surface of the remaining first nitride material layer 103, preferably, the second oxide material layer 106 is made of silicon oxide (such as silicon dioxide), as shown in fig. 2 e.
In step S6, the remaining first nitride material layer 103 is removed, and preferably, the remaining first nitride material layer 103 is removed by a dry etching process, such as the structure shown in fig. 2 f.
Step S7, using an isotropic etching process to remove the sige layer 105 until the sige layer 105 located in the middle portion of the i-shaped structure opening is completely removed, as can be seen from steps S1-S7, the middle of the sige layer 105 is thin and thick, so that, after the sige layer 105 located in the middle portion of the i-shaped structure opening is removed, the sige layer 105 located in the two side portions of the i-shaped structure opening still remains partially to support the second oxide material layer 106, such as the structure shown in fig. 2g (1) -2g (3), wherein fig. 2g (1) is a top view after the partial sige layer 105 is removed, fig. 2g (2) is a cross-sectional view at a-a of fig. 2g (1), and fig. 2g (3) is a cross-sectional view at B-B of fig. 2g (1).
Step S8, continuing the silicon epitaxial growth process to form a second silicon material layer 107, where the second silicon material layer 107 fills the original position where the remaining first nitride layer 103 is located and the position where the etched portion of the silicon germanium layer 105 is located, as shown in fig. 2 h.
Step S9, removing the second oxide material layer 106 by using a dry etching process, and forming a groove in the second silicon material layer 107 at the position of the original second oxide material layer 106; the second silicon material layer 107 with the groove and the first silicon material layer 104 constitute a second silicon layer; and the first silicon layer 101, the remaining first oxide material layer 102 with the via holes (hereinafter referred to as the first oxide layer 102), and the second silicon layer filling the via holes and covering the surface of the first oxide layer 102 form a semiconductor structure, which may also be formed by other processes in the present invention, and is not limited to the above-described manner, such as the structure shown in fig. 2 i.
In step S10, a first thermal oxidation process is performed to form a second oxide layer 108 on the bottom of the trench and the sidewall thereof, and the second oxide layer 108 is in contact with the first oxide layer 102, since the second oxide layer 108 is formed by the thermal oxidation process, the second oxide layer 108 is made of silicon oxide, as shown in fig. 2 j.
In step S11, after depositing the second nitride material layer 109 to fill the recess, a planarization process is performed to polish and remove the second oxide layer 108 on the upper surface including the second silicon material layer 107, so as to expose the upper surface of the second silicon material layer 107, preferably, the second nitride material layer 109 is made of silicon nitride, as shown in fig. 2 k.
In step S12, a second thermal oxidation process is performed to form a third oxide layer 110 to cover the exposed upper surface of the second silicon material layer 107, wherein the third oxide layer 110 is formed by a thermal oxidation process, so the material of the third oxide layer 110 is silicon dioxide, as shown in fig. 2 l.
Step S13, removing the second nitride material layer 109 by a dry etching process, and partially removing the third oxide layer 110 and the remaining second oxide layer 108 ' by an isotropic etching process to expose a portion of the surface of the second silicon material layer 107, wherein the thickness of the remaining second oxide layer 108 "is smaller than that of the first oxide layer 102, in the actual process, while removing the second nitride material layer 109, the third oxide layer 110 and the remaining second oxide layer 108 ' are also partially removed, and then partially removing the third oxide layer 110 and the remaining second oxide layer 108 ' by an isotropic etching process according to the process requirements, so that the thickness of the remaining second oxide layer 108" is smaller than that of the first oxide layer 102, and the thickness difference satisfies the process requirements, thereby providing a higher soft error resistance, and the device performance can be adjusted by applying the body region bias effect to further improve the device performance, in the present invention, other processes may be adopted as long as the thickness of the second oxide layer retained at the bottom of the groove is smaller than the thickness of the first oxide layer, which is not limited to the manner adopted in this embodiment, such as the structure shown in fig. 2 m.
Step S14, carrying out silicon epitaxial growth process to form a third silicon material layer filling the groove; performing a planarization process on the third silicon material layer to form a third silicon layer 111, wherein the third silicon layer 111 is connected with the second silicon layers positioned at two sides of the groove to form an SOI substrate, the first oxide layer 102 and the remaining second oxide layer 108 "(i.e., the second oxide layer remaining at the bottom of the groove) form a buried oxide layer, and the first silicon layer 101, the remaining second silicon layer (including the remaining first silicon material layer 104 and the second silicon material layer 107), the third silicon layer 111 and the buried oxide layer form an SOI substrate; in the embodiment of the present invention, while performing the planarization process on the third silicon material layer, the remaining third oxide layer 110 'may be completely removed, and since the remaining third oxide layer 110' is already very thin, the remaining third oxide layer 110 'may also be removed in the subsequent process of forming the source and drain, for better clarity of describing the steps of the present invention, in this embodiment, the remaining third oxide layer 110' is removed in this step, such as the structure shown in fig. 2 n.
Step S15, continuing to prepare a gate oxide layer 112 and a gate 113 covering the upper surface of the gate oxide layer on the SOI substrate right above the through hole, wherein the gate oxide layer 112 and the gate 113 form a gate structure covering the upper surface of the SOI substrate right above the through hole; preferably, the gate oxide layer 112 is made of silicon dioxide, and the gate electrode 113 is made of polysilicon, as shown in fig. 2 o.
In step S16, an LDD process is performed to form lightly doped drains in the SOI substrate on both sides of the gate structure, as shown in fig. 2 p.
Step S17, after forming a sidewall 114 covering the sidewall of the gate structure (the sidewall 114 covers the sidewall of the gate 113 and the sidewall of the gate oxide layer 112), continuing to form a source/drain process to form a source region 1151 and a drain region 1152 (the source region and the drain region in the embodiment of the present invention may be interchanged) on the SOI substrate located on both sides of the gate structure, and both the source region 1151 and the drain region 1152 are in contact with a buried oxide layer, wherein a channel region 116 is formed between the source region 1151 and the drain region 1152, further, the remaining second oxide layer 108 "in the buried oxide layer is located right below the channel region, and the first oxide layer 102 in the buried oxide layer is located right below the source/drain region 115, as shown in fig. 2 q.
It should be understood that this embodiment is an embodiment of a method corresponding to an embodiment of an SOI device, and that this embodiment may be implemented in cooperation with the above-described embodiments of an SOI device. The related technical details mentioned in the above embodiments of the SOI device are still valid in this embodiment, and are not described herein again for the sake of reducing redundancy. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the above-described embodiments of the SOI device.
In summary, the present invention discloses an SOI device and a method for fabricating the same, wherein a buried oxide layer is formed in an SOI substrate through a silicon epitaxial growth process and a thermal oxidation process, and the thickness of the buried oxide layer under a channel region is smaller than the thickness of the buried oxide layer under a source region and/or a drain region; the SOI device has high soft error resistance, and the performance of the device can be adjusted by applying a body region bias effect, so that the performance of the device is further improved.
Those skilled in the art will appreciate that those skilled in the art can implement the modifications in combination with the prior art and the above embodiments, and the details are not described herein. Such variations do not affect the essence of the present invention and are not described herein.
The above description is of the preferred embodiment of the invention. It is to be understood that the invention is not limited to the particular embodiments described above, in that devices and structures not described in detail are understood to be implemented in a manner common in the art; those skilled in the art can make many possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments to equivalent variations, without departing from the spirit of the invention, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (7)
1. A method for manufacturing an SOI device, comprising the steps of:
providing a semiconductor structure comprising a first silicon layer, a first oxide layer and a second silicon layer, wherein a through hole is formed in the first oxide layer, the first oxide layer is arranged on the first silicon layer, and part of the surface of the first silicon layer is exposed through the through hole; the second silicon layer is filled in the through hole and covers the upper surface of the first oxide layer, and a groove is further formed in the second silicon layer above the through hole;
carrying out thermal oxidation process on the semiconductor structure to form a second oxide layer on the bottom of the groove and the side wall of the groove;
removing the second oxide layer on the side wall of the groove, and reserving the second oxide layer at the bottom of the groove to connect the first oxide layers on two sides of the through hole to form a buried oxide layer;
filling a third silicon layer in the groove to connect the second silicon layers positioned at two sides of the groove to form an SOI substrate;
continuing to prepare a gate stack structure on the SOI substrate which is positioned right above the through hole, and forming a source region, a drain region and a channel region between the source region and the drain region of the gate stack structure in the SOI substrate;
wherein the thickness of the second oxide layer remained at the bottom of the groove is smaller than that of the first oxide layer;
the step of forming the semiconductor structure comprises:
sequentially forming a first oxide material layer and a first nitride material layer on the surface of the first silicon layer from bottom to top, and etching the first nitride material layer back to the upper surface of the first silicon layer to form an opening, wherein the opening is in an I-shaped structure with a thin middle and two thick sides, and the remaining first oxide material layer forms a first oxide layer provided with the through hole;
performing a silicon epitaxial growth process to form a first silicon material layer with the same thickness as the first oxide layer at the bottom of the opening, and performing a silicon germanium epitaxial growth process to form a silicon germanium layer on the surface of the first silicon material layer;
continuing to deposit a second oxide material layer to fill the opening, and removing the remaining first nitride material layer;
partially etching the silicon germanium layer to remove the silicon germanium layer positioned in the middle of the I-shaped structure, and performing a silicon epitaxial growth process to form a second silicon material layer;
after removing the second oxide material layer, forming the semiconductor structure;
wherein the first silicon material layer and the second silicon material layer constitute the second silicon layer.
2. The method of fabricating an SOI device of claim 1 wherein the silicon germanium layer is partially etched using an isotropic etch process to remove the silicon germanium layer in the middle of the i-shaped structure.
3. The method for manufacturing an SOI device according to claim 1, wherein the step of removing the second oxide layer on the sidewall of the recess and leaving the second oxide layer at the bottom of the recess to connect the first oxide layers on both sides of the via hole to form a buried oxide layer is embodied as:
depositing a second nitride material layer until the groove is filled, and then carrying out a planarization process to expose the upper surface of the second silicon material layer;
continuing to perform a thermal oxidation process to form a third oxide layer to cover the exposed upper surface of the second silicon material layer;
and removing the second silicon nitride material layer, partially removing the second oxide layer and the third oxide layer to expose partial side walls of the grooves and partial surfaces of the second silicon material layer, and connecting the reserved second oxide layer with the first oxide layer positioned on two sides of the through hole to form the buried oxide layer.
4. The method of fabricating an SOI device of claim 3 wherein the second oxide layer and the third oxide layer are partially removed using an isotropic etch process to expose portions of the sidewalls of the recess and portions of the surface of the second silicon material layer.
5. The method for manufacturing an SOI device according to claim 1, wherein the step of filling the recess with a third silicon layer to connect the second silicon layers located at both sides of the recess to form an SOI substrate is specifically:
performing a silicon epitaxial growth process to form a third silicon material layer filling the groove;
and carrying out a planarization process on the third silicon material layer to form the third silicon layer, wherein the third silicon layer is connected with the second silicon layers positioned at two sides of the groove to form the SOI substrate.
6. The method of fabricating an SOI device of claim 1 wherein the gate stack structure comprises:
the grid structure covers the upper surface of the SOI substrate right above the through hole;
and the side wall covers the side wall of the grid structure.
7. The method of fabricating an SOI device of claim 6 wherein the gate structure comprises:
the gate oxide layer covers the upper surface of the SOI substrate right above the through hole;
the grid electrode covers the upper surface of the grid oxide layer;
the side walls cover the side walls of the grid electrode and the side walls of the grid oxide layer.
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| CN102487033B (en) * | 2010-12-03 | 2014-04-02 | 中芯国际集成电路制造(北京)有限公司 | Method for forming standard SOI (Silicon On Insulator) structure |
| CN102214694B (en) * | 2011-05-30 | 2013-05-08 | 西安电子科技大学 | Heterogeneous metal stacked grid strained silicon-germanium on insulator p-channel metal oxide semiconductor field effect tube (SSGOI pMOSFET) device structure |
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