CN102306213B - Anti-single particle irradiating method and anti-single particle irradiating system based on frame data processing - Google Patents

Abstract

The invention discloses an anti-single-particle irradiation method and an anti-single-particle irradiation system based on frame data processing, which mainly solves the problem that the existing frame data processing system has a function error caused by single-particle irradiation. The anti-single particle radiation system includes a single frame detection and reset module, and a frame data processor. The single frame detection and reset module resets the frame data processor. The frame data processor includes: a finite state machine assembly unit, a controller protection error correction unit, a memory, a memory protection error correction unit, a data input interface, a data output interface and a configuration module, the finite state machine assembly unit processes each frame data, and the controller The protection error correction unit protects the finite state machine assembly unit, the memory protection error correction unit protects memory data, and the configuration module stores parameter information required by the frame data processor. The invention has the advantages of simple implementation, anti-single particle radiation and the like, and can be used in image compression systems and other error correction and modulation circuits based on frames or groups in space environments.

Description

Anti-single event irradiation method and anti-single event irradiation system based on frame data processing

technical field

The invention relates to the field of communication technology, and relates to a design method and system for anti-single-event radiation, which is used in image compression systems under space environment and single-event radiation, or other error correction and modulation circuits based on frames or groups.

Background technique

As mankind enters the information age, especially in the last ten years, multimedia signal processing technology and communication technology have developed rapidly. The integration between the two is unstoppable, ranging from information highways and backbone networks to small multimedia entertainment and personal communications for families and individuals, all of which have put forward higher requirements for the storage and transmission of information data. Users hope to get stable and reliable information representation and transmission at any time, any place and in any way, which poses a huge challenge to digital signal processing DSP technology, very large scale integrated circuit VLSI technology and modern digital communication technology. The vigorous development of the above technologies and related industries. With the development of consumer electronics towards portability and miniaturization, aerospace and military applications towards low storage and low power consumption, and the rapid development of integrated circuit technology, ASIC and system-on-chip SoC have entered the market and gradually matured.

With the continuous development of microelectronics technology, the line width inside the chip is continuously reduced, so the area of electronic devices is getting smaller and smaller; however, the reduction of line width increases the circuit density of the chip, and the latch-up effect in CMOS circuits becomes more and more serious. Moreover, according to the paper Single Event Upset at Ground Level (Vo1.43, No.6, Dec.1996, pp.2742-2750) published by American researcher Eugene Normand in the journal IEEE Trans.Nuclear Science in 1996, integrated circuits and electronic equipment are very sensitive to radiation in both the space environment and the terrestrial environment. For example, if communication and signal processing chips are to be used in satellite systems, they must ensure reliable operation in the space radiation environment. Space radiation mainly comes from cosmic rays, Van Allen radiation belts, solar flares, solar electromagnetic radiation, and auroral radiation; radiation in the ground environment mainly comes from atmospheric neutrons and high-energy particles produced by deep-space cosmic radiation sources. cosmic rays, and radioactive materials used in the production of circuits.

The two main causes of functional failure of electronic devices by irradiation are atomic displacement and ionization. Atomic displacement is caused by particles hitting atoms and changing their intrinsic position. If the atoms are in a crystal structure, this atomic displacement will change the material properties. The effect of particle injection on semiconductor devices is similar. Ionization also causes charges to move, forming electron-hole pairs, which create internal electric fields and internal currents that can change the functionality of the original circuit. This effect will not cause damage to the circuit, but only cause the circuit function to be disordered.

After the electronic device is irradiated, it will produce ionizing radiation total dose effect, dose rate effect, single event effect, displacement effect and high-voltage electrostatic discharge breakdown effect, etc. At present, the total dose effect of ionizing radiation TID and single event Effect SEE. Using a specific CMOS tape-out process, a good total ionizing radiation dose index can be obtained in theory, and it has been verified in experiments. Single event effects are mainly divided into single event locking SEL and single event flipping SEU. Single event lock-up is a large current gathered in the low-frequency path generated between the power supply and ground, so it is inevitably destructive to the circuit, and with the continuous reduction of physical size, supply current and threshold voltage, single event lock-up The resulting functional failures continue to increase. Therefore, in practical applications, it is of great value to analyze and propose solutions to the single event flipping problem in the irradiation environment from the perspective of circuit design.

Single event flipping is a state jump generated when high-energy charged particles bombard the device. Figure 8(a) shows a simple circuit of a single-bit memory cell. The circuit in the figure remains in a stable state, that is, storing "0" or storing " 1", in each state two transistors are active and the other two are blocked. Figure 8(b) illustrates the process of a single-bit memory cell being bombarded by a high-energy charged particle and causing a bit flip. The particle forms electron-hole pairs on the path through the substrate. Drain crowding, similar to the effect of a sufficiently large current pulse, produces the spurious equivalent of a normal signal acting on a transistor, namely a bit flip. In addition to generating bit flips on memory cells, single event flips may also cause errors in logic resources, mainly in the following categories: (1) changing a bit in the lookup table LUT, thereby changing the implemented combinational logic function; (2) ) Changing the configuration of the multiplexer MUX, which causes the signal to not be transmitted correctly in the forward direction of each logic block; (3) Changing the configuration of the flip-flop FF, such as changing the polarity of the reset signal line or the clock line, resulting in a circuit function error.

Most of the field programmable gate array FPGA devices and special-purpose chips currently used are based on random access memory RAM. This kind of device integrating a large number of storage units is more sensitive to single event upset, and the frequency of single event upset is closely related to the irradiation environment. . According to American researcher Michael Wirthlin's estimate in the paper The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets (llth Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003, pp.133-142), for an integrated 6 million-bit storage array , The FPGA model is XilinxVirtex 1000, the peak frequency of single event flipping under harsh conditions is as high as 4.2 times per hour, far exceeding the 0.13 times per hour during the period of stable solar activity. Moreover, with the different energy and frequency of charged particles, the phenomenon of device failure is also different. When it is mild, only a single bit flip may occur in a single clock, and when it is severe, multiple bits may occur in a certain segment The time is continuously or intermittently reversed, and even worse, the function of the whole device collapses.

In communication and signal processing systems involving civil applications, aerospace exploration, and military applications, many data processing units are composed of frame structures, that is, input and output are in units of frames, and they are independent of each other. . For example, for an image compression encoding processing unit conforming to the JPEG2000 standard, each frame data is separately compressed and processed, and the output bit stream is composed of N frames, and each frame is composed of a frame header, frame data and frame tail, and the specific format is shown in Figure 9; Another example is the error correction coding unit in the communication system. For commonly used block coding methods, such as Reed-Solomon RS code, low-density parity check LDPC code, etc., the encoded signal is also separated frame by frame. If the processing unit does not consider the frame design, the error of the control function caused by the single event flip may not be corrected and the error will continue. Therefore, even with physical shielding and protection, there are still potential risks in the application of processing units without framing design in environments such as space radiation, and cannot provide reliable and stable services for users.

Contents of the invention

Based on the analysis of the above-mentioned single event effect and its influence on electronic devices, and in combination with the characteristics of the frame structure data processing unit, the present invention provides an anti-single event irradiation method and an anti-single event irradiation system based on frame data processing, aiming at From the perspective of circuit design, the frame data processing unit is protected and error corrected to reduce the influence of single event effects and improve the reliability and stability of the processing unit and the entire system.

The technical key to realize the object of the present invention is to establish a reasonable single event flip model, and analyze the impact of the single event effect on the frame data processing unit through the software simulation model, specifically to analyze the bit flips that occur in the frame header, frame data and frame tail respectively. The impact on the processing results, on this basis, protect and correct the single frame detection and reset module, controller circuit, memory circuit and configuration module in the hardware implementation structure from the perspective of circuit design, so that the frame data processing unit The hardware structure has the characteristics of resisting single event radiation within a certain range. Its specific scheme is described as follows:

1. The anti-single event irradiation method based on frame data processing, comprising the following steps:

(1) By reading in data, each frame of data to be processed and independent of each other is generated;

(2) Simulate the errors generated by the single event radiation effect, and generate a single event radiation effect error list;

(3) Using the single event irradiation effect error list, modify the internal functions of the correct frame data processing module to form an error frame data processing module;

(4) each frame data is processed separately with the correct frame data processing module and the error frame data processing module, and the correct processing result and the error processing result of each frame are respectively obtained;

(5) Compare the difference between the correct processing result and the wrong processing result of each frame, and analyze the errors caused by the single event irradiation effect error list to the correct frame data processing module, which specifically appear in the frame header, frame data or frame tail of the error processing result which parts, and give an error report;

(6) Feedback the error part listed in the error report to the error frame data processing module to correct the error function therein, and obtain the corrected processing result of this step;

(7) Steps (5)-(6) are repeated until the corrected processing result is exactly the same as the result of the correct frame data processing module.

2. Anti-single particle radiation system based on frame data processing, including: single frame detection and reset module, frame data processor,

The single frame detection and reset module includes: a frame synchronization signal extraction circuit and a single frame reset signal generation circuit, the frame synchronization signal extraction circuit detects and extracts the frame synchronization signal from the input frame data and transmits it to the single frame reset signal generation circuit, The single-frame reset signal generating circuit resets the frame data processor during the period when the frame synchronization signal is invalid, so that all circuits of the frame data processor return to the initial state;

The frame data processor includes: a finite state machine assembly unit, a controller protection error correction unit, a memory, a memory protection error correction unit, a data input interface, a data output interface and a configuration module, and the finite state machine assembly unit is respectively connected with The data input interface, the data output interface and the configuration module are unidirectionally connected, and are bidirectionally connected with the controller protection error correction unit and the memory for processing each frame of data. The memory protection error correction unit is integrated with the finite state machine through the memory Connection for protection and error correction of data in memory using Hamming codes.

The present invention has the following advantages:

(1) The anti-single event irradiation method based on frame data processing proposed by the present invention simulates the error produced by the single event irradiation effect through software methods, establishes a reasonable single event flip model, and analyzes the single event effect on the frame data processing The impact of errors generated by the unit, so that the impact of bit flips on the processing results that occur in the frame header, frame data, and frame tail can be determined;

(2) The anti-single event irradiation system based on frame data processing proposed by the present invention corrects and protects the frame data processing unit from the perspective of circuit design, detects and resets each frame data as a unit, and performs frame data processing The controller, memory and configuration module in the processor perform protection and error correction, thereby reducing the impact of single event effects, and improving the reliability and stability of the frame data processing unit and the entire system.

Description of drawings

Fig. 1 is the flow chart of the anti-single particle irradiation method based on frame data processing in the present invention;

Fig. 2 is a functional block diagram of the anti-single particle irradiation system based on frame data processing in the present invention;

Fig. 3 is a functional block diagram of a single frame detection and reset module of the present invention;

Fig. 4 is a functional block diagram of the finite state machine assembly unit of the present invention;

Fig. 5 is a functional block diagram of the controller protection error correction unit of the present invention;

Fig. 6 is a functional block diagram of the memory protection error correction unit of the present invention;

Fig. 7 is a schematic diagram of the configuration module of the present invention;

8 is a schematic diagram of a single-bit storage unit circuit and a single event flip;

FIG. 9 is a schematic diagram of a frame format based on the JPEG2000 standard adopted by the present invention.

Detailed ways

The frame data processing unit adopted in the specific embodiment of the present invention is an image compression system based on the JPEG2000 standard. The JPEG2000 standard is currently an international standard for still image compression and encoding, and each frame is independently encoded for still image compression. The JPEG2000 standard is widely used in medical imaging, remote sensing images, and digital image/video transmission due to its excellent compression performance and support for progressive transmission of image quality and resolution, especially in satellites that require high image compression quality. Earth observation and other applications play an increasing technical and strategic role. For other data processing units based on frame data processing, such as image compression units based on JPEG standards or error correction and modulation circuits based on packets, they also have important requirements in various applications, so the research and design implementation for space environment and unit The design method and corresponding structure based on frame data processing under particle irradiation are of great significance and value.

Software emulation model of the present invention utilizes Microsoft Visual Studio development platform and C/C++ language to finish realizing, and hardware implementation structure adopts Xilinx ISE 10.1.03 integrated development environment and Verilog HDL language, and the model of Xilinx company is on the FPGA device of XC4Vfx140-11ff1517 accomplish.

Referring to Fig. 1, the anti-single event irradiation method based on frame data processing proposed by the present invention comprises the following steps:

In the first step, each frame of data to be processed and independent of each other is generated by reading in data, and each frame of data is several frames of images for independent processing or a packet-based error correction and modulation sequence.

The second step is to simulate the errors generated by the single event radiation effect, and generate a single event radiation effect error list:

(2a) Some status bits or data bits in the correct frame data processing module are fixed or randomly set to "1" or set to "0", so that errors occur in these status bits or data bits, which are used to simulate single events register bit flip caused by flipping;

(2b) One or several bits in the lookup table of the correct frame data processing module are fixed or randomly flipped, so that the corresponding relationship of the lookup table is wrong, and the error is used to simulate the combinational logic function error caused by the single event flipping;

(2c) Using random distribution or other probability distributions, adding errors in the memory space mapped to the cached data of the correct frame data processing module to cause errors in the cached data, which are used to simulate data errors in storage units caused by single event flipping;

(2d) Modify the parameter value or cut off the connection relationship between the functions in the correct frame data processing module, so that the function transmission error occurs. This error is used to simulate the functional disorder or even the failure of all functions when the single event effect is serious;

(2e) Select one or more of the errors in (2a) to (2d) and arrange and combine them to generate a single event irradiation effect error list.

The third step is to modify the internal functions of the correct frame data processing module by using the single event irradiation effect error list to form an error frame data processing module:

(3a) Add the single event radiation effect error list to the frame header of the correct frame data processing module, resulting in "1" and "0" exchange, bit increase and bit decrease in the value of the frame header start-stop flag or information flag Three types of errors lead to the inability to correctly determine the position of the frame header start and end flags, and the meaning of the frame header information flags cannot be correctly expressed;

(3b) Add the single event irradiation effect error list to the frame data part of the correct frame data processing module, resulting in three errors of "1" and "0" exchange, bit increase and bit decrease in the value of the effective information bit of the frame data, Make errors in the effective information represented by the frame data;

(3c) Add the single event irradiation effect error list to the frame tail part of the correct frame data processing module, resulting in "1" and "0" exchange, bit increase and bit decrease in the value of the start and end flag bit or information flag bit at the end of the frame Three kinds of errors cause the position of the start-stop flag at the end of the frame cannot be correctly determined, and the meaning of the end-of-frame information flag cannot be correctly expressed.

The fourth step is to use the correct frame data processing module and the error frame data processing module to process each frame data separately, and obtain the correct processing results and error processing results of each frame respectively:

(4a) For the sequence I formed by each frame data, carry out image compression processing based on the JPEG standard or the JPEG2000 standard according to the correct frame data processing module function F( ):

First, discrete cosine transform or discrete wavelet transform is performed on the image data,

Then, entropy encoding is performed on the transformed coefficients,

Finally, pack the entropy encoding result and output the correct processing result J=F(I) of each frame;

(4b) For the sequence S formed by each frame data, carry out error correction coding processing according to the correct frame data processing module function G(·):

First, the information bits to be coded are grouped,

Next, determine the generation matrix used in the error correction code,

Then, perform a matrix operation on the grouped codeword and the generator matrix to generate an error correction code check bit,

Finally, the information bit and the parity bit are interleaved or combined, and the correct processing result T=G(S) of each frame is output;

(4c) For the sequence X formed by each frame data, perform cascade processing based on JPEG standard or JPEG2000 standard image compression and error correction coding according to the correct frame data processing module function H( ):

(4c1) performing discrete cosine transform or discrete wavelet transform on the image data,

(4c2) entropy coding the transformed coefficients,

(4c3) Pack the entropy coding result,

(4c4) group the packed information bits,

(4c5) determining the generator matrix used in the cascading process,

(4c6) performing a matrix operation on the codeword after packing and grouping with the generation matrix used in the concatenation process to generate the concatenation process check bit,

(4c7) Interleaving or merging the information bit and the parity bit, and outputting the final correct processing result Y=H(X) of each frame;

(4d) The sequence P formed by each frame data is processed according to the wrong frame data processing module function E(·), this processing is an image compression function error based on the JPEG2000 standard after adding the single event radiation effect error list, or It is an error correction coding error, or a cascade processing error based on JPEG2000 standard image compression and error correction coding, and the error processing result Q=E(P) of each frame is obtained.

The fifth step is to compare the difference between the correct processing result and the wrong processing result of each frame, and analyze the errors caused by the single event irradiation effect error list to the correct frame data processing module, which specifically appear in the frame header, frame data or frame tail of the error processing result which parts of the , and give an error report.

The sixth step, error feedback correction:

From the output results, the errors caused by the single event effect are divided into three situations, namely, bit errors, bit loss and bit increase, in which bit errors include random errors and burst errors, and the errors of the compressed code stream directly affect the performance of the decoding software. Normal operation will lead to errors in decoding and restoring images, resulting in image quality degradation or even unusable restored images, or a large amount of useful data will be lost during the decoding process, and once decoding errors may directly affect the normal progress of subsequent decoding, accumulation and propagation of decoding errors will occur, serious It may cause the decoding software system to crash.

Feedback the error part listed in the error report to the error frame data processing module to correct the error function, and obtain the corrected processing result of this step, proceed as follows:

Firstly, the frame data analysis module judges which parts of the frame head, frame data and frame tail appear in the compressed code stream respectively by detecting the error frame data processing result and the correct frame data processing result,

Then, with the help of image decompression software, objective and subjective quality evaluation criteria, the impact of errors on the restored image is analyzed, for example, when a slight error occurs, it hardly affects the quality of the restored image; or when a moderate error occurs, the original image can be partially restored correctly, but the restored quality decline; even in the event of a serious error, the image data cannot be recovered at all,

Finally, the error part listed in the error report is fed back to the error frame data processing module to correct the error function therein.

In the seventh step, the fifth and sixth steps are repeated until the corrected processing result is exactly the same as the result of the correct frame data processing module.

Referring to Fig. 2, the anti-single particle irradiation system based on frame data processing proposed by the present invention includes: a single frame detection and reset module, a frame data processor, wherein: a single frame detection and reset module, as shown in Fig. 3; Data processor, as shown in Figure 4 to Figure 7.

Referring to FIG. 3 , the single frame detection and reset module proposed by the present invention includes: a frame synchronization signal extraction circuit and a single frame reset signal generation circuit.

If the input image data contains a frame synchronization signal, the frame synchronization signal extraction circuit extracts the frame synchronization signal and transmits it to the single frame reset signal generation circuit, the frame synchronization signal in Fig. 3 is active at high level and invalid at low level; if the input If the image data does not contain a frame synchronization signal, the corresponding frame synchronization signal is generated by the frame synchronization signal extraction circuit and transmitted to the single frame reset signal generation circuit.

The single-frame reset signal generation circuit resets the frame data processor during the invalid period of the frame synchronization signal. In Fig. 3, the low level of the single-frame reset signal is in the reset valid state, and the high level is in the invalid state. The generated single-frame reset signal is in every Return all the circuits inside the frame data processor to the initial state before the effective data of the frame image is input, so that the single event error that may occur in the image data of this frame can be limited to the frame, avoiding the functional error caused by the single event flip passed between two consecutive frames, resulting in uncorrectable errors.

The frame data processor, as shown in Figures 4 to 7, includes: a finite state machine assembly unit, a controller protection error correction unit, a memory, a memory protection error correction unit, a data input interface, a data output interface and a configuration module, The finite state machine assembly unit is respectively connected to the data input interface, data output interface and configuration module in one direction, and is connected to the controller protection error correction unit and memory in two directions to process each frame of data; the memory protection error correction unit communicates with the finite The state machine assembly unit is connected, and is used for protecting and error-correcting the data in the memory by using the Hamming code.

Referring to Fig. 4, the finite state machine assembly unit in the frame data processor is composed of several finite state machines cascaded, and these finite state machines jointly complete the processing of each frame data, wherein each finite state machine includes:

The current state register is used to record the state value of the finite state machine in the current state;

The output function circuit is used to complete the logic function in the current state;

The output register is used to register and output the result generated by the output function circuit;

The next state switching circuit is used to switch the state value in the current state register to the next state after the output function circuit completes the logic function of the current state.

The finite state machine is divided into two types: Moore type finite state machine and Miller type finite state machine. Figure 4(a) and Figure 4(b) show Moore type and Miller type finite state machine respectively. The difference is that the output of the Moore-type state machine is only related to the current state, while the output of the Miller-type state machine is a function of the current state and the input signal; both have in common that no matter the Moore-type or Miller-type, only the current Status registers are sequential logic components with memory capabilities.

With reference to Fig. 5, the controller protection error correction unit in the described frame data processor realizes the effective protection to the control function in the frame data processor by the protection of state machine, this controller protection error correction unit is divided into Fig. 5(a) The protection and error correction unit of the Moore-type state machine and the protection and error-correction unit of the Miller-type state machine in Figure 5(b), both of which include:

A Hamming coding logic circuit for performing Hamming coding on all state values in the current state register;

The Hamming decoding logic circuit is used to perform Hamming decoding on the state value in the current state in the current state register;

The error indication reset circuit is used to judge whether the state value generated by the Hamming decoding logic circuit is equal to the state value in the Hamming encoding logic circuit. If the two are equal, proceed according to the original function of the finite state machine. If the two are not equal , to reset the finite state machine to make it return to the initial state;

The Hamming coding logic circuit, the Hamming decoding logic circuit and the error indication reset circuit are respectively connected with each finite state machine in the finite state machine assembly unit, and the finite state machine is protected and corrected by Hamming code.

The protection and error correction unit of the Moore-type state machine in FIG. 5( a ) will be described in detail below. The protection and error correction unit of the Moore state machine adopts (7,4) Hamming code when encoding the finite state machine, but it is not limited to the block code form of this Hamming code, and improves the state machine by increasing the Hamming distance between code words. Fault tolerance of registers affected by single event effects. In the process of the state in the current state register jumping from the current state to the next state, the specific implementation functions of the protection and error correction unit circuit of the Moore-type state machine are as follows:

The current state passes through the output function circuit and the output register to obtain the final result;

The current state jumps to the next state through the next state switching circuit;

Hamming coding logic circuit, which performs Hamming coding on the next state value, and at the same time, the state in the current state register is changed from the current state to the next state

The Hamming decoding logic circuit performs Hamming decoding on the state value in the current state in the current state register, and completes the protection and error correction function of the Moore state machine;

An error indication resets the circuit, and judges whether the state value generated by the Hamming decoding logic circuit is equal to the state value in the Hamming coding logic circuit. If the state error caused by the single event effect is within the error correction capability of the Hamming code, according to the principle If the function continues, the correct function of the entire state machine can be ensured; if the Hamming code cannot correct the error, the current state register will be reset to prevent the current state register from being uncorrected due to the state error of the single event effect. Figure 5(b) is the protection and error correction unit of the Miller-type finite state machine, and the difference between the protection and error correction unit of the Moore-type finite state machine in Figure 5(a) is only that the output function is a function of the current state and the input signal.

Referring to Fig. 6, the memory protection and error correction unit in the frame data processor protects and corrects the data in the memory, and it includes: a check bit calculation circuit, a check bit check circuit and a comparator. Both the check bit calculation circuit and the check bit check circuit are unidirectionally connected to the memory, and the comparator is respectively unidirectionally connected to the memory and the check bit check circuit. The check bit calculation circuit performs Hamming encoding on the effective data information bit M to be written into the memory to produce the check bit K, and writes M and K into the memory respectively; Read the information bit M' from the middle to perform Hamming code inspection to generate a new check bit K"; the comparator reads the check bit K' from the memory affected by the single event irradiation effect, and compares it bit by bit with K", If K' and K" are equal, the read information bit M' is output, and if they are not equal, an error indication will be given.

The memory protection error correction unit can relieve the influence of the single event effect on the memory to a certain extent. In order to save the storage space for saving the check information, choose the form of Hamming code to calculate the check digit, for example, choose the (7,4) form Hamming code including 4 information bits and 3 check digits. According to the nature of the Hamming code, any 1 bit in the 7-bit data is flipped, and the Hamming code can be corrected, so as to achieve the purpose of anti-single event effect.

With reference to Fig. 7, the configuration module in the described frame data processor is made up of three parameter register groups with the same function and a decision device, stores the parameter information needed by the frame data processor in the three register groups, and the decision device is respectively from three Read the corresponding parameter information from the parameter register group, and output the result according to the large number judgment method.

The first parameter register group is composed of a number of registers. The number of registers is determined by the function of the frame data processor. The parameter information required by the frame data processor is stored in the registers. The internal parameters of the second parameter register group and the third parameter register group The structure is exactly the same as that of the first parameter register group, that is, the function of the first parameter register group is copied twice. When the frame data processor accesses the parameter information in the parameter register group, the decision device simultaneously reads out the corresponding data from the first parameter register group, the second parameter register group and the third parameter register group respectively, and decides according to the large number judgment method Output the result. Through this method of parameter register group backup, once a bit in a parameter register group is affected by a single event effect and an error occurs, the decision device can determine the correct parameter information through the data of the other two parameter register groups to avoid The frame data processor uses wrong parameter information to get wrong processing results.

For those skilled in the art, after understanding the contents and methods of the present invention, they can make various modifications and changes in form and details according to the methods of the present invention without departing from the principle and scope of the present invention. It is not limited to the anti-single event irradiation method and anti-single event irradiation structure based on JPEG2000 standard image compression in the embodiment, such as other anti-single event irradiation methods based on frame or packet data processing error correction and modulation systems And anti-single event radiation structure, but these amendments and changes based on the present invention are still within the protection scope of the claims of the present invention.

Claims (8)

1. An anti-single particle irradiation method based on frame data processing, comprising the steps of: (1) By reading in data, each frame of data to be processed and independent of each other is generated; (2) Simulate the errors generated by the single event radiation effect, and generate a single event radiation effect error list; (3) Using the single event irradiation effect error list, modify the internal functions of the correct frame data processing module to form an error frame data processing module; (4) each frame data is processed separately with the correct frame data processing module and the error frame data processing module, and the correct processing result and the error processing result of each frame are respectively obtained; (5) Compare the difference between the correct processing result and the wrong processing result of each frame, and analyze the errors caused by the single event irradiation effect error list to the correct frame data processing module, which specifically appear in the frame header, frame data or frame tail of the error processing result which parts, and give an error report; (6) Feedback the error part listed in the error report to the error frame data processing module to correct the error function therein, and obtain the corrected processing result of this step; (7) Steps (5) to (6) are repeated until the corrected processing result is exactly the same as the result of the correct frame data processing module; The error generated by simulating the single event radiation effect described in step (2) generates a single event radiation effect error list, which is generated according to the following steps: (2a) Some status bits or data bits in the correct frame data processing module are fixed or randomly set to "1" or set to "0", so that errors occur in these status bits or data bits; (2b) One or several bits in the look-up table of the correct frame data processing module are fixed or flipped randomly, so that the corresponding relationship of the look-up table is wrong; (2c) Using random distribution or other probability distributions, adding error codes into the memory space mapped by the cached data of the correct frame data processing module, causing errors in the cached data; (2d) Modify the parameter value or cut off the connection relationship between the functions in the correct frame data processing module, so that an error occurs in the function transfer; (2e) Select one or more of the errors in (2a) to (2d) and arrange and combine them to generate a single event irradiation effect error list. 2. The anti-single event irradiation method according to claim 1, wherein the use of the single event irradiation effect error list described in step (3) modifies the internal functions of the correct frame data processing module, and operates as follows: (3a) Add the single event radiation effect error list to the frame header of the correct frame data processing module, resulting in "1" and "0" exchange, bit increase and bit decrease in the value of the frame header start-stop flag or information flag Three types of errors lead to the inability to correctly determine the position of the frame header start and end flags, and the meaning of the frame header information flags cannot be correctly expressed; (3b) Add the single event irradiation effect error list to the frame data part of the correct frame data processing module, resulting in three errors of "1" and "0" exchange, bit increase and bit decrease in the value of the effective information bit of the frame data, Make errors in the effective information represented by the frame data; (3c) Add the single event irradiation effect error list to the frame tail part of the correct frame data processing module, resulting in "1" and "0" exchange, bit increase and bit decrease in the value of the start and end flag bit or information flag bit at the end of the frame Three kinds of errors cause the position of the start-stop flag at the end of the frame cannot be correctly determined, and the meaning of the end-of-frame information flag cannot be correctly expressed. 3. anti-single particle irradiation method according to claim 1, wherein the described in step (4) processes each frame data separately with correct frame data processing module and error frame data processing module, respectively obtains each frame's Correct processing results and error processing results, proceed as follows: (4a) For the sequence I formed by each frame data, carry out image compression processing based on the JPEG standard or the JPEG2000 standard according to the correct frame data processing module function F( ): First, discrete cosine transform or discrete wavelet transform is performed on the image data, Then, entropy encoding is performed on the transformed coefficients, Finally, pack the entropy encoding result and output the correct processing result J=F(I) of each frame; (4b) For the sequence S formed by each frame data, carry out error correction coding processing according to the correct frame data processing module function G(·): First, the information bits to be coded are grouped, Next, determine the generation matrix used in the error correction code, Then, perform a matrix operation on the grouped codeword and the generator matrix to generate an error correction code check bit, Finally, the information bit and the parity bit are interleaved or combined, and the correct processing result T=G(S) of each frame is output; (4c) For the sequence X formed by each frame data, perform cascade processing based on JPEG standard or JPEG2000 standard image compression and error correction coding according to the correct frame data processing module function H( ): The first step is to perform discrete cosine transform or discrete wavelet transform on the image data, The second step is to entropy encode the transformed coefficients, The third step is to pack the entropy coding results, The fourth step is to group the packed information bits, The fifth step is to determine the generation matrix used in the cascade processing, The sixth step is to perform a matrix operation on the codewords after packing and grouping with the generation matrix used for the concatenation processing to generate the concatenation processing check bits, The 7th step, information bit and parity bit are carried out interweaving or combining, output the correct processing result Y=H(X) of final each frame; (4d) The sequence P formed by each frame data is processed according to the wrong frame data processing module function E( ), which is an image compression function based on the JPEG standard or JPEG2000 standard after adding the single event radiation effect error list The error is either an error correction coding error, or a cascading processing error based on JPEG standard or JPEG2000 standard image compression and error correction coding, and the error processing result Q=E(P) of each frame is obtained. 4. An anti-single event irradiation system based on frame data processing, including: single frame detection and reset module, frame data processor, The single-frame detection and reset module includes: a frame synchronization signal extraction circuit and a single-frame reset signal generation circuit, and the frame synchronization signal extraction circuit detects and extracts frame synchronization signals from input frame data and transmits them to the single-frame reset signal generation circuit , the single-frame reset signal generation circuit resets the frame data processor during the invalid period of the frame synchronization signal, so that all circuits of the frame data processor return to the initial state; The frame data processor includes: a finite state machine assembly unit, a controller protection error correction unit, a memory, a memory protection error correction unit, a data input interface, a data output interface and a configuration module, and the finite state machine assembly unit is respectively One-way connection with the data input interface, data output interface and configuration module, and two-way connection with the controller protection error correction unit and memory for processing each frame of data; the memory protection error correction unit is integrated with the finite state machine through the memory The unit is connected, and is used for protecting and correcting the data in the memory by Hamming code. 5. The anti-single event irradiation system according to claim 4, characterized in that the finite state machine assembly unit in the frame data processor is composed of several finite state machines cascaded, and these finite state machines jointly complete the processing of each frame data processing, where each finite state machine consists of: The current state register is used to record the state value of the finite state machine in the current state; The output function circuit is used to complete the logic function in the current state; The output register is used to register and output the result generated by the output function circuit; The next state switching circuit is used to switch the state value in the current state register to the next state after the output function circuit completes the logic function of the current state. 6. The anti-single event irradiation system according to claim 4, characterized in that the controller protection error correction unit in the frame data processor comprises: A Hamming coding logic circuit for performing Hamming coding on all state values in the current state register; The Hamming decoding logic circuit is used to perform Hamming decoding on the state value in the current state in the current state register; The error indication reset circuit is used to judge whether the state value generated by the Hamming decoding logic circuit is equal to the state value in the Hamming encoding logic circuit. If the two are equal, proceed according to the original function of the finite state machine. If the two are not equal , to reset the finite state machine to make it return to the initial state; The Hamming coding logic circuit, the Hamming decoding logic circuit and the error indication reset circuit are respectively connected with each finite state machine in the finite state machine assembly unit, and the finite state machine is protected and corrected by Hamming code. 7. The anti-single event irradiation system according to claim 4, characterized in that the memory protection and error correction unit in the frame data processor adopts the form of Hamming code to protect and correct the data in the memory, the memory protection and correction Faulty units, including: A parity calculation circuit, which is used to perform Hamming encoding on the effective data information bit M to be written into the memory to produce a parity K, and write M and K into the memory; A parity check circuit, which is used to read the information bit M' from the memory affected by the single event radiation effect to perform Hamming code check, and generate a new check bit K"; The comparator is used to read the check bit K' from the memory affected by the single event irradiation effect, and compare it bit by bit with K ", and if K' is equal to K", output the read information bit M', If the two are not equal, an error indication will be given. 8. The anti-single event irradiation system according to claim 4, characterized in that the configuration module in the frame data processor is composed of three parameter register groups with the same function and a decision device, and the frame data is stored in the three register groups For the parameter information required by the processor, the decider reads out the corresponding parameter information from the three parameter register groups respectively, and outputs the result according to the large number judgment method.

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