CN114692564B - Verification system and method of LDPC error correction module, storage medium and electronic equipment - Google Patents
Verification system and method of LDPC error correction module, storage medium and electronic equipment Download PDFInfo
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Abstract
The application discloses a verification system and method of an LDPC error correction module, a storage medium and electronic equipment. The system comprises: the test case library is used for storing a plurality of test cases; a sequencer for generating an input stimulus transaction; the input agent is used for acquiring an input excitation transaction, driving the input excitation transaction to the LDPC error correction module, converting the input information of the LDPC error correction module into a reference input excitation transaction and sending the reference input excitation transaction to the simulation module; the simulation module is used for acquiring the reference input excitation transaction, generating a reference output transaction based on the reference input excitation transaction, and sending the reference output transaction to the comparator; the output agent is used for packaging the actual output information of the LDPC error correction module into an actual output transaction and sending the actual output transaction to the comparator; and the comparator is used for comparing the actual output transaction with the reference output transaction to obtain a comparison result. The application solves the problems of low verification efficiency and poor universality of the verification system of the LDPC error correction module in the related technology.
Description
Technical Field
The application relates to the field of verification of LDPC error correction modules, in particular to a verification system and method of an LDPC error correction module, a storage medium and electronic equipment.
Background
With the increase of chip scale and complexity, the difficulty and workload of chip verification also increase dramatically. The average time taken up by the verification work in the current chip design flow is already more than half, and the time ratio in part of chips is more than 70%. Therefore, how to efficiently and completely complete the verification work is a key factor for influencing the chip quality, the development period and the cost. Aiming at the problems of low abstraction level of verification language, limitation of verification ideas and the like in the traditional verification field, the prior UVM (Universal Verification Methodology) verification methodology based on the System Verilog language introduces a constrained random test idea, so that the defects of the traditional verification method can be overcome to a great extent, and the unique ideas, architecture and verification library also enable UVM to become the main stream method in the current verification field.
LDPC (Low DENSITY PARITY CHECK) codes, known as Low density parity check codes, have excellent performance, can approach Shannon's limit, and are widely studied and applied in the fields of communication, storage, and the like. In related chips in the communication and storage fields, an LDPC error correction module is generally responsible for the encoding and decoding functions of data as a key module. The conventional verification platform has to be improved in portability, universality, high efficiency and the like.
Aiming at the problems of low verification efficiency and poor universality of a verification system of an LDPC error correction module in the related art, no effective solution is proposed at present.
Disclosure of Invention
The application provides a verification method, a system, a storage medium and electronic equipment of an LDPC error correction module, which are used for solving the problems of low verification efficiency and poor universality of a verification system of the LDPC error correction module in the related technology.
According to an aspect of the present application, there is provided an authentication system of an LDPC error correction module. The system comprises: the test case library is used for storing a plurality of test cases of the LDPC error correction module; the sequencer is used for generating an input excitation transaction according to each test case respectively, wherein each sequencer corresponds to one test case; the input agent comprises a sequencer, a driver and an input monitor, wherein the sequencer is connected with the sequencer and used for acquiring input excitation transactions sent by the sequencer, the driver is connected with the sequencer and used for driving the input excitation transactions to the LDPC error correction module, the input monitor is used for converting input information of the LDPC error correction module into reference input excitation transactions and sending the reference input excitation transactions to the simulation module, the input excitation transactions contain input information, and the LDPC error correction module generates actual output information based on the input information; the simulation module is connected with the input monitor in the input agent and used for acquiring a reference input excitation transaction, generating a reference output transaction based on the reference input excitation transaction and sending the reference output transaction to the comparator; the output agent comprises an output monitor, and the output monitor is used for packaging the actual output information of the LDPC error correction module into an actual output transaction and sending the actual output transaction to the comparator; and the comparator is connected with the simulation module and an output monitor in the output agent and is used for comparing the actual output transaction with the reference output transaction to obtain a comparison result.
Optionally, the system further comprises: and aggregating the parameter class, wherein the aggregation parameter class is used for storing check matrix information, and the check matrix information is used for initializing the LDPC error correction module.
Optionally, the system further comprises: and one end of the configuration interface is connected with the LDPC error correction module, and the other end of the configuration interface is connected with a driver for providing a first method, wherein the driver calls the first method to drive the check matrix information to the LDPC error correction module so as to complete the initialization configuration of the LDPC error correction module.
Optionally, the system further comprises: the data interface is used for providing a second method, a third method and a fourth method, wherein the driver calls the second method to drive the input excitation transaction to the LDPC error correction module, the input monitor calls the third method to acquire the input information of the LDPC error correction module, the input information is packaged into a reference input excitation transaction, the output monitor calls the fourth method to acquire actual output information, and the actual output information is packaged into an actual output transaction.
According to another aspect of the present application, there is provided a verification method of an LDPC error correction module. The method comprises the following steps: acquiring test cases of the LDPC error correction module from a test case library; generating an input excitation transaction through a sequencer corresponding to a test case of the LDPC error correction module; driving, by a driver, the input stimulus transaction to an LDPC error correction module; acquiring a reference input excitation transaction through an input monitor, and sending the reference input excitation transaction to a simulation module; operating a reference input excitation transaction through a simulation module to obtain a reference output transaction, and sending the reference output transaction to a comparator; acquiring an actual output transaction of the LDPC error correction module through an output monitor, and sending the actual output transaction to a comparator; and comparing the actual output transaction with the reference output transaction through a comparator to obtain a comparison result.
Optionally, before acquiring the test case of the LDPC error correction module from the test case library, the method further includes: acquiring a function list of the LDPC error correction module, creating a plurality of first test cases according to functions in the function list, and storing the plurality of first test cases into a test case library; and/or acquiring interface information and register information of the LDPC error correction module, creating a plurality of second test cases according to the interface information and the register information, and storing the plurality of second test cases into a test case library; and/or obtaining abnormal condition information existing in the LDPC error correction module, creating a plurality of third test cases according to the abnormal condition information, and storing the plurality of third test cases into a test case library, wherein the abnormal condition at least comprises one of the following: data exception, register exception, protocol exception, timing exception, pressure test exception; and/or acquiring error code characteristics of the LDPC error correction module under different application scenes, creating a plurality of fourth test cases according to the error code characteristics under different application scenes, and storing the plurality of fourth test cases into a test case library; and/or determining the code which is not verified by the LDPC error correction module according to the coverage rate data result of the LDPC error correction module, designing a fifth test case according to the code which is not verified, and storing the fifth test case into a test case library.
Optionally, after the test cases of the LDPC error correction module are obtained from the test case library, the method further includes: acquiring check matrix information; storing the check matrix information into an aggregation parameter class, and transmitting a pointer of the aggregation parameter class to a driver; and calling a first method in the configuration interface through a driver to drive the check matrix information in the aggregation parameter class into the LDPC error correction module so as to finish the initialization configuration of the LDPC error correction module.
Optionally, driving, by the driver, the input stimulus transaction to the LDPC error correction module comprises: invoking a second method in the data interface by the driver to drive the input stimulus transaction to the LDPC error correction module; acquiring, by the input monitor, a reference input stimulus transaction includes: the method comprises the steps that input information of an LDPC error correction module is obtained through a third method in a data interface called by an input monitor, and the input information is packaged into a reference input excitation transaction; acquiring, by the output monitor, the actual output transaction generated by the LDPC error correction module includes: and the output monitor calls a fourth method of the data interface to acquire the actual output information generated by the LDPC error correction module, and encapsulates the actual output information into an actual output transaction.
Optionally, running the reference input stimulus transaction through the simulation module, the deriving the reference output transaction includes: under the condition that the LDPC error correction module is an encoding module, invoking an LDPC encoding algorithm model in the simulation module through a direct programming interface, and running a reference input excitation transaction in the LDPC encoding algorithm model to obtain a reference output transaction; and under the condition that the LDPC error correction module is a decoding module, calling the LDPC decoding algorithm model in the simulation module through a direct programming interface, and operating the reference input excitation transaction in the LDPC decoding algorithm model to obtain the reference output transaction.
According to another aspect of the present application, there is provided an apparatus for verifying an LDPC error correction module. The device comprises: the first acquisition unit is used for acquiring the test cases of the LDPC error correction module from the test case library; the generating unit is used for generating an input excitation transaction through a sequencer corresponding to the test case of the LDPC error correction module; a driving unit for driving the input excitation transaction to the LDPC error correction module through a driver; the second acquisition unit is used for acquiring a reference input excitation transaction through the input monitor and sending the reference input excitation transaction to the simulation module; the operation unit is used for operating the reference input excitation transaction through the simulation module to obtain a reference output transaction and transmitting the reference output transaction to the comparator; the third acquisition unit is used for acquiring the actual output transaction of the LDPC error correction module through the output monitor and sending the actual output transaction to the comparator; and the comparison unit is used for comparing the actual output transaction with the reference output transaction through the comparator to obtain a comparison result.
According to another aspect of the embodiment of the present invention, there is also provided a nonvolatile storage medium, the nonvolatile storage medium including a stored program, wherein when the program runs, the device in which the nonvolatile storage medium is controlled to execute a verification method of an LDPC error correction module.
According to another aspect of the embodiment of the present invention, there is also provided an electronic device including a processor and a memory; the memory stores computer readable instructions, and the processor is configured to execute the computer readable instructions, where the computer readable instructions execute a method for verifying an LDPC error correction module.
According to the application, the following steps are adopted: acquiring test cases of the LDPC error correction module from a test case library; generating an input excitation transaction through a sequencer corresponding to a test case of the LDPC error correction module; driving, by a driver, the input stimulus transaction to an LDPC error correction module; acquiring a reference input excitation transaction through an input monitor, and sending the reference input excitation transaction to a simulation module; operating a reference input excitation transaction through a simulation module to obtain a reference output transaction, and sending the reference output transaction to a comparator; acquiring an actual output transaction of the LDPC error correction module through an output monitor, and sending the actual output transaction to a comparator; the comparison result is obtained by comparing the actual output transaction with the reference output transaction through the comparator, and the problems of low verification efficiency and poor universality of a verification system of the LDPC error correction module in the related technology are solved. By constructing a verification system of the LDPC error correction module based on the thought and the framework of the UVM verification methodology, the method has better universality and reusability for application scenes of different LDPC error correction modules; the verification system of the LDPC error correction module comprises a configuration interface and a data interface, and the interfaces of the LDPC error correction module are divided, so that the problem of code redundancy and error susceptibility caused by excessive signals in the same interface can be solved; the main method in the verification system of the LDPC error correction module is realized in the configuration interface and the data interface, and the design thought ensures that the verification platform only needs to pay attention to the interface part when in maintenance and transplantation; the design thought does not need to realize time sequence control in a driver and a monitor, thereby being beneficial to the realization of the acceleration of co-simulation hardware; the design of the test excitation library provides a referent design idea of test cases, and the idea can be applied to other modules to be tested.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
FIG. 1 is a schematic diagram of a verification system of an LDPC error correction module provided according to an embodiment of the present application;
FIG. 2 is a flowchart of a verification method of an LDPC error correction module provided according to an embodiment of the present application;
Fig. 3 is a schematic diagram of a verification apparatus of an LDPC error correction module according to an embodiment of the present application.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
For convenience of description, the following will describe some terms or terminology involved in the embodiments of the present application:
UVM: (Universal Verification Methodology) a verification methodology that introduces a constrained random test concept, provides a unique and unified verification concept and architecture, and can meet the requirements of various chip verifications;
LDPC code: (Low DENSITY PARITY CHECK), the Low density parity check code has excellent performance, can approach Shannon limit, and is widely researched and applied in the fields of communication, storage and the like.
According to an embodiment of the present application, there is provided an authentication system of an LDPC error correction module.
Fig. 1 is a schematic structural diagram of an authentication system of an LDPC error correction module according to an embodiment of the present application, as shown in fig. 1, the system includes:
And the test case library is used for storing a plurality of test cases of the LDPC error correction module.
Specifically, a plurality of test cases corresponding to the LDPC error correction module to be tested can be obtained from a test case library, each test case corresponds to one test excitation, each test excitation stores configuration information or data information, the verification system of the LDPC error correction module tests one test case each time until all test cases in the test case library are tested, and the verification of the LDPC error correction module is finished.
And the sequencers are used for generating input excitation transactions according to each test case respectively, wherein each sequencer corresponds to one test case.
Specifically, the sequencer is configured to generate an input excitation transaction according to data information and configuration information corresponding to the test case, where the input excitation transaction is a communication unit including the input information, and the communication is performed in a transaction form in a verification system of the LDPC error correction module.
The input agent comprises a sequencer, a driver and an input monitor, wherein the sequencer is connected with the sequencer and used for acquiring input excitation affairs sent by the sequencer, the driver is connected with the sequencer and used for driving the input excitation affairs to the LDPC error correction module, the input monitor is used for converting input information of the LDPC error correction module into reference input excitation affairs and sending the reference input excitation affairs to the simulation module, the input excitation affairs contain the input information, and the LDPC error correction module generates actual output information based on the input information.
Specifically, the sequencer sends an input excitation transaction to the sequencer, the driver applies for the input excitation transaction to the sequencer, and in the case that the driver successfully acquires the input excitation transaction, the driver calls a put_transfer method in the data interface to drive the input excitation transaction to the LDPC error correction module, and the input monitor calls a get_in_transfer method in the data interface to collect input information of the LDPC error correction module, package the input information into a reference input excitation transaction, and send the reference input excitation transaction to the simulation module.
And the simulation module is connected with the input monitor in the input agent and used for acquiring the reference input excitation transaction, generating a reference output transaction based on the reference input excitation transaction and sending the reference output transaction to the comparator.
Specifically, the simulation module uses a DPI interface (direct programming interface) to invoke an algorithm model to run a reference input stimulus transaction, obtain a reference output transaction, and send the reference output transaction to the comparator.
And the output agent comprises an output monitor, and the output monitor is used for packaging the actual output information of the LDPC error correction module into an actual output transaction and sending the actual output transaction to the comparator.
Specifically, the LDPC error correction module operates input information and outputs actual output information, and the output monitor calls a get_out_transfer method in the data interface to collect the actual output information, packages the actual output information into an actual output transaction and sends the actual output transaction to the comparator.
And the comparator is connected with the simulation module and an output monitor in the output agent and is used for comparing the actual output transaction with the reference output transaction to obtain a comparison result.
Specifically, after the actual output transaction and the reference output transaction are obtained by the comparator, the actual output transaction and the reference output transaction are compared, and under the condition that the comparison result shows that the data in the actual output transaction and the data in the reference output transaction are consistent, the verification of the test case of the current test is determined to pass.
Optionally, in the verification system of the LDPC error correction module provided by the embodiment of the present application, the system further includes: and aggregating the parameter class, wherein the aggregation parameter class is used for storing check matrix information, and the check matrix information is used for initializing the LDPC error correction module.
Specifically, the check matrix information may be LDPC check matrix related information, which is read from the outside of the verification system of the LDPC error correction module, stored into an aggregation parameter class, and transferred to the driver by a pointer of the aggregation parameter class.
Optionally, the system further comprises: and one end of the configuration interface is connected with the LDPC error correction module, and the other end of the configuration interface is connected with a driver for providing a first method, wherein the driver calls the first method to drive the check matrix information to the LDPC error correction module so as to complete the initialization configuration of the LDPC error correction module.
Specifically, the first method may be a set_matrix method, a set_matrix method is defined in the configuration interface, and the driver calls the set_matrix method to drive the check matrix information to the LDPC error correction module, and the LDPC error correction module completes initialization configuration through the check matrix information.
Optionally, the system further comprises: the data interface is used for providing a second method, a third method and a fourth method, wherein the driver calls the second method to drive the input excitation transaction to the LDPC error correction module, the input monitor calls the third method to acquire the input information of the LDPC error correction module, the input information is packaged into a reference input excitation transaction, the output monitor calls the fourth method to acquire actual output information, and the actual output information is packaged into an actual output transaction.
Specifically, the second method may be a put_transfer method, the third method may be a get_in_transfer method, and the fourth method may be a get_out_transfer method, where the second, third, and fourth methods are defined in the data interface to facilitate the driver, the input monitor, and the output monitor to call these methods.
The verification system of the LDPC error correction module provided by the embodiment of the application is realized based on the idea and framework of UVM verification methodology, and has better universality and reusability for application scenes of different LDPC error correction modules.
According to another embodiment of the present application, there is provided a verification method of an LDPC error correction module.
Fig. 2 is a flowchart of a verification method of an LDPC error correction module according to an embodiment of the present application. As shown in fig. 2, the method comprises the steps of:
Step S102, test cases of the LDPC error correction module are obtained from the test case library.
Specifically, the test case library is designed according to the multi-dimensions of the function list, the input signals, the register information, the abnormal scene, the coverage rate result and the like of the LDPC error correction module, the test case library is a database for storing test cases, each test case generates a corresponding input excitation, and the input excitation can be driven into the LDPC error correction module to realize various functions of the LDPC error correction module.
Step S104, generating an input excitation transaction through a sequencer corresponding to the test case of the LDPC error correction module.
Specifically, the input excitation transaction contains input information, and the input information can run in the LDPC error correction module.
Step S106, driving the input excitation transaction to the LDPC error correction module by the driver.
Specifically, the driver drives the input information to the LDPC error correction module.
Step S108, acquiring a reference input excitation transaction through the input monitor, and sending the reference input excitation transaction to the simulation module.
Specifically, an input monitor monitors input information of the LDPC error correction module, encapsulates the input information as a reference input stimulus transaction, and sends the reference input stimulus transaction to the simulation module.
Step S110, a reference input excitation transaction is run through the simulation module, a reference output transaction is obtained, and the reference output transaction is sent to the comparator.
Specifically, the simulation module calls an algorithm model to run a reference input excitation transaction through the DPI interface, when the LDPC error correction module is an encoding module, the simulation module calls an LDPC encoding C algorithm model to run the reference input excitation transaction, when the LDPC error correction module is a decoding module, the simulation module calls an LDPC decoding C algorithm model to run the reference input excitation transaction, the simulation module obtains a reference output transaction after running the reference input excitation transaction, and the reference output transaction is sent to the comparator.
And step S112, acquiring an actual output transaction of the LDPC error correction module through the output monitor, and sending the actual output transaction to the comparator.
Specifically, the output monitor monitors output information of the LDPC error correction module, encapsulates the output information into an actual output transaction, and sends the actual output transaction to the comparator.
In step S114, the actual output transaction is compared with the reference output transaction by the comparator, and a comparison result is obtained.
Specifically, the comparator judges whether the test case passes or not by comparing whether the actual output transaction is consistent with the reference output transaction or not.
According to the verification method of the LDPC error correction module, the test cases of the LDPC error correction module are obtained from the test case library; generating an input excitation transaction through a sequencer corresponding to a test case of the LDPC error correction module; driving, by a driver, the input stimulus transaction to an LDPC error correction module; acquiring a reference input excitation transaction through an input monitor, and sending the reference input excitation transaction to a simulation module; operating a reference input excitation transaction through a simulation module to obtain a reference output transaction, and sending the reference output transaction to a comparator; acquiring an actual output transaction of the LDPC error correction module through an output monitor, and sending the actual output transaction to a comparator; the comparison result is obtained by comparing the actual output transaction with the reference output transaction through the comparator, and the problems of low verification efficiency and poor universality of a verification system of the LDPC error correction module in the related technology are solved. By constructing a verification system of the LDPC error correction module based on the thought and the framework of the UVM verification methodology, the method has better universality and reusability for application scenes of different LDPC error correction modules; the verification system of the LDPC error correction module comprises a configuration interface and a data interface, and the interfaces of the LDPC error correction module are divided, so that the problem of code redundancy and error susceptibility caused by excessive signals in the same interface can be solved; the main method in the verification system of the LDPC error correction module is realized in the configuration interface and the data interface, and the design thought ensures that the verification platform only needs to pay attention to the interface part when in maintenance and transplantation; the design thought does not need to realize time sequence control in a driver and a monitor, thereby being beneficial to the realization of the acceleration of co-simulation hardware; the design of the test excitation library provides a referent design idea of test cases, and the idea can be applied to other modules to be tested.
When the module is verified, a complete test case is required, and optionally, before the test case of the LDPC error correction module is obtained from the test case library, the method further comprises: acquiring a function list of the LDPC error correction module, creating a plurality of first test cases according to functions in the function list, and storing the plurality of first test cases into a test case library; and/or acquiring interface information and register information of the LDPC error correction module, creating a plurality of second test cases according to the interface information and the register information, and storing the plurality of second test cases into a test case library; and/or obtaining abnormal condition information existing in the LDPC error correction module, creating a plurality of third test cases according to the abnormal condition information, and storing the plurality of third test cases into a test case library, wherein the abnormal condition at least comprises one of the following: data exception, register exception, protocol exception, timing exception, pressure test exception; and/or acquiring error code characteristics of the LDPC error correction module under different application scenes, creating a plurality of fourth test cases according to the error code characteristics under different application scenes, and storing the plurality of fourth test cases into a test case library; and/or determining the code which is not verified by the LDPC error correction module according to the coverage rate data result of the LDPC error correction module, designing a fifth test case according to the code which is not verified, and storing the fifth test case into a test case library.
For example, the function list of the LDPC error correction module includes a, b, c, d functions, according to each function, a first test case corresponding to the design is designed, according to interface information and register information of the LDPC error correction module, whether a test case corresponding to the function is missing is judged, in the case that missing is detected, a second test case corresponding to the design is designed according to the interface information and the register information, in consideration of abnormal conditions in the process of verifying the LDPC error correction module, a third test case corresponding to the design is designed according to historical verification experience, the LDPC error correction module has different error characteristics in different application scenarios, a fourth test case corresponding to the design is designed according to the error characteristics, the first test case, the second test case, the third test case and the fourth test case are verified in a verification system of the LDPC error correction module, the unverified function is determined by combining coverage rate data of the LDPC error correction module, and a fifth test case is designed in an oriented manner. By providing a referenceable test case design concept, the test case design concept can be applied to verification of other modules.
When the verification system of the LDPC error correction module starts to verify, the configuration of the related information of the verification matrix in the LDPC module needs to be completed first, and optionally, after the test cases of the LDPC error correction module are obtained from the test case library, the method further comprises: acquiring check matrix information; storing the check matrix information into an aggregation parameter class, and transmitting a pointer of the aggregation parameter class to a driver; and calling a first method in the configuration interface through a driver to drive the check matrix information in the aggregation parameter class into the LDPC error correction module so as to finish the initialization configuration of the LDPC error correction module.
Specifically, the check matrix information is obtained from the outside of the verification system of the LDPC error correction module, the check matrix information is stored in the aggregation parameter class, meanwhile, the pointer is sent to the driver, and the driver can call the check matrix information stored in the aggregation parameter class according to the pointer, so that the check matrix information is driven to the LDPC error correction module, and the LDPC error correction module completes initialization configuration through the check matrix information.
After the LDPC error correction module completes the initialization configuration, the simulation execution of the test case is started, and optionally, driving the input excitation transaction to the LDPC error correction module through the driver comprises: invoking a second method in the data interface by the driver to drive the input stimulus transaction to the LDPC error correction module; acquiring, by the input monitor, a reference input stimulus transaction includes: the method comprises the steps that input information of an LDPC error correction module is obtained through a third method in a data interface called by an input monitor, and the input information is packaged into a reference input excitation transaction; acquiring, by the output monitor, the actual output transaction generated by the LDPC error correction module includes: and the output monitor calls a fourth method of the data interface to acquire the actual output information generated by the LDPC error correction module, and encapsulates the actual output information into an actual output transaction.
Specifically, the second method may be a put_transfer method, the third method may be a get_in_transfer method, the fourth method may be a get_out_transfer method, the second method, the third method and the fourth method are defined in the data interface, the driver drives the input excitation transaction to the LDPC error correction module by calling the second method, the input monitor calls the third method to collect input information of the LDPC error correction module, encapsulates the input information into a reference input excitation transaction and sends the reference input excitation transaction to the simulation module, the LDPC error correction module runs the input information to obtain output information, and the output monitor calls the fourth method to collect the output information and encapsulates the output information into an actual output transaction and sends the actual output transaction to the comparator. The main method in the verification system is realized in the data interface, so that the verification system of the LDPC error correction module only needs to pay attention to the interface part when in maintenance and transplantation; meanwhile, time sequence control is not needed to be realized in a driver and a monitor, so that acceleration realization of co-simulation hardware is facilitated.
Running the reference input stimulus transaction after the simulation module receives the reference input stimulus transaction, optionally running the reference input stimulus transaction through the simulation module, the obtaining the reference output transaction comprising: under the condition that the LDPC error correction module is an encoding module, invoking an LDPC encoding algorithm model in the simulation module through a direct programming interface, and running a reference input excitation transaction in the LDPC encoding algorithm model to obtain a reference output transaction; and under the condition that the LDPC error correction module is a decoding module, calling the LDPC decoding algorithm model in the simulation module through a direct programming interface, and operating the reference input excitation transaction in the LDPC decoding algorithm model to obtain the reference output transaction.
Specifically, the LDPC error correction module is divided into an encoding module and a decoding module, and the simulation module calls a corresponding algorithm model through the DPI interface to run a reference input excitation transaction according to the type of the verified LDPC error correction module, so as to obtain a reference output transaction.
The embodiment of the application also provides a verification device of the LDPC error correction module, and the verification device of the LDPC error correction module can be used for executing the verification method for the LDPC error correction module. The following describes a verification device of an LDPC error correction module provided by an embodiment of the present application.
Fig. 3 is a schematic diagram of a verification apparatus of an LDPC error correction module according to an embodiment of the present application. As shown in fig. 3, the apparatus includes:
the first obtaining unit 10 is configured to obtain a test case of the LDPC error correction module from a test case library.
The generating unit 20 is configured to generate an input excitation transaction by using a sequencer corresponding to a test case of the LDPC error correction module.
And a driving unit 30 for driving the input excitation transaction to the LDPC error correction module through the driver.
The second obtaining unit 40 is configured to obtain the reference input excitation transaction through the input monitor, and send the reference input excitation transaction to the simulation module.
The operation unit 50 is configured to operate the reference input excitation transaction through the simulation module, obtain the reference output transaction, and send the reference output transaction to the comparator.
The third obtaining unit 60 is configured to obtain, by using the output monitor, an actual output transaction of the LDPC error correction module, and send the actual output transaction to the comparator.
And a comparing unit 70 for comparing the actual output transaction with the reference output transaction by a comparator to obtain a comparison result.
According to the verification device for the LDPC error correction module provided by the embodiment of the application, the test cases of the LDPC error correction module are obtained from the test case library through the first obtaining unit 10. The generating unit 20 generates the input excitation transaction by a sequencer corresponding to the test case of the LDPC error correction module. The driving unit 30 drives the input excitation transaction to the LDPC error correction module through a driver. The second acquisition unit 40 acquires the reference input excitation transaction by the input monitor and sends the reference input excitation transaction to the simulation module. The operation unit 50 operates the reference input excitation transaction through the simulation module, obtains the reference output transaction, and transmits the reference output transaction to the comparator. The third acquisition unit 60 acquires an actual output transaction of the LDPC error correction module through the output monitor, and transmits the actual output transaction to the comparator. The comparison unit 70 obtains a comparison result by comparing the actual output transaction with the reference output transaction through a comparator, and solves the problems of low verification efficiency and poor universality of the verification system of the LDPC error correction module in the related art. By constructing a verification system of the LDPC error correction module based on the thought and the framework of the UVM verification methodology, the method has better universality and reusability for application scenes of different LDPC error correction modules; the verification system of the LDPC error correction module comprises a configuration interface and a data interface, and the interfaces of the LDPC error correction module are divided, so that the problem of code redundancy and error susceptibility caused by excessive signals in the same interface can be solved; the main method in the verification system of the LDPC error correction module is realized in the configuration interface and the data interface, and the design thought ensures that the verification platform only needs to pay attention to the interface part when in maintenance and transplantation; the design thought does not need to realize time sequence control in a driver and a monitor, thereby being beneficial to the realization of the acceleration of co-simulation hardware; the design of the test excitation library provides a referent design idea of test cases, and the idea can be applied to other modules to be tested.
Optionally, in the verification device of the LDPC error correction module provided by the embodiment of the present application, the device further includes: the first test case acquisition unit is used for acquiring a function list of the LDPC error correction module, creating a plurality of first test cases according to functions in the function list, and storing the plurality of first test cases into the test case library; the second test case acquisition unit is used for acquiring interface information and register information of the LDPC error correction module, creating a plurality of second test cases according to the interface information and the register information, and storing the plurality of second test cases into the test case library; the third test case acquisition unit is used for acquiring abnormal condition information of the LDPC error correction module, creating a plurality of third test cases according to the abnormal condition information, and storing the plurality of third test cases into the test case library, wherein the abnormal condition at least comprises one of the following: data exception, register exception, protocol exception, timing exception, pressure test exception; the fourth test case acquisition unit is used for acquiring error code characteristics of the LDPC error correction module in different application scenes, creating a plurality of fourth test cases according to the error code characteristics in different application scenes, and storing the plurality of fourth test cases into the test case library; the fifth test case acquisition unit is used for determining codes which are not verified by the LDPC error correction module according to the coverage rate data result of the LDPC error correction module, designing the fifth test case according to the codes which are not verified, and storing the fifth test case into the test case library.
Optionally, in the verification device of the LDPC error correction module provided by the embodiment of the present application, the device further includes: a fourth acquisition unit for acquiring check matrix information; the storage unit is used for storing the check matrix information into the aggregation parameter class and transmitting a pointer of the aggregation parameter class to the driver; and the configuration unit is used for driving the check matrix information in the aggregation parameter class into the LDPC error correction module by calling a first method in the configuration interface through a driver so as to complete the initialization configuration of the LDPC error correction module.
Optionally, in the verification device of the LDPC error correction module provided in the embodiment of the present application, the driving unit 30 includes: the driving module is used for driving the input excitation transaction to the LDPC error correction module by calling a second method in the data interface through the driver; the second acquisition unit 40 includes: the first acquisition module is used for acquiring the input information of the LDPC error correction module by calling a third method in the data interface through the input monitor and packaging the input information into a reference input excitation transaction; the third acquisition unit 60 includes: the second acquisition module is used for acquiring the actual output information generated by the LDPC error correction module through a fourth method of calling the data interface by the output monitor, and packaging the actual output information into an actual output transaction.
Optionally, in the verification device of the LDPC error correction module provided in the embodiment of the present application, the operation unit 50 includes: the first operation module is used for calling the LDPC coding algorithm model in the simulation module through the direct programming interface under the condition that the LDPC error correction module is the coding module, and operating the reference input excitation transaction in the LDPC coding algorithm model to obtain the reference output transaction; and the second operation module is used for calling the LDPC decoding algorithm model in the simulation module through the direct programming interface under the condition that the LDPC error correction module is a decoding module, and operating the reference input excitation transaction in the LDPC decoding algorithm model to obtain the reference output transaction.
The verification device of the LDPC error correction module includes a processor and a memory, and the first acquisition unit 10, the generation unit 20, the driving unit 30, the second acquisition unit 40, the operation unit 50, the third acquisition unit 60, the comparison unit 70, and the like are stored in the memory as program units, and the processor executes the program units stored in the memory to implement corresponding functions.
The processor includes a kernel, and the kernel fetches the corresponding program unit from the memory. The kernel can be provided with one or more than one, the universality of a verification system of the LDPC error correction module is enhanced by adjusting kernel parameters, and the efficiency of verifying the LDPC error correction module is improved.
The memory may include non-volatile memory in a computer readable medium, random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory LDPC error correction module.
The embodiment of the application also provides a nonvolatile storage medium, which comprises a stored program, wherein the program is used for controlling equipment where the nonvolatile storage medium is located to execute an LDPC error correction module verification method when running.
The embodiment of the application also provides electronic equipment, which comprises a processor and a memory; the memory stores computer readable instructions, and the processor is configured to execute the computer readable instructions, where the computer readable instructions execute a method for verifying an LDPC error correction module. The electronic device herein may be a server, a PC, a PAD, a mobile phone, etc.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, etc., such as Read Only Memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.
Claims (11)
1. An authentication system of an LDPC error correction module, comprising:
the test case library is used for storing a plurality of test cases of the LDPC error correction module;
the sequencer is used for generating an input excitation transaction according to each test case respectively, wherein each sequencer corresponds to one test case;
The input agent comprises a sequencer, a driver and an input monitor, wherein the sequencer is connected with the sequencer and used for acquiring the input excitation transaction sent by the sequencer, the driver is connected with the sequencer and used for driving the input excitation transaction to the LDPC error correction module, the input monitor is used for converting input information of the LDPC error correction module into a reference input excitation transaction and sending the reference input excitation transaction to the simulation module, the input excitation transaction contains the input information, and the LDPC error correction module generates actual output information based on the input information;
the simulation module is connected with an input monitor in the input agent and used for acquiring the reference input excitation transaction, generating a reference output transaction based on the reference input excitation transaction and sending the reference output transaction to the comparator;
an output agent including an output monitor for packaging the actual output information of the LDPC error correction module into an actual output transaction and transmitting the actual output transaction to the comparator;
and the comparator is connected with the simulation module and an output monitor in the output agent and is used for comparing the actual output transaction with the reference output transaction to obtain a comparison result.
2. The system of claim 1, wherein the system further comprises:
And the aggregation parameter class is used for storing check matrix information, wherein the check matrix information is used for initializing the LDPC error correction module.
3. The system of claim 2, wherein the system further comprises:
And one end of the configuration interface is connected with the LDPC error correction module, and the other end of the configuration interface is connected with the driver and is used for providing a first method, wherein the driver calls the first method to drive the check matrix information to the LDPC error correction module so as to complete the initialization configuration of the LDPC error correction module.
4. The system of claim 1, wherein the system further comprises:
The data interface is used for providing a second method, a third method and a fourth method, wherein the driver calls the second method to drive the input excitation transaction to the LDPC error correction module, the input monitor calls the third method to acquire the input information of the LDPC error correction module, the input information is packaged into the reference input excitation transaction, and the output monitor calls the fourth method to acquire the actual output information and package the actual output information into the actual output transaction.
5.A verification method of an LDPC error correction module, applied to the verification system of an LDPC error correction module as claimed in any one of claims 1 to 4, comprising:
acquiring test cases of the LDPC error correction module from a test case library;
generating an input excitation transaction through a sequencer corresponding to a test case of the LDPC error correction module;
driving, by a driver, the input stimulus transaction to the LDPC error correction module;
Acquiring the reference input excitation transaction through an input monitor, and sending the reference input excitation transaction to a simulation module;
operating the reference input excitation transaction through the simulation module to obtain a reference output transaction, and sending the reference output transaction to a comparator;
Acquiring an actual output transaction of the LDPC error correction module through an output monitor, and sending the actual output transaction to the comparator;
And comparing the actual output transaction with the reference output transaction through the comparator to obtain a comparison result.
6. The method of claim 5, wherein prior to retrieving test cases of the LDPC error correction module from the test case library, the method further comprises:
Acquiring a function list of the LDPC error correction module, creating a plurality of first test cases according to functions in the function list, and storing the plurality of first test cases into the test case library; and/or
Acquiring interface information and register information of the LDPC error correction module, creating a plurality of second test cases according to the interface information and the register information, and storing the plurality of second test cases into the test case library; and/or
Acquiring abnormal condition information existing in the LDPC error correction module, creating a plurality of third test cases according to the abnormal condition information, and storing the plurality of third test cases into the test case library, wherein the abnormal condition at least comprises one of the following: data exception, register exception, protocol exception, timing exception, pressure test exception; and/or
Acquiring error code characteristics of the LDPC error correction module under different application scenes, creating a plurality of fourth test cases according to the error code characteristics under the different application scenes, and storing the fourth test cases into the test case library; and/or
And determining a code which is not verified by the LDPC error correction module according to a coverage rate data result of the LDPC error correction module, designing a fifth test case according to the code which is not verified, and storing the fifth test case into the test case library.
7. The method of claim 5, wherein after obtaining test cases of the LDPC error correction module from the test case library, the method further comprises:
Acquiring check matrix information;
storing the check matrix information into an aggregation parameter class, and transmitting a pointer of the aggregation parameter class to the driver;
And calling a first method in a configuration interface through the driver to drive the check matrix information in the aggregation parameter class into the LDPC error correction module so as to finish the initialization configuration of the LDPC error correction module.
8. The method of claim 5, wherein driving the input stimulus transaction to the LDPC error correction module by a driver comprises: invoking a second method in a data interface by a driver to drive the input stimulus transaction to the LDPC error correction module;
Acquiring the reference input stimulus transaction by the input monitor includes: invoking a third method in the data interface through the input monitor to acquire the input information of the LDPC error correction module, and packaging the input information into the reference input excitation transaction;
Acquiring, by an output monitor, an actual output transaction generated by the LDPC error correction module includes: and calling a fourth method of the data interface through an output monitor to acquire actual output information generated by the LDPC error correction module, and packaging the actual output information into an actual output transaction.
9. The method of claim 5, wherein running the reference input stimulus transaction through the simulation module to obtain a reference output transaction comprises:
Under the condition that the LDPC error correction module is an encoding module, invoking an LDPC encoding algorithm model in the simulation module through a direct programming interface, and running the reference input excitation transaction in the LDPC encoding algorithm model to obtain a reference output transaction;
And under the condition that the LDPC error correction module is a decoding module, calling an LDPC decoding algorithm model in the simulation module through a direct programming interface, and operating the reference input excitation transaction in the LDPC decoding algorithm model to obtain a reference output transaction.
10. A non-volatile storage medium, characterized in that the non-volatile storage medium comprises a stored program, wherein the program, when run, controls a device in which the non-volatile storage medium is located to perform the method of verifying an LDPC error correction module according to any one of claims 5 to 9.
11. An electronic device comprising a processor and a memory, the memory having stored therein computer readable instructions for executing the computer readable instructions, wherein the computer readable instructions when executed perform the method of validating an LDPC error correction module of any one of claims 5 to 9.
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