CN103617811B - Error correction circuit of SRAM type memory - Google Patents
Error correction circuit of SRAM type memory Download PDFInfo
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- CN103617811B CN103617811B CN201310642317.0A CN201310642317A CN103617811B CN 103617811 B CN103617811 B CN 103617811B CN 201310642317 A CN201310642317 A CN 201310642317A CN 103617811 B CN103617811 B CN 103617811B
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Abstract
The invention provides an error correction circuit of an SRAM type memory, which comprises: the device comprises an encoding module, a first transmission gate module, a second transmission gate module, an exclusive OR operation module and an error correction circuit module. The coding module is used for decoding operation, control signals are added, and time division multiplexing is carried out on the coding operation and the decoding operation. The circuit area is small, and meanwhile, the memory is fast in reading and writing time and accurate in error correction.
Description
Technical field
The present invention relates to memory data reliability, more particularly to ensure the reliable circuit of memory read/write data.
Background technology
Many is well known, and high energy particle can cause the multiple units of VLSI device insides to produce instantaneously in space radiation environment
Mistake, in SRAM type memory, the performance that this multiple units produce transient error is Multiple-bit upsets.Due to space environment
In particle distribution have high-energy small throughput the characteristics of, therefore occur memory Multiple-bit upsets mainly due to single high energy
Particle hits device sensitizing range, and the electric charge of generation occurs diffusion, causes multiple units of device transient error occur.
With continuing to develop for integrated circuit fabrication process, the process of SRAM structure devices constantly reduces, core electricity
Pressure is constantly reduced, therefore this wrong probability of appearance gradually increases.Data manipulation generally to SRAM type memory device is all
Carried out by basic byte, therefore actual influence application is oneself single basic Multiple-bit upsets mistake（SMU）.
It is currently mostly the SMU that memory is solved the problems, such as by following several method：One is the carry out technique in device level
Reinforce, two be that Logic adjacent position is physically carried out into scattering device, and three be to carry out many dislocations by BISC+SEC-DED methods
Correction, four be the detection and correction that many dislocations are carried out by the method for coding, and first three methods are required for again device grading by mistake
Row protection Design, so that the complexity for bringing device layout to connect up, adds the power consumption of device, while adding device
Production cost.Therefore it is many in the prior art that system-level protection is carried out to SRAM type memory using coding method.
Hamming code is a kind of conventional error correction/encoding method, and it has been obtained extensively with less redundancy check bit
Application.Traditional Hamming code, information bit is not equal to 2 power, it is therefore desirable to shorten, and deletes partial information position, could widely
Using on a memory.As shown in figure 1, existing shortening Hamming code coding circuit and decoding circuit are separated, electricity is so added
The expense of road surface product.On the other hand, SRAM can not be read while write, and caused the independence of coding circuit and decoding circuit and can not be improved reading
Writing rate.
The content of the invention
The technical problem to be solved in the present invention is that a kind of circuit area of design is small, access time is fast, the accurate SRAM of error correction
The error correction circuit of type memory
The present invention provides a kind of error correction circuit of SRAM type memory, wherein, including：
Coding module, for data-signal computing to be generated into check bit；
First transmission gate module, the verification with information bit is generated according to the check bit and the computing of write operation control signal
Position；
Second transmission gate module and xor operation module, generate according to the check bit and read operation control signal computing and examine
Test vector；
Error correction circuit module, searches error bit, and carry out error-correcting decoding according to verification vector.
It is preferred that, it is Hamming code coding rule inside the coding module.
It is preferred that, the input connection data signal input and its inversion signal input of the coding module are described
The check bit of the output end output computing generation of coding module.
It is preferred that, two inputs of first transmission gate connect the output end of the coding module and write behaviour respectively
Make control signal end, the check bit of the adjoint information bit of output end output of first transmission gate.
It is preferred that, two inputs of the second transmission gate module connect the output end of the coding module respectively
And read operation control signal end, output end, data signal input and its inversion signal input of second transmission gate
Connect the input of the xor operation module, the output end output verification vector of the xor operation module.
It is preferred that, the input of the error correction circuit module connects the output end of the xor operation module, the error correction
The output end connection data signal input and its inversion signal input of circuit module.
Decoded operation is carried out using coding module, control signal is added, coding and decoded operation are time-multiplexed.
If memory is data write operation, the check bit and write operation control signal for being exported coding module using the first transmission gate
Generation is exported with the check bit of information bit, then now coding module and the first transmission gate and write operation signal equivalent to
The effect of coding circuit；If memory is data read operation, the second transmission gate module and xor operation module will encode mould
The check bit of block output examines bit vector with read operation control signal computing generation, and coordinates the completion error correction of error correction circuit module to translate
Code.Coding module has now been multiplexed, it has been simultaneously used in coding and decoding circuit so that circuit area is small, has been deposited simultaneously
Reservoir access time is fast, error correction is accurate.
Brief description of the drawings
The present invention is described in further detail with reference to the accompanying drawings and detailed description：
Fig. 1 is a kind of circuit diagram of SRAM type memory in the prior art；
Fig. 2 is the circuit diagram of the embodiment 1 of the error correction circuit of SRAM type memory of the present invention.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail, make the above and other purpose of the present invention, feature and advantage will become apparent from.Complete
Identical reference indicates identical part in portion's accompanying drawing.Not deliberately accompanying drawing drawn to scale, it is preferred that emphasis is show this hair
Bright purport.
As shown in Fig. 2 the present invention provides a kind of error correction circuit of SRAM type memory, wherein, including：Coding module
Encoder, the first transmission gate module TG, the second transmission gate module and xor operation module TG＆XOR, error correction circuit module
Locating error。
In the present embodiment, coding module Encoder input connection data-signal O inputs and its inversion signal OB
Input, coding module Encoder output end exports the verification of computing generation to the first transmission gate and the second transmission gate；First
Transmission gate TG two inputs difference connect coding module Encoder output end and write operation control signal Write ends,
The check bit of the first transmission gate TG adjoint information bit of output end output；Second transmission gate module TG two inputs connect respectively
Connect connect coding module Encoder output end and read operation control signal Read ends, the second transmission gate TG output end, number
Connect xor operation module XOR input, the xor operation respectively according to signal input part O and its inversion signal OB inputs
The output end output verification vector of module gives error correction circuit module Locating error, error correction circuit module Locating
Error output end connection data-signal O inputs and its inversion signal OB inputs.
The operation principle of the present embodiment：
For the linear block codes including Hamming code, a k is tieed up into message vector and is multiplied by k × n matrix, one is generated
N ties up code word（word）
Such as（38,32）32 × 38 dimension generator matrixes for shortening Hamming code are as follows：
G=[
11000010000000000000000000000000000000;
10100001000000000000000000000000000000;
01100000100000000000000000000000000000;
11100000010000000000000000000000000000;
10010000001000000000000000000000000000;
01010000000100000000000000000000000000;
11010000000010000000000000000000000000;
00110000000001000000000000000000000000;
10110000000000100000000000000000000000;
01110000000000010000000000000000000000;
11110000000000001000000000000000000000;
10001000000000000100000000000000000000;
01001000000000000010000000000000000000;
11001000000000000001000000000000000000;
00101000000000000000100000000000000000;
10101000000000000000010000000000000000;
01101000000000000000001000000000000000;
11101000000000000000000100000000000000;
00011000000000000000000010000000000000;
10011000000000000000000001000000000000;
01011000000000000000000000100000000000;
11011000000000000000000000010000000000;
00111000000000000000000000001000000000;
10111000000000000000000000000100000000;
01111000000000000000000000000010000000;
11111000000000000000000000000001000000;
10000100000000000000000000000000100000;
01000100000000000000000000000000010000;
11000100000000000000000000000000001000;
00100100000000000000000000000000000100;
10100100000000000000000000000000000010;
01100100000000000000000000000000000001
];
（38,32）The check matrix for shortening Hamming code is as follows：
H=[
10000011011010101101010101010101101010;
01000010110110011011001100110011011001;
00100001110001111000111100001111000111;
00010000001111111000000011111111000000;
00001000000000000111111111111111000000;
00000100000000000000000000000000111111
];
During decoding, n is tieed up into the transposition that code word is multiplied by check matrix（N × m is tieed up）M dimension verification subvectors are generated, wherein m is school
Test bits number.
Syndrome computations mode：s=rHT；Wherein r ties up code word for the n read.The wherein shape of generator matrix and check matrix
Formula is met：
Gk×n=[PIk],
Hm×n=[ImPT].
To the code word that any one is generated by generator matrix G, its low level is check bit, and a high position is information bit.If v is write-in
Shi Shengcheng code word, then have：
v=(s0,s1,...sm-1,u0,u1,...,uk-1)
By the form of code word v, generator matrix G and check matrix H it can be found that code word be multiplied by H-shaped into new syndrome,
Practically equal to k information bits of reading on original syndrome that k information vectors are write to memory generation, XOR to regenerate
Syndrome.Therefore decoded operation can be carried out using original coding circuit.Control signal is added, is grasped to encoding and decoding
As being time-multiplexed.
Therefore, in embodiment, input data signal O and its inversion signal the OB high k encoded modules of information bit
Encoder generates check bit.If write-in storage operation, then write operation control signal write is high level, is used as one
Signal is enabled, the first transmission gate TG modules are controlled, the check bit of the check bit that coding module is exported as adjoint information bit is defeated
Go out and be stored in memory, m altogether；If read operation, then read operation control signal read is height, coding module Encoder
The check bit of output is by one high effective transmission gate and the xor operation module for reading to enable that signal is controlled, with original input number
It is believed that low m of number O and its inversion signal OB check bit XORs carried, generation one is used for error correction circuit module Locating
Error verifies bit vector.Error correction circuit module finds a certain bit errors position according to verification vector, make input data signal O and
A certain information bit in high k of its inversion signal OB is overturn.The high k information bit of final output.
Decoded operation is carried out using coding module, control signal is added, coding and decoded operation are time-multiplexed.
If memory is data write operation, the check bit and write operation control signal for being exported coding module using the first transmission gate
Generation is exported with the check bit of information bit, then now coding module and the first transmission gate and write operation signal equivalent to
The effect of coding circuit；If memory is data read operation, the second transmission gate module and xor operation module will encode mould
The check bit of block output examines bit vector with read operation control signal computing generation, and coordinates the completion error correction of error correction circuit module to translate
Code.Coding module has now been multiplexed, it has been simultaneously used in coding and decoding circuit so that circuit area is small, has been deposited simultaneously
Reservoir access time is fast, error correction is accurate.
Many details are elaborated in the above description to fully understand the present invention.But above description is only
Presently preferred embodiments of the present invention, the invention can be embodied in many other ways as described herein, therefore this
Invention is not limited by specific implementation disclosed above.Any those skilled in the art are not departing from the technology of the present invention simultaneously
In the case of aspects, all make many possible to technical solution of the present invention using the methods and techniques content of the disclosure above
Change and modify, or be revised as the equivalent embodiment of equivalent variations.Every content without departing from technical solution of the present invention, according to this
The technical spirit of invention still falls within skill of the present invention to any simple modifications, equivalents, and modifications made for any of the above embodiments
In the range of the protection of art scheme.
Claims (2)
1. a kind of error correction circuit of SRAM type memory, it is characterised in that including：
Coding module, for data-signal computing to be generated into check bit；
First transmission gate module, the check bit with information bit is generated according to the check bit and the computing of write operation control signal；
Second transmission gate module and xor operation module, according to the check bit and read operation control signal computing generation examine to
Amount；
Error correction circuit module, searches error bit, and carry out error-correcting decoding according to inspection vector；
Wherein, if the memory is data write operation, the verification for being exported coding module using the first transmission gate module
Position generates with write operation control signal and exported with the check bit of information bit；If memory is data read operation, the
The check bit that two transmission gate modules and xor operation module export coding module is generated with read operation control signal computing and examined
Vector, and coordinate error correction circuit module to complete error-correcting decoding；The coding module input connection data signal input and
Its inversion signal input, the check bit of the output end output computing generation of the coding module；The first transmission gate module
Two inputs connect the output end and write operation control signal end of the coding module, the first transmission gate mould respectively
The check bit of the adjoint information bit of output end output of block；It is Hamming code coding rule inside the coding module；Described second passes
Two inputs of defeated door module connect output end and the read operation control signal end of the coding module, described second respectively
Output end, data signal input and its inversion signal input of transmission gate module connect the input of the xor operation module
Vector is examined in end, the output end output of the xor operation module.
2. the error correction circuit of SRAM type memory according to claim 1, it is characterised in that the error correction circuit module
Input connects the output end of the xor operation module, the output end connection data signal input of the error correction circuit module
And its inversion signal input.
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| CN102306213A (en) * | 2011-07-19 | 2012-01-04 | 西安电子科技大学 | Anti-single particle irradiating method and anti-single particle irradiating system based on frame data processing |
| CN102651240A (en) * | 2011-02-25 | 2012-08-29 | 阿尔特拉公司 | Error detection and correction circuitry |
| CN202856718U (en) * | 2012-07-20 | 2013-04-03 | 天津工大瑞工光电技术有限公司 | Multiple bits up set resistant RS code error detection and correction system based on FPGA |
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| US20080256419A1 (en) * | 2007-04-13 | 2008-10-16 | Microchip Technology Incorporated | Configurable Split Storage of Error Detecting and Correcting Codes |
| CN102682826A (en) * | 2011-03-10 | 2012-09-19 | 中国科学院微电子研究所 | Coding and decoding storage device and method for multiplexing coder |
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| CN102651240A (en) * | 2011-02-25 | 2012-08-29 | 阿尔特拉公司 | Error detection and correction circuitry |
| CN102306213A (en) * | 2011-07-19 | 2012-01-04 | 西安电子科技大学 | Anti-single particle irradiating method and anti-single particle irradiating system based on frame data processing |
| CN202856718U (en) * | 2012-07-20 | 2013-04-03 | 天津工大瑞工光电技术有限公司 | Multiple bits up set resistant RS code error detection and correction system based on FPGA |
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