[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN101882609A - 用于半导体封装体的引线框 - Google Patents

用于半导体封装体的引线框 Download PDF

Info

Publication number
CN101882609A
CN101882609A CN2009101405659A CN200910140565A CN101882609A CN 101882609 A CN101882609 A CN 101882609A CN 2009101405659 A CN2009101405659 A CN 2009101405659A CN 200910140565 A CN200910140565 A CN 200910140565A CN 101882609 A CN101882609 A CN 101882609A
Authority
CN
China
Prior art keywords
lead frame
frame structure
shallow grooves
tube core
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2009101405659A
Other languages
English (en)
Inventor
姚晋钟
白志刚
骆军华
宋美江
朱红
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to CN2009101405659A priority Critical patent/CN101882609A/zh
Priority to US12/753,118 priority patent/US20100283135A1/en
Publication of CN101882609A publication Critical patent/CN101882609A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0616Random array, i.e. array with no symmetry
    • H01L2224/06164Random array, i.e. array with no symmetry covering only portions of the surface to be connected
    • H01L2224/06165Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明涉及用于半导体封装体的引线框。引线框包括引线框结构,其具有管芯支撑区域和多个电接触区域。引线框具有形成在该引线框结构表面上的浅凹槽。

Description

用于半导体封装体的引线框
技术领域
本发明涉及集成电路(IC)的封装,并且更具体地涉及用于半导体封装体的引线框。
背景技术
来自半导体封装体引线框的模塑料的分层(delamination)是不期望的,因为它可以致使封装体失效。可以由引线框分层引起的失效机理包括接合拉起(bond lifting)、跟部开裂(heel cracking)以及断线。引线框分层还可以导致封装体开裂。因此,期望具有可以减少引线框分层发生的引线框。
附图说明
当结合附图阅读时将更好理解本发明优选实施例的以下详细说明。本发明由附图以实例的方式来示出,并且不受附图的限制,在附图中相似的附图标记表示类似的元件。应当理解,附图没有按比例绘制,并且为了便于理解本发明已经被简化。
图1是根据本发明实施例的引线框的示意性顶部平面图;
图2是沿着线X-X的图1的引线框的一部分的放大截面图;
图3是根据本发明另一实施例的半导体封装体的示意性顶部平面局部剖视图;以及
图4是沿着图3中的线Y-Y的引线框的一部分的放大截面图。
具体实施方式
下面结合附图阐述的详细说明意图作为本发明当前优选实施例的描述,而不意图表示可以实现本发明的唯一形式。应当理解,可以由不同的实施例来实现相同的或者等同的功能,所述不同的实施例意图包含在本发明的精神和范围内。在附图中,自始至终相似的标记用来表示相似的元件。
本发明提供了一种引线框,其包括具有管芯(die)支撑区域和多个电接触区域的引线框结构。在一个实施例中,在该引线框结构的表面上形成浅凹槽。在另一实施例中,在该引线框结构的表面上至少部分地围绕该引线框结构的多个关键部分中的相应的关键部分形成多个浅凹槽。在又一实施例中,在该引线框结构的表面上形成浅凹槽。将集成电路(IC)管芯附接于管芯支撑区域并且电连接到电接触区域。该引线框结构的一部分以及该IC管芯由模塑料密封。
现在参考图1,其示出了引线框10的示意性顶部平面图。引线框10包括引线框结构12,引线框结构12具有管芯支撑区域14和多个电接触区域16。在引线框结构12的表面上至少部分地围绕该引线框结构12的多个关键部分20中的相应的关键部分形成多个浅凹槽18。
引线框10可以由铜或者金属合金板或条经由刻蚀或者冲压来形成,如现有技术中已知的。引线框10可以具有约120微米(μm)到约770μm之间的厚度,并且可以镀有金属或者金属合金。使管芯支撑区域14的尺寸和形状适合于接收集成电路(IC)管芯。管芯的尺寸以及因此管芯支撑区域14的尺寸可以根据在其中的电路的功能而变化。如本领域技术人员将理解的,本发明不由管芯支撑区域14的尺寸和形状来限制。电接触区域16(有时也被称为引线指)通常围绕引线框10的周界放置,或者沿着引线框10的一个或多个边放置。如可以在图1中看到的,电接触区域16的长度可以变化。例如,最靠近或者邻近于管芯支撑区域14的电接触区域16可以比更远离管芯支撑区域14的电接触区域短。然而,在其它实施例中,电接触区域16可以具有一致的长度。
现在参考图2,示出了沿着图1中的线X-X的引线框10的一部分的放大截面图。如图2所示,将浅凹槽18形成为引线框结构12的关键部分20中的沟槽。
在引线框结构12的表面上提供浅凹槽18增大了引线框10和随后淀积于其上的密封材料之间的接触面积。接触面积的增大有助于改进引线框10和密封材料之间的粘附性。另外,浅凹槽18有助于容纳在引线框10和密封材料之间的任何初始的分层。
可以将浅凹槽18形成为具有在引线框结构12的厚度的约百分之十五(15%)到约30%之间的深度,并且更优选地具有在引线框结构12的厚度的约20%到约25%之间的深度。例如,在引线框结构12具有约510μm的厚度时,可以将浅凹槽18形成为具有在约100微米(μm)到约130μm之间的深度。
浅凹槽18可以具有在约0.1毫米(mm)到约0.25mm之间的宽度。有利地,相对于浅凹槽18形成于其中的引线框10的特定部分20的表面面积,浅凹槽18的宽度较窄,这允许浅凹槽18的布局上的灵活性。例如,浅凹槽18不限于直的沟槽设计,而是可以由不同的形状形成。浅凹槽18的宽度的狭窄也允许将浅凹槽18安置在引线框10的小的关键区域中。
在一个实施例中,可以通过使用刻蚀掩模刻蚀来形成浅凹槽18。可以通过改变刻蚀掩模的孔径宽度来控制浅凹槽18的深度。减小刻蚀掩模的孔径宽度来实现更浅的刻蚀深度。在可替代实施例中也可以通过激光切割、冲孔或者其它已知的引线框制造工艺来形成浅凹槽18。
如图2所示,可以将浅凹槽18形成在引线框结构12的被刻蚀部分22上方并且在与引线框结构12的被刻蚀部分22相对的表面上。由于相对于引线框10的厚度而言凹槽18较浅,因此这是可能的。可以同时形成浅凹槽18和被刻蚀了一半的部分22。
虽然图2示出了将浅凹槽18形成在引线框结构12的一个(1)表面上,并且在被刻蚀了一半的部分22上方,但是应当理解,可以将浅凹槽18形成在引线框结构12的两个表面上,并且在引线框结构12上的相同位置处。
再次参考图1,关键部分20包括一个或多个管芯接合区域(即,管芯支撑区域14)、引线接合区域(即,电接触区域16)、湿气敏感区域(例如,拉杆(tie-bar)区域)以及在其处引线框分层能影响封装体性能的引线框结构12的其它区域。至少部分地在关键部分20附近提供浅凹槽18有助于防止分层穿透到半导体封装体的关键区域中,由此改进封装体的稳健性。
现在参考图3,示出了半导体封装体50的示意性顶部平面局部剖视图。半导体封装体50包括引线框结构52,引线框结构52具有管芯支撑区域54和多个电接触区域56。在引线框结构52的表面上至少部分地围绕该引线框结构52的多个关键部分60中相应的关键部分形成多个浅凹槽58。将集成电路(IC)管芯62附接于管芯支撑区域54并且经由多个引线64电连接到电接触区域56。该引线框结构52的一部分以及该IC管芯62由模塑料66密封。
半导体封装体50可以是功率四方扁平无引脚(PQFN)封装体或者需要引线框的任何其它封装体类型。
引线框结构52与图1和图2的引线框结构12类似,除了本实施例的浅凹槽58的布置不同。因此,将省略类似元件的详细说明。然而,布局上的差异描述如下。
现在参考图4,示出了沿着图3中的线Y-Y的引线框结构52的关键部分60的放大截面图。如图4所示,在本实施例中将浅凹槽58形成为在关键部分60的边缘处的台阶。同样如图4所示,将浅凹槽58中的一个形成在引线框结构52的被刻蚀了一半的部分68上方,并且在与引线框结构52的被刻蚀了一半的部分68相对的表面上。
再次参考图3,IC管芯62可以是任何类型的电路,例如,数字信号处理器(DSP)或者专用功能电路。IC管芯62不限于特定技术(例如CMOS),也不源自任何特定的晶片(wafer)技术。此外,本发明能够适应各种尺寸的IC管芯;例如,在一个实施例中,IC管芯62的尺寸可以为约3mm乘以约5mm。
引线64可以由金(Au)、铜(Cu)、铝(Al)或者其它如现有技术中已知的并且市场上可买到的导电材料制成。已知的引线接合工艺可以用来形成电连接件。
可以执行公知的密封工艺(例如,注射成型)来密封IC管芯62和引线64。模塑料66可以包含公知的市场上可买到的成型材料,例如塑料或者环氧树脂。
如可以从图1和图3看到的,浅凹槽18和58不限于直的沟槽设计。相反,根据浅凹槽18和58意图保护的关键区域来形成该浅凹槽18和58的形状。
如从前述讨论中显而易见的,本发明以在引线框结构表面上的浅凹槽的形式提供具有改进的模塑料堵塞和分层停止特征的引线框和半导体封装体。由于浅凹槽的尺寸较小,因此可以将它们形成于引线框的关键区域中,其中在该关键区域处间隔是约束。因此,本发明能够对引线框的关键区域提供改进的分层保护。
为了示例和说明起见已经给出了本发明优选实施例的描述,但是该描述不意图是穷举的或者将本发明限于所公开的形式。本领域技术人员将明白,在不脱离其宽的发明构思的情况下可以对上述实施例进行改动。因此,应当理解,本发明不限于所公开的具体实施例,而是覆盖在如由所附权利要求所限定的本发明的精神和范围内的修改。

Claims (12)

1.一种引线框,包含:
引线框结构,该引线框结构具有管芯支撑区域和多个电接触区域,其中在所述引线框结构的表面上至少部分地围绕所述引线框结构的多个关键部分中的相应的关键部分形成有多个浅凹槽。
2.根据权利要求1的引线框,其中所述关键部分包含管芯接合区域、引线接合区域和湿气敏感区域中的至少一个。
3.根据权利要求2的引线框,其中所述浅凹槽被形成为在所述关键部分的边缘处的台阶。
4.根据权利要求1的引线框,其中所述浅凹槽被形成为具有所述引线框结构的厚度的约15%到约30%之间的深度。
5.根据权利要求1的引线框,其中所述浅凹槽被形成在所述引线框结构的被刻蚀部分上方,并且在与所述引线框结构的被刻蚀部分相对的表面上。
6.根据权利要求1的引线框,其中所述浅凹槽具有约0.1mm到约0.25mm之间的宽度。
7.一种半导体封装体,包含:
引线框结构,该引线框结构具有管芯支撑区域和多个电接触区域,其中在所述引线框结构的表面上至少部分地围绕所述引线框结构的关键部分形成有浅凹槽;
IC管芯,附接于所述管芯支撑区域并且电连接到所述电接触区域;以及
模塑料,密封所述引线框结构的一部分以及所述IC管芯。
8.根据权利要求7的半导体封装体,其中所述关键部分包含管芯接合区域、引线接合区域和湿气敏感区域中的至少一个。
9.根据权利要求7的半导体封装体,其中所述浅凹槽被形成为在所述关键部分的边缘处的台阶。
10.根据权利要求7的半导体封装体,其中将所述浅凹槽被形成为具有所述引线框结构的厚度的约15%到约30%之间的深度。
11.根据权利要求10的半导体封装体,其中所述浅凹槽具有约0.1mm到约0.25mm之间的宽度。
12.根据权利要求7的半导体封装体,其中将所述浅凹槽被形成在所述引线框结构的被刻蚀了一半的部分上方,并且在与所述引线框结构的被刻蚀了一半的部分相对的表面上。
CN2009101405659A 2009-05-08 2009-05-08 用于半导体封装体的引线框 Pending CN101882609A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2009101405659A CN101882609A (zh) 2009-05-08 2009-05-08 用于半导体封装体的引线框
US12/753,118 US20100283135A1 (en) 2009-05-08 2010-04-02 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2009101405659A CN101882609A (zh) 2009-05-08 2009-05-08 用于半导体封装体的引线框

Publications (1)

Publication Number Publication Date
CN101882609A true CN101882609A (zh) 2010-11-10

Family

ID=43054573

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009101405659A Pending CN101882609A (zh) 2009-05-08 2009-05-08 用于半导体封装体的引线框

Country Status (2)

Country Link
US (1) US20100283135A1 (zh)
CN (1) CN101882609A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103066046A (zh) * 2011-10-20 2013-04-24 英特赛尔美国股份有限公司 引脚框架锁定设计部的系统和方法
US9728491B2 (en) 2011-10-20 2017-08-08 Intersil Americas LLC Systems and methods for lead frame locking design features

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6674156B1 (en) * 2001-02-09 2004-01-06 National Semiconductor Corporation Multiple row fine pitch leadless leadframe package with use of half-etch process
US20080093715A1 (en) * 2006-10-18 2008-04-24 Texas Instruments Deutschland Gmbh Leadframe and mold compound interlock in packaged semiconductor device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2570037B2 (ja) * 1990-12-03 1997-01-08 モトローラ・インコーポレイテッド 分離型ヒートシンク・ボンディングパッドを有する半導体パッケージ
US5444293A (en) * 1993-09-22 1995-08-22 Opl Limited Structure and method for providing a lead frame with enhanced solder wetting leads
US5969414A (en) * 1994-05-25 1999-10-19 Advanced Technology Interconnect Incorporated Semiconductor package with molded plastic body
US6046507A (en) * 1997-12-08 2000-04-04 Advanced Micro Devices Electrophoretic coating methodology to improve internal package delamination and wire bond reliability
JP3764587B2 (ja) * 1998-06-30 2006-04-12 富士通株式会社 半導体装置の製造方法
US6847103B1 (en) * 1999-11-09 2005-01-25 Amkor Technology, Inc. Semiconductor package with exposed die pad and body-locking leadframe
JP2002118222A (ja) * 2000-10-10 2002-04-19 Rohm Co Ltd 半導体装置
US7091602B2 (en) * 2002-12-13 2006-08-15 Freescale Semiconductor, Inc. Miniature moldlocks for heatsink or flag for an overmolded plastic package
WO2005022633A1 (en) * 2003-08-29 2005-03-10 Infineon Technologies Ag Chip support of a lead frame for an integrated circuit package
US7834431B2 (en) * 2008-04-08 2010-11-16 Freescale Semiconductor, Inc. Leadframe for packaged electronic device with enhanced mold locking capability
US7667306B1 (en) * 2008-11-12 2010-02-23 Powertech Technology Inc. Leadframe-based semiconductor package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6674156B1 (en) * 2001-02-09 2004-01-06 National Semiconductor Corporation Multiple row fine pitch leadless leadframe package with use of half-etch process
US20080093715A1 (en) * 2006-10-18 2008-04-24 Texas Instruments Deutschland Gmbh Leadframe and mold compound interlock in packaged semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103066046A (zh) * 2011-10-20 2013-04-24 英特赛尔美国股份有限公司 引脚框架锁定设计部的系统和方法
US9728491B2 (en) 2011-10-20 2017-08-08 Intersil Americas LLC Systems and methods for lead frame locking design features
CN103066046B (zh) * 2011-10-20 2017-12-15 英特赛尔美国股份有限公司 引脚框架锁定设计部的系统和方法
US10290564B2 (en) 2011-10-20 2019-05-14 Intersil Americas LLC Systems and methods for lead frame locking design features

Also Published As

Publication number Publication date
US20100283135A1 (en) 2010-11-11

Similar Documents

Publication Publication Date Title
EP1905077B1 (en) Semiconductor device
CN101512762B (zh) 用于半导体电路小片的三维封装的可堆叠封装
US8410585B2 (en) Leadframe and semiconductor package made using the leadframe
CN203983265U (zh) 半导体装置
US9478484B2 (en) Semiconductor packages and methods of formation thereof
KR20060116696A (ko) 리드프레임 및 수지봉입형 반도체장치
JP2005191240A (ja) 半導体装置及びその製造方法
US20180122731A1 (en) Plated ditch pre-mold lead frame, semiconductor package, and method of making same
CN101847626B (zh) 发光装置
KR20150004282A (ko) 반도체 장치
JP4767277B2 (ja) リードフレームおよび樹脂封止型半導体装置
KR20040108582A (ko) 반도체 장치 및 그 제조 방법
CN101882609A (zh) 用于半导体封装体的引线框
CN105374787B (zh) 模制倒装芯片半导体封装体
JP2016201447A (ja) モールドパッケージ
CN103392230A (zh) 半导体装置及半导体装置的制造方法
US7821141B2 (en) Semiconductor device
JP4979661B2 (ja) 半導体装置の製造方法
JP2009065201A (ja) 半導体装置の製造方法
JP4887346B2 (ja) 半導体装置
CN106409694B (zh) 半导体装置及其制造方法
JP2003007933A (ja) 樹脂封止型半導体装置
JP2005311099A (ja) 半導体装置及びその製造方法
US20180025965A1 (en) WFCQFN (Very-Very Thin Flip Chip Quad Flat No Lead) with Embedded Component on Leadframe and Method Therefor
KR100881979B1 (ko) 반사판을 갖는 전력용 엘이디 칩 패키지 및 그 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20101110