[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN101339928A - 半导体元件封装之内联线结构及其方法 - Google Patents

半导体元件封装之内联线结构及其方法 Download PDF

Info

Publication number
CN101339928A
CN101339928A CNA2008101329449A CN200810132944A CN101339928A CN 101339928 A CN101339928 A CN 101339928A CN A2008101329449 A CNA2008101329449 A CN A2008101329449A CN 200810132944 A CN200810132944 A CN 200810132944A CN 101339928 A CN101339928 A CN 101339928A
Authority
CN
China
Prior art keywords
substrate
crystal grain
semiconductor die
die package
package structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2008101329449A
Other languages
English (en)
Other versions
CN101339928B (zh
Inventor
杨文焜
林殿方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yupei Science & Technology Co Ltd
Original Assignee
Yupei Science & Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yupei Science & Technology Co Ltd filed Critical Yupei Science & Technology Co Ltd
Publication of CN101339928A publication Critical patent/CN101339928A/zh
Application granted granted Critical
Publication of CN101339928B publication Critical patent/CN101339928B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01059—Praseodymium [Pr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明揭露一种半导体晶粒封装结构之内联线结构，包含：一基板，具有预先制作之导线于其中；一晶粒，具有接触垫于主动表面；一黏合材质，将该晶粒黏合于该基板之上，其中该基板包含通孔贯穿该基板以及该黏合材质；导电材质填充于该通孔以利于连接该接触垫以及该导线。

Description

半导体元件封装之内联线结构及其方法
【技术领域】
本发明系有关一种半导体封装，特别是关于一种内联线封装结构。
【背景技术】
高效能集成电路封装已是熟知的技术。工业需求趋使集成电路封装之改善以提升其热及电性效能并降低尺寸及制造成本。在半导体组件领域中，组件之密度持续增加，且体积逐渐减小。高密度组件之封装或交互连接技术的需求亦日益增加，以符合上述情况。一般而言，在覆晶接合方法中，焊锡凸块数组系形成于晶粒表面上。焊锡凸块之形成系利用焊锡化合材料配置于焊锡罩幕层，以产生所需焊锡凸块之图案。晶粒封装之功能包含电源分配、讯号分配、散热、保护及支撑等。由于半导体结构趋向复杂化，而一般传统技术，例如导线架封装、软性封装、刚性封装技术，已无法达成于晶粒上产生具有高密度组件之小型晶粒。
通常，BGA封装提供相对于封装表面区域之高密度联线，其包含回旋式讯号路径，传统结构具有高阻抗以及不良散热，因此导致较差散热能力。随着封装密度之增加，将内部组件产生之热导出益形重要。
覆晶技术为电性连接晶粒至黏合基板(例如印刷电路板)之已知电子讯号连接晶粒技术，晶粒主动面受制于复数之电性耦合(习知技术系位于芯片旁侧)。电讯连接位于覆晶之主动表面上以作为端点，凸块包含锡球以及/或铜、金使得其机械与电性连接于基板之上。位于增层后之锡球具有凸块高度约为50-100微米，晶粒反转配置于基板表面，其凸块对准基板之接触垫，如图1所示。若凸块为锡球，则覆晶上之其将被焊于基板接合垫上，锡接合成本不高，但当基于热机械应力超时产生的材料疲劳时将导致电性阻抗增加以及毁损或孔洞。此外，锡球为锡铅合金组成，以铅为基础之材质将因为会产生有毒物质之释放及进入地下水供应等环保考虑而不再受到欢迎。一般，填充材质被用以降低介于芯片与基板间热膨胀所产生之热应力。
再者，由于一般封装技术必须先将晶圆上之晶粒分割为个别晶粒，再将晶粒分别封装，因此上述技术之制程十分费时。因为晶粒封装技术与集成电路之发展有密切关联，因此封装技术以及电子组件之尺寸要求越来越高。基于上述之理由，现今之封装技术已逐渐趋向采用球门阵列封装(BGA)、覆晶球门阵列封装、芯片尺寸封装、晶圆级封装之技术。应可理解「晶圆级封装(WLP)」指晶圆上整体封装及所有内联线结构以及其它制程步骤，系于切割为个别芯片(晶粒)之前进行。一般而言，在完成所有配装制程或封装制程之后，由具有复数半导体晶粒之晶圆中将个别半导体封装分离。上述晶圆级封装具有极小之尺寸及良好之电性。
美国第6,271,469号专利揭露具有重分布层(RDL)124之封装结构，如图2所示。此微电子封装包含微电子晶粒102，具有主动面。封装胶体112配置于晶粒102周遭。其中所述之封装胶体至少具有一表面大致上与晶粒主动表面相当平整。第一介电层118配置于封装胶体112与微电子晶粒102主动面之至少一部分之上。至少一导电层124配置于第一介电层118之上。导电层124电性连接微电子晶粒之主动面。第二介电层126以及第三介电层136分别形成于晶粒102之上。介层穿孔132形成于第二介电层126中以利于耦合导线124。接合垫134连接介层穿孔132以及锡球138配置于接合垫上。
上述传统封装结构以及制程技术牵涉过多堆栈介电层层形成于晶粒/基板表面上以构成增层。其不只需要平坦的主动面化以利于增重分布层制程步骤，更须高精度之光微影设备以完成封装步骤，但其于增层制程期间也易于毁损晶粒表面。主要在于欠缺缓冲层界介于硅晶粒与锡球间，因此此架构造成低良率以及可靠度问题。
因此，本发明提供一种具有内连线结构之覆晶结构以克服上述问题以提供较佳组件效能。
【发明内容】
本发明之一目的系在于提供一种半导体组件封装(芯片构装)，其具有芯片及导线，提供低成本、高效能以及高可靠度封装。
本发明之另一目的系在于提供一种方便、经济的半导体组件封装(芯片构装)之制作方法。
本发明揭露一种半导体晶粒封装结构之内联线结构，包含：一基板，具有预先制作之导线电路于其中；一晶粒，具有接触垫于主动表面；一黏合材质，将该晶粒黏合于该基板之上，其中该基板包含通孔贯穿该基板以及该黏合材质；导电材质填充于该通孔以利于连接该接触垫以及该导线电路。
上述结构更包含核心黏胶位于该晶粒及基板背面或该黏合材质上，以及导电凸块耦合该导线电路；支撑基板位于该核心黏胶之上。导体层位于该核心黏胶及/或该晶粒背面之上。其中该导体层包含铜箔薄片、溅镀或电镀之铜/镍/金合金。
其中更包含斜顶结构之封膜单元，位于该晶粒以及基板或该黏合材质之上，斜顶结构之角度约为水平面起30-60度。其中该封膜单元为液态化合物或封胶化合物。
一种形成半导体晶粒封装之内联线结构之方法，包含：
提供一基板具有导线电路位于其中；
形成黏合材质于基板或晶粒表面(硅晶圆表面)上；
以微对位之置放装置将晶粒配置于该黏合材质之上，以覆晶方式配置；
形成核心黏胶于该晶粒背面，并填入该晶粒周遭空隙；
形成通孔于该基板以曝露接触垫，其亦可于基板程序中预制；
以物理气相沉积或化学气相沉积制作金属种子层于该接触垫上；
形成光阻于该基板/晶粒之上并暴露通孔区域；
以电镀制程制作导电材质于该通孔中，以形成该内联线结构并与该晶粒之接触垫及基板之导线电路耦合。
上述方法更包含形成黏合材质之后热处理该黏合材质；在曝露出金属接触垫之后以干式或湿式清洁该金属接触垫。其中该金属导电包含Ti/Cu，Cu/Au，Cu/Ni/Au或Sn/Ag/Cu。完成内连结构后更包含去除光阻以及回蚀刻该种子金属层。在此例子中，若无金存在于锡球之金属区上面，则形成之光阻可于物理气相沉积之前保护锡球之金属区。
金属种子层包含Ti/Cu，Cu/Au，Cu/Ni/Au或Sn/Ag/Cu。
【附图说明】
图1系为根据先前技术之剖面示意图。
图2系为根据先前技术之剖面示意图。
图3系为根据本发明之剖面示意图。
图4系为根据本发明之剖面示意图。
图5系为根据本发明之剖面示意图。
图6系为根据本发明之示意图。
图7至图10系为根据本发明之制程示意图。
图11系为根据本发明之内连结构剖面示意图。
图中：
先前技术
晶粒102、封装胶体112、第一介电层118、导电层124、第二介电层126、介层穿孔132、接合垫135、第三介电层136、锡球138
本发明
基板100、晶粒105、黏着材质110、内连线结构115、导线120、导电凸块125、核心黏胶130、支撑基板135、导体层140、封膜单元145
【具体实施方式】
本发明将配合其较佳实施例与后附之图式详述于下。应可理解，本发明中之较佳实施例系仅用以说明，而非用以限定本发明。此外，除文中之较佳实施例外，本发明亦可广泛应用于其它实施例，并且本发明并不限定于任何实施例，而应视后附之申请专利范围而定。
本发明揭露一种半导体封装之结构，包含芯片、导线、以及金属内联线结构，如图3所示。
图3系为本发明基板100之截面，基板100可以为金属、玻璃、陶瓷、塑料、PCB或PI。基板100厚度约为40-70微米，其可为单层或多层(导线电路)基板。晶粒105藉由黏着材质110黏于其上，黏着材质110其具有弹性以吸收热应力。黏着材质110得只覆盖晶粒大小之区域。内联线结构115回填形成于基板100内之通孔，得藉由雷射钻孔制作。内联线结构115耦合到芯片105之预定接触垫102，其材质可为铝垫、铜垫或其它金属垫，其系于形成硅晶圆之重分布层后制作。导线120配至于基板100之底部或上部表面，且耦合到内联线结构115。导电凸块125耦合至导线120之末端。
图3所示，导线(布线)120形成于基板底下(或内部)。例如，导线120以金、铜、铜镍或类似材质组成。导线120可以藉由电镀技术、涂布或蚀刻方法制作。铜电镀程序持续进行直到所遇之厚度。导线120延伸出承载晶粒之区域，核心黏胶层(corepaste)130系填充且覆盖晶粒105，并形成于基板100或黏着材质110上。可以藉由树脂、化合物、硅胶或环氧树脂构成。
参阅图4，其显示另一实施例，支撑基板135贴附于核心黏胶层130，以提供封装体之刚性支撑，另一例为导体层140涂布或覆盖于核心黏胶层130上作为散热器。可以藉由银胶粘合铜箔薄片制作、溅镀技术、电镀铜/镍/金制作导体层140，如图5所示。
参阅图6，封膜单元145系利用液态化合物或封胶化合物形成以取代核心黏胶层130。晶粒高度约为50-200微米，自封膜单元145至晶粒表面之尺寸大约30-100微米。基板与粘着材质厚度合计大约40-100微米。因此整个封装体之厚度约为大约120-400微米。值得注意者系为封膜单元145具有斜顶，倾斜结构之角度Θ约为30-60度，进而提供较佳之散热路径。
参阅图7，基板(圆或矩形)100具有电路形成于其内，黏合材质(较好为具有弹性以吸收热应力，基于热膨胀系数介于基板与硅晶粒不匹配问题)110涂布于基板上，随之热处理(预烘烤)该黏合材质110。晶粒105以微对准装置置放于基板100之上，接着进行最终烘烤。下一步骤为自晶粒105背面印刷或涂布核心黏胶层130。基板135一般则是则是利用面板压合技术(panelbonding)使其与晶粒背面相互结合。随之热处理以形成“panelwafer”，如图8所示。下一步骤为使用雷射穿孔技术凿穿通孔(亦可于面板压合前实施)，以及形成金属种子层，随后采用光阻形成通孔及连接至基板电路。随后去除光阻后，使用电镀及蚀刻金属种子层以利于制作内连线结构115。需注意者金属垫可为硅晶圆型态重分布层后之铝垫或其它金属垫，通孔区域非为制作凸块之区域，参图8以及图9。
随后，凸块置于基板之上，且加以红外线热流步骤以制作终端结构，如图10所示。执行面板级(Panel level)测试以及切割所述(PI)基板以及核心黏胶层以分离“panel wafer”为个别单体。
图11系为根据本发明之内联线结构之一实施例，集成电路封装之内联机结构包含晶粒105，具有金属接触垫102位于主动表面，黏合材质110位于晶粒105底面，具有预制电路120之基板100用以承载晶粒105，以及通孔形成于基板100及黏合材质110内，导电材质经由通孔结构115耦合至晶粒105之金属接触垫102以联系基板电路120。
本发明提供简单之制程，无需传统重分布层制程于Panelwafer level中(重分布层意谓导线电路，其预先制作于基板以预防在重分布层制程中损坏芯片)。且本发明无须对准工具，对准图案通常位于基板表面于制作电路过程中。晶粒主动面贴附于基板弹性黏着层，本发明无须底部填充材质，且本发明具有电路之PI基板采大面积面板。且本发明采用简易涂布干式光阻而非湿式光阻，以形成导电材质于通孔区域。晶粒可被封装于其中，只需开孔金属垫区域，因此主动表面受到保护。此架构不但低成本且高良率，且封装体之尺寸极薄(无须锡球高度，硅晶圆易于研磨至非常薄而不会受限于锡球高度因素之考虑)。
本发明也藉由采用弹性黏合层做为缓冲层以释放应力，以提供高可靠度结构。填充金属(铜或锡)全覆盖通孔，以强化机械力。其显示于基板Z方向无热应力冲击，其与目前增层技术截然不同。介于PI基板与PCB母板之热膨胀系数相当，其消除热问题，因此，相较于传统技术，本发明有效克服热管理问题。
本发明结构包括LGA型态封装(终端垫位于封装周边)及球门阵列(BGA)型态封装。
本发明以较佳实施例说明如上，然其并非用以限定本发明所主张之专利权利范围。其专利保护范围当视后附之权利要求及其等同领域而定。凡熟悉此领域之技艺者，在不脱离本专利精神或范围内，所作之更动或润饰，均属于本发明所揭示精神下所完成之等效改变或设计，且应包含在下述之权利要求内。

Claims (10)

1.一种半导体晶粒封装结构之内联线结构，其特征在于包含：
一基板，具有预先制作之导线电路于其中；
一晶粒，具有接触垫于主动表面；
一黏合材质，形成于该基板上以将该晶粒黏合于该基板之上，其中该基板包含通孔贯穿该基板以及该黏合材质；
导电材质填充于该通孔以利于连接该接触垫以及该导线电路。
2.根据权利要求1所述之半导体晶粒封装结构之内联线结构，其特征在于更包含核心黏胶位于该晶粒与该黏合材质上，以及包含导电凸块耦合该导线电路。
3.根据权利要求2所述之半导体晶粒封装结构之内联线结构，其特征在于更包含支撑基板位于该核心黏胶之上。
4.根据权利要求2所述之半导体晶粒封装结构之内联线结构，其特征在于更包含导体层位于该核心黏胶之上。
5.根据权利要求1所述之半导体晶粒封装结构之内联线结构，其特征在于更包含斜顶结构之封膜单元，位于该晶粒、以及该黏合材质之上。
6.根据权利要求5所述之半导体晶粒封装结构之内联线结构，其特征在于该斜顶结构之角度约为30-60度。
7.一种形成半导体晶粒封装结构之内联线结构之方法，其特征在于包含：
提供一基板具有电路于其中；
形成黏合材质于该基板之上；
以微对位之置放装置将晶粒配置于该黏合材质之上，以覆晶方式配置；
形成核心黏胶于该晶粒背面，与填入该晶粒周遭空隙；
形成通孔于该基板以暴露接触垫；
以物理气相沉积或化学气相沉积制作金属种子层于该接触垫上；
形成光阻于该晶粒之上并暴露通孔区域；
以电镀制程制作金属导体于该通孔中，以形成该内联线结构与该接触垫耦合。
8.根据权利要求7所述之形成半导体晶粒封装结构之内联线结构之方法，其特征在于更包含在形成黏合材质之后热处理该黏合材质。
9.根据权利要求7所述之形成半导体晶粒封装结构之内联线结构之方法，其特征在于更包含在曝露该接触垫之后清洁该接触垫。
10.根据权利要求9所述之形成半导体晶粒封装结构之内联线结构之方法，其特征在于更包含在形成该内联机结构之后去除该光阻以及回蚀刻该金属种子层。
CN2008101329449A 2007-07-06 2008-07-02 半导体元件封装之内联线结构及其方法 Expired - Fee Related CN101339928B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/773,993 2007-07-06
US11/773,993 US20090008777A1 (en) 2007-07-06 2007-07-06 Inter-connecting structure for semiconductor device package and method of the same

Publications (2)

Publication Number Publication Date
CN101339928A true CN101339928A (zh) 2009-01-07
CN101339928B CN101339928B (zh) 2011-04-06

Family

ID=40092772

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008101329449A Expired - Fee Related CN101339928B (zh) 2007-07-06 2008-07-02 半导体元件封装之内联线结构及其方法

Country Status (7)

Country Link
US (1) US20090008777A1 (zh)
JP (1) JP2009033153A (zh)
KR (1) KR20090004775A (zh)
CN (1) CN101339928B (zh)
DE (1) DE102008031358A1 (zh)
SG (1) SG148987A1 (zh)
TW (1) TWI344199B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102315187A (zh) * 2010-03-03 2012-01-11 育霈科技股份有限公司 导体封装结构

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8446243B2 (en) * 2008-10-31 2013-05-21 Infineon Technologies Austria Ag Method of constructing inductors and transformers
US20130214418A1 (en) * 2012-01-12 2013-08-22 King Dragon International Inc. Semiconductor Device Package with Slanting Structures
US20130181227A1 (en) * 2012-01-12 2013-07-18 King Dragon International Inc. LED Package with Slanting Structure and Method of the Same
CN102867759B (zh) * 2012-08-17 2015-04-29 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
TWI492344B (zh) * 2013-04-09 2015-07-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9331038B2 (en) 2013-08-29 2016-05-03 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor interconnect structure
US9859265B2 (en) * 2014-06-06 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming the same
US10043769B2 (en) 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
KR102492733B1 (ko) 2017-09-29 2023-01-27 삼성디스플레이 주식회사 구리 플라즈마 식각 방법 및 디스플레이 패널 제조 방법
US11404365B2 (en) * 2019-05-07 2022-08-02 International Business Machines Corporation Direct attachment of capacitors to flip chip dies
CN114496986A (zh) * 2022-02-10 2022-05-13 成都天成电科科技有限公司 超宽带晶圆级封装匹配结构

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6069407A (en) * 1998-11-18 2000-05-30 Vlsi Technology, Inc. BGA package using PCB and tape in a die-up configuration
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6569712B2 (en) * 2001-10-19 2003-05-27 Via Technologies, Inc. Structure of a ball-grid array package substrate and processes for producing thereof
SG115455A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Methods for assembly and packaging of flip chip configured dice with interposer
US20040088855A1 (en) * 2002-11-11 2004-05-13 Salman Akram Interposers for chip-scale packages, chip-scale packages including the interposers, test apparatus for effecting wafer-level testing of the chip-scale packages, and methods
US7309622B2 (en) * 2005-02-14 2007-12-18 Stats Chippac Ltd. Integrated circuit package system with heat sink
US20070096285A1 (en) * 2005-11-02 2007-05-03 Chin-Tien Chiu Semiconductor die package including construction for preventing delamination and/or cracking of the semiconductor die

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102315187A (zh) * 2010-03-03 2012-01-11 育霈科技股份有限公司 导体封装结构

Also Published As

Publication number Publication date
CN101339928B (zh) 2011-04-06
TW200903763A (en) 2009-01-16
JP2009033153A (ja) 2009-02-12
SG148987A1 (en) 2009-01-29
KR20090004775A (ko) 2009-01-12
DE102008031358A1 (de) 2009-01-08
TWI344199B (en) 2011-06-21
US20090008777A1 (en) 2009-01-08

Similar Documents

Publication Publication Date Title
CN101339928B (zh) 半导体元件封装之内联线结构及其方法
CN104882416B (zh) 具有堆叠式封装能力的半导体封装件及其制作方法
TWI533412B (zh) 半導體元件封裝結構及其形成方法
US10177130B2 (en) Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener
US7422978B2 (en) Methods of manufacturing interposers with flexible solder pad elements
TWI460845B (zh) 具有區域陣列單元連接器之可堆疊模製微電子封裝
TWI604591B (zh) 薄型扇出式多晶片堆疊封裝構造及其製造方法
TWI409923B (zh) 具有晶粒埋入式以及雙面覆蓋重增層之基板結構及其方法
US20090166873A1 (en) Inter-connecting structure for semiconductor device package and method of the same
US9230901B2 (en) Semiconductor device having chip embedded in heat spreader and electrically connected to interposer and method of manufacturing the same
JP2019512168A (ja) シリコン基板に埋め込まれたファンアウト型の３ｄパッケージ構造
TW200931628A (en) Stacking die package structure for semiconductor devices and method of the same
CN101252125A (zh) 具减缩结构的复数晶粒封装结构与其形成方法
TW200921884A (en) Method for making copper-core layer multi-layer encapsulation substrate
TW201110309A (en) Stacking package structure with chip embedded inside and die having through silicon via and method of the same
CN111508912A (zh) 功率覆盖结构及其制作方法
CN106711105A (zh) 覆盖金属层填充孔或槽的封装结构及制作方法
CN102034768B (zh) 具有晶粒埋入式以及双面覆盖重增层的基板结构及其方法
CN101740551A (zh) 用于半导体元件的叠层晶粒封装结构及其方法
CN206558490U (zh) 覆盖金属层填充孔或槽的封装结构
US6586829B1 (en) Ball grid array package
WO2022037147A1 (zh) 扇出型封装结构及其制造方法
TW200921889A (en) Package on package structure for semiconductor devices and method of the same
CN103887256A (zh) 一种高散热芯片嵌入式电磁屏蔽封装结构及其制作方法
CN113990815A (zh) 一种硅基微模组塑封结构及其制备方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110406